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clk: rockchip: add clock ids for i2s_src on RK3366

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Set the newly added id for i2s_src, so that they can be called
in other parts.

Change-Id: Ie4ecc4d19e3ae64a07d1f2a80aa08d40f38d09ad
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao 2016-06-21 18:07:39 +08:00 committed by Huang, Tao
parent 006efbdf39
commit c32d8b0ebe
2 changed files with 6 additions and 3 deletions
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6
drivers/clk/rockchip/clk-rk3366.c
View File

@ -299,7 +299,7 @@ static struct rockchip_clk_branch rk3366_clk_branches[] __initdata = {
RK3368_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK3368_CLKGATE_CON(1), 3, GFLAGS),
COMPOSITE(0, "i2s_8ch_src", mux_pll_src_cpll_gpll_p, 0,
COMPOSITE(SCLK_I2S_8CH_SRC, "i2s_8ch_src", mux_pll_src_cpll_gpll_p, 0,
RK3368_CLKSEL_CON(27), 12, 1, MFLAGS, 0, 7, DFLAGS,
RK3368_CLKGATE_CON(6), 1, GFLAGS),
COMPOSITE_FRACMUX(0, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT,
@ -312,7 +312,7 @@ static struct rockchip_clk_branch rk3366_clk_branches[] __initdata = {
GATE(SCLK_I2S_8CH, "sclk_i2s_8ch", "i2s_8ch_pre", CLK_SET_RATE_PARENT,
RK3368_CLKGATE_CON(6), 3, GFLAGS),
COMPOSITE(0, "spdif_8ch_src", mux_pll_src_cpll_gpll_p, 0,
COMPOSITE(SCLK_SPDIF_8CH_SRC, "spdif_8ch_src", mux_pll_src_cpll_gpll_p, 0,
RK3368_CLKSEL_CON(31), 12, 1, MFLAGS, 0, 7, DFLAGS,
RK3368_CLKGATE_CON(6), 4, GFLAGS),
COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT,
@ -322,7 +322,7 @@ static struct rockchip_clk_branch rk3366_clk_branches[] __initdata = {
GATE(SCLK_SPDIF_8CH, "sclk_spdif_8ch", "spdif_8ch_mux", CLK_SET_RATE_PARENT,
RK3368_CLKGATE_CON(6), 6, GFLAGS),
COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0,
COMPOSITE(SCLK_I2S_2CH_SRC, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0,
RK3368_CLKSEL_CON(53), 12, 1, MFLAGS, 0, 7, DFLAGS,
RK3368_CLKGATE_CON(5), 13, GFLAGS),
COMPOSITE_FRACMUX(0, "i2s_2ch_frac", "i2s_2ch_src", CLK_SET_RATE_PARENT,

3
include/dt-bindings/clock/rk3366-cru.h
View File

@ -96,6 +96,9 @@
#define SCLK_MPLL_SRC 130
#define SCLK_32K_INTR 131
#define SCLK_32K 132
#define SCLK_I2S_8CH_SRC 133
#define SCLK_I2S_2CH_SRC 134
#define SCLK_SPDIF_8CH_SRC 135
#define DCLK_VOP_FULL 170
#define DCLK_VOP_LITE 171