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RISC-V Fixes for 6.15-rc4
* A fix for a missing icache flush in uprobes, which manifests as at least a BFF selftest failure on the Spacemit X1. * A workaround for build warnings in flush_icache_range(). -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmgLvt0THHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYiSXTEACYyBa3WiAywufa8qeMli8s5McgIp76 WQhTakhp2/2KWegbFfn4+ugvY9NhpY3CGGESJPo1tgHvvDh6kceVEV1jqVuQuPBl IEh4NImUc9UvimL9QhqsIEkGiF3lTSB+gsmp9VE/tk2BsPcq07oJgtTCaB87JQND mLpcBkHSu8T6YbN7ZM8XSVc0sbvTEzKFGBtXyVu5y/7OehiNXeFKVIZ1Qdv1tBf/ QbfC43UBQ++mO7v6QTDy7BwWcBR3r6EBR/rLxutjyefhXNwHQVEGk2WP9pIVcc2P B4nihfiCfDFCwijgRQFtH54Cwdxr253bdci5tEw640hQCRHAJSVXKjjdxcdX9FXm qlXyXDgmDXUqGR5gC34i1eUT+ahjyvOeS39SJbE2QT8ZRbNRXIU6KNN9sO6h5x7P sN6pJin04nT0No9ADGnUza7rtVlEgCpM1KYTOVgVltHYJ5PtSdHv1dIiYjqlJx7G LaAbs93FUE6f7aJd6un/RMAb6g9sCu2GnDTU+iivU4IKRXQ+Bf1LSEst3lYNxMln r6o7jg0ZZFa9cqBKGVl4G74YOBzRi5wzlwtJsxo7uA3tc0WnlFVVSZv6lryGYR1S e8dMttYDQ+vpWrP5Qvo55YnebRt3khmxcWbVTcA8EBiX5cPHAvo456JBby7h7vqU BA8wEj0K7O/+Eg== =SrfS -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-6.15-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V fixes from Palmer Dabbelt: - A fix for a missing icache flush in uprobes, which manifests as at least a BFF selftest failure on the Spacemit X1 - A workaround for build warnings in flush_icache_range() * tag 'riscv-for-linus-6.15-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: riscv: uprobes: Add missing fence.i after building the XOL buffer riscv: Replace function-like macro by static inline function
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c3137514f1
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@ -34,11 +34,6 @@ static inline void flush_dcache_page(struct page *page)
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flush_dcache_folio(page_folio(page));
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}
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/*
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* RISC-V doesn't have an instruction to flush parts of the instruction cache,
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* so instead we just flush the whole thing.
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*/
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#define flush_icache_range(start, end) flush_icache_all()
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#define flush_icache_user_page(vma, pg, addr, len) \
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do { \
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if (vma->vm_flags & VM_EXEC) \
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@ -78,6 +73,16 @@ void flush_icache_mm(struct mm_struct *mm, bool local);
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#endif /* CONFIG_SMP */
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/*
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* RISC-V doesn't have an instruction to flush parts of the instruction cache,
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* so instead we just flush the whole thing.
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*/
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#define flush_icache_range flush_icache_range
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static inline void flush_icache_range(unsigned long start, unsigned long end)
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{
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flush_icache_all();
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}
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extern unsigned int riscv_cbom_block_size;
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extern unsigned int riscv_cboz_block_size;
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void riscv_init_cbo_blocksizes(void);
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@ -167,6 +167,7 @@ void arch_uprobe_copy_ixol(struct page *page, unsigned long vaddr,
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/* Initialize the slot */
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void *kaddr = kmap_atomic(page);
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void *dst = kaddr + (vaddr & ~PAGE_MASK);
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unsigned long start = (unsigned long)dst;
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memcpy(dst, src, len);
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@ -176,13 +177,6 @@ void arch_uprobe_copy_ixol(struct page *page, unsigned long vaddr,
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*(uprobe_opcode_t *)dst = __BUG_INSN_32;
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}
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flush_icache_range(start, start + len);
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kunmap_atomic(kaddr);
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/*
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* We probably need flush_icache_user_page() but it needs vma.
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* This should work on most of architectures by default. If
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* architecture needs to do something different it can define
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* its own version of the function.
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*/
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flush_dcache_page(page);
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}
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