From c2caac3167f2f8e8f136f7be844ee3ab0456f03c Mon Sep 17 00:00:00 2001
From: Zefa Chen <zefa.chen@rock-chips.com>
Date: Wed, 9 Mar 2022 09:35:51 +0800
Subject: [PATCH] ARM: dts: rockchip: add csidphy for rv1106

Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: Ia6d4dbadba3367758bf66f9b30022c5901f2143a
---
 arch/arm/boot/dts/rv1106.dtsi | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/arch/arm/boot/dts/rv1106.dtsi b/arch/arm/boot/dts/rv1106.dtsi
index 04d0c175cf2e..f5cb992c3597 100644
--- a/arch/arm/boot/dts/rv1106.dtsi
+++ b/arch/arm/boot/dts/rv1106.dtsi
@@ -20,6 +20,9 @@ / {
 	interrupt-parent = <&gic>;
 
 	aliases {
+		csi2dphy0 = &csi2_dphy0;
+		csi2dphy1 = &csi2_dphy1;
+		csi2dphy2 = &csi2_dphy2;
 		ethernet0 = &gmac;
 		gpio0 = &gpio0;
 		gpio1 = &gpio1;
@@ -67,6 +70,27 @@ cpuinfo {
 		nvmem-cell-names = "id", "cpu-version", "cpu-code";
 	};
 
+	/* dphy0 full mode */
+	csi2_dphy0: csi2-dphy0 {
+		compatible = "rockchip,rv1106-csi2-dphy";
+		rockchip,hw = <&csi2_dphy_hw>;
+		status = "disabled";
+	};
+
+	/* dphy1 split mode 01 */
+	csi2_dphy1: csi2-dphy1 {
+		compatible = "rockchip,rv1106-csi2-dphy";
+		rockchip,hw = <&csi2_dphy_hw>;
+		status = "disabled";
+	};
+
+	/* dphy2 split mode 23 */
+	csi2_dphy2: csi2-dphy2 {
+		compatible = "rockchip,rv1106-csi2-dphy";
+		rockchip,hw = <&csi2_dphy_hw>;
+		status = "disabled";
+	};
+
 	display_subsystem: display-subsystem {
 		compatible = "rockchip,display-subsystem";
 		ports = <&vop_out>;
@@ -506,6 +530,17 @@ u2phy_otg: otg-port {
 		};
 	};
 
+	csi2_dphy_hw: csi2-dphy-hw@ff3e8000 {
+		compatible = "rockchip,rv1106-csi2-dphy-hw";
+		reg = <0xff3e8000 0x8000>;
+		clocks = <&cru PCLK_MIPICSIPHY>;
+		clock-names = "pclk";
+		resets = <&cru SRST_P_MIPICSIPHY>;
+		reset-names = "srst_p_csiphy";
+		rockchip,grf = <&grf>;
+		status = "disabled";
+	};
+
 	dmac: dma-controller@ff420000 {
 		compatible = "arm,pl330", "arm,primecell";
 		reg = <0xff420000 0x4000>;