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arm64: dts: freescale: add missing cache properties

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As all level 2 and level 3 caches are unified, add required
cache-unified properties to fix warnings like:

  fsl-ls2080a-simu.dtb: l2-cache3: 'cache-unified' is a required property

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Krzysztof Kozlowski 2023-04-22 00:32:06 +02:00 committed by Shawn Guo
parent d2bd947176
commit c290d09a99
5 changed files with 11 additions and 0 deletions
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1
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
View File

@ -47,6 +47,7 @@ cpu1: cpu@1 {
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

1
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
View File

@ -85,6 +85,7 @@ cpu3: cpu@3 {
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

1
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
View File

@ -80,6 +80,7 @@ cpu3: cpu@3 {
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

4
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
View File

@ -96,21 +96,25 @@ cpu7: cpu@301 {
cluster0_l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
CPU_PW20: cpu-pw20 {

4
arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
View File

@ -96,21 +96,25 @@ cpu7: cpu@301 {
cluster0_l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
CPU_PW20: cpu-pw20 {