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i2c: imx: add I2C_M_REV_DIR_ADDR and I2C_M_NOSTART
The Realtek RTL8366SE SMI read frame per: S Addr Rd [A] reg[7:0] [A] reg[15:8] [A] [data[7:0]] A [data[15:8]] NA P Linux support it using I2C_M_REV_DIR_ADDR on a write message that inverts the transmitted R/W bit, and I2C_M_NOSTART on the following read message that continues the frame without re-addressing. This NXP i2c-imx is missing such support, so on an LX2160A the Realtek switch could not be used. Signed-off-by: Vincent Jardin <vjardin@free.fr> Acked-by: Carlos Song <carlos.song@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Andi Shyti <andi.shyti@kernel.org> Link: https://patch.msgid.link/20261023-for-upstream-i2c-imx-lx2160-reverse-v3-1-a07b249df381@free.fr
This commit is contained in:
Vincent Jardin
Andi Shyti
parent
b7fd977fec
commit
c2867bb0fa
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@ -1000,16 +1000,10 @@ static inline int i2c_imx_isr_write(struct imx_i2c_struct *i2c_imx)
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return 1;
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}
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static inline int i2c_imx_isr_read(struct imx_i2c_struct *i2c_imx)
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static inline void i2c_imx_setup_read(struct imx_i2c_struct *i2c_imx)
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{
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int result;
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unsigned int temp;
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result = i2c_imx_isr_acked(i2c_imx);
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if (result)
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return result;
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/* setup bus to read data */
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temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
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temp &= ~I2CR_MTX;
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if ((i2c_imx->msg->len - 1) || (i2c_imx->msg->flags & I2C_M_RECV_LEN))
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@ -1017,6 +1011,18 @@ static inline int i2c_imx_isr_read(struct imx_i2c_struct *i2c_imx)
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imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
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imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
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}
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static inline int i2c_imx_isr_read(struct imx_i2c_struct *i2c_imx)
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{
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int result;
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result = i2c_imx_isr_acked(i2c_imx);
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if (result)
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return result;
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/* setup bus to read data */
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i2c_imx_setup_read(i2c_imx);
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return 0;
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}
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@ -1172,6 +1178,16 @@ static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
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return i2c_imx_master_isr(i2c_imx, status);
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}
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static u8 i2c_imx_addr_byte(struct i2c_msg *msg)
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{
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u8 addr = i2c_8bit_addr_from_msg(msg);
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if (msg->flags & I2C_M_REV_DIR_ADDR)
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addr ^= 1;
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return addr;
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}
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static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
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struct i2c_msg *msgs)
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{
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@ -1200,7 +1216,7 @@ static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
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* Write slave address.
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* The first byte must be transmitted by the CPU.
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*/
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imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
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imx_i2c_write_reg(i2c_imx_addr_byte(msgs), i2c_imx, IMX_I2C_I2DR);
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time_left = wait_for_completion_timeout(
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&i2c_imx->dma->cmd_complete,
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msecs_to_jiffies(DMA_TIMEOUT));
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@ -1242,14 +1258,20 @@ static int i2c_imx_prepare_read(struct imx_i2c_struct *i2c_imx,
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int result;
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unsigned int temp = 0;
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/* write slave address */
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imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
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result = i2c_imx_trx_complete(i2c_imx, !use_dma);
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if (result)
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return result;
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result = i2c_imx_acked(i2c_imx);
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if (result)
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return result;
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/*
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* I2C_M_NOSTART continues a frame that is already open, so there is
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* no address phase: go straight to turning the bus around.
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*/
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if (!(msgs->flags & I2C_M_NOSTART)) {
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/* write slave address */
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imx_i2c_write_reg(i2c_imx_addr_byte(msgs), i2c_imx, IMX_I2C_I2DR);
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result = i2c_imx_trx_complete(i2c_imx, !use_dma);
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if (result)
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return result;
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result = i2c_imx_acked(i2c_imx);
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if (result)
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return result;
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}
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dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
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@ -1371,16 +1393,18 @@ static int i2c_imx_atomic_write(struct imx_i2c_struct *i2c_imx,
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int i, result;
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dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
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__func__, i2c_8bit_addr_from_msg(msgs));
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__func__, i2c_imx_addr_byte(msgs));
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/* write slave address */
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imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
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result = i2c_imx_trx_complete(i2c_imx, true);
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if (result)
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return result;
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result = i2c_imx_acked(i2c_imx);
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if (result)
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return result;
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if (!(msgs->flags & I2C_M_NOSTART)) {
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/* write slave address */
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imx_i2c_write_reg(i2c_imx_addr_byte(msgs), i2c_imx, IMX_I2C_I2DR);
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result = i2c_imx_trx_complete(i2c_imx, true);
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if (result)
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return result;
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result = i2c_imx_acked(i2c_imx);
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if (result)
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return result;
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}
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dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
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/* write data */
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@ -1402,7 +1426,7 @@ static int i2c_imx_atomic_write(struct imx_i2c_struct *i2c_imx,
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static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
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{
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dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
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__func__, i2c_8bit_addr_from_msg(msgs));
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__func__, i2c_imx_addr_byte(msgs));
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i2c_imx->state = IMX_I2C_STATE_WRITE;
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i2c_imx->msg = msgs;
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@ -1411,8 +1435,16 @@ static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
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/*
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* By writing the device address we start the state machine in the ISR.
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* The ISR will report when it is done or when it fails.
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*
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* I2C_M_NOSTART continues a frame that is already open and so has no
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* address byte: push the first data byte instead. That raises the same
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* interrupt and the ISR carries on from the second byte.
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*/
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imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
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if (msgs->flags & I2C_M_NOSTART)
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imx_i2c_write_reg(msgs->buf[i2c_imx->msg_buf_idx++], i2c_imx,
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IMX_I2C_I2DR);
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else
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imx_i2c_write_reg(i2c_imx_addr_byte(msgs), i2c_imx, IMX_I2C_I2DR);
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wait_event_timeout(i2c_imx->queue,
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i2c_imx->state == IMX_I2C_STATE_DONE ||
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i2c_imx->state == IMX_I2C_STATE_FAILED,
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@ -1529,22 +1561,29 @@ static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs,
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dev_dbg(&i2c_imx->adapter.dev,
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"<%s> write slave address: addr=0x%x\n",
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__func__, i2c_8bit_addr_from_msg(msgs));
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__func__, i2c_imx_addr_byte(msgs));
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i2c_imx->is_lastmsg = is_lastmsg;
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if (block_data)
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i2c_imx->state = IMX_I2C_STATE_READ_BLOCK_DATA;
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else
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i2c_imx->state = IMX_I2C_STATE_READ;
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i2c_imx->msg = msgs;
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i2c_imx->msg_buf_idx = 0;
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/*
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* By writing the device address we start the state machine in the ISR.
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* The ISR will report when it is done or when it fails.
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*/
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imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
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if (msgs->flags & I2C_M_NOSTART) {
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i2c_imx->state = block_data ? IMX_I2C_STATE_READ_BLOCK_DATA_LEN
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: IMX_I2C_STATE_READ_CONTINUE;
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i2c_imx_setup_read(i2c_imx);
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} else {
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if (block_data)
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i2c_imx->state = IMX_I2C_STATE_READ_BLOCK_DATA;
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else
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i2c_imx->state = IMX_I2C_STATE_READ;
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/*
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* By writing the device address we start the state machine in the ISR.
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* The ISR will report when it is done or when it fails.
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*/
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imx_i2c_write_reg(i2c_imx_addr_byte(msgs), i2c_imx, IMX_I2C_I2DR);
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}
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wait_event_timeout(i2c_imx->queue,
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i2c_imx->state == IMX_I2C_STATE_DONE ||
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i2c_imx->state == IMX_I2C_STATE_FAILED,
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@ -1574,6 +1613,37 @@ static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs,
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return ret;
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}
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#define I2C_IMX_UNSUPPORTED_PROTOCOL_MANGLING_FLAGS \
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(I2C_M_IGNORE_NAK | I2C_M_NO_RD_ACK | I2C_M_STOP)
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static int i2c_imx_check_msgs(struct i2c_msg *msgs, int num)
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{
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int i;
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for (i = 0; i < num; i++) {
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/* Reject rather than silently transfer */
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if (msgs[i].flags & I2C_IMX_UNSUPPORTED_PROTOCOL_MANGLING_FLAGS)
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return -EOPNOTSUPP;
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if (msgs[i].flags & I2C_M_NOSTART) {
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/*
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* NOSTART continues an already open frame. The first
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* message has nothing to continue from,
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* a 0 length continuation leaves the controller with
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* no byte to clock.
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*/
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if (i == 0 || msgs[i].len == 0)
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return -EOPNOTSUPP;
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if ((msgs[i].flags & I2C_M_RD) &&
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(msgs[i - 1].flags & I2C_M_RD))
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return -EOPNOTSUPP;
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}
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}
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return 0;
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}
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static int i2c_imx_xfer_common(struct i2c_adapter *adapter,
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struct i2c_msg *msgs, int num, bool atomic)
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{
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@ -1583,6 +1653,10 @@ static int i2c_imx_xfer_common(struct i2c_adapter *adapter,
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struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
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int use_dma = 0;
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result = i2c_imx_check_msgs(msgs, num);
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if (result)
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return result;
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/* Start I2C transfer */
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result = i2c_imx_start(i2c_imx, atomic);
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if (result) {
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@ -1604,7 +1678,7 @@ static int i2c_imx_xfer_common(struct i2c_adapter *adapter,
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if (i == num - 1)
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is_lastmsg = true;
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if (i) {
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if (i && !(msgs[i].flags & I2C_M_NOSTART)) {
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dev_dbg(&i2c_imx->adapter.dev,
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"<%s> repeated start\n", __func__);
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temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
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@ -1636,7 +1710,8 @@ static int i2c_imx_xfer_common(struct i2c_adapter *adapter,
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#endif
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use_dma = i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD &&
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msgs[i].flags & I2C_M_DMA_SAFE;
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msgs[i].flags & I2C_M_DMA_SAFE &&
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!(msgs[i].flags & I2C_M_NOSTART);
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if (msgs[i].flags & I2C_M_RD) {
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int block_data = msgs->flags & I2C_M_RECV_LEN;
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@ -1730,7 +1805,9 @@ static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx,
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static u32 i2c_imx_func(struct i2c_adapter *adapter)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
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| I2C_FUNC_SMBUS_READ_BLOCK_DATA;
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| I2C_FUNC_SMBUS_READ_BLOCK_DATA
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| I2C_FUNC_NOSTART
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| I2C_FUNC_PROTOCOL_MANGLING;
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}
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static const struct i2c_algorithm i2c_imx_algo = {
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