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drm/panthor: Introduce panthor_pwr API and power control framework
Add the new panthor_pwr module, which provides basic power control management for Mali-G1 GPUs. The initial implementation includes infrastructure for initializing the PWR_CONTROL block, requesting and handling its IRQ, and checking for PWR_CONTROL support based on GPU architecture. The patch also integrates panthor_pwr with the device lifecycle (init, suspend, resume, and unplug) through the new API functions. It also registers the IRQ handler under the 'gpu' IRQ as the PWR_CONTROL block is located within the GPU_CONTROL block. Reviewed-by: Steven Price <steven.price@arm.com> Signed-off-by: Karunika Choo <karunika.choo@arm.com> Link: https://patch.msgid.link/20251125125548.3282320-4-karunika.choo@arm.com Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
This commit is contained in:
Karunika Choo
Boris Brezillon
parent
7d334f5c0b
commit
c27787f2b7
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@ -10,6 +10,7 @@ panthor-y := \
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panthor_heap.o \
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panthor_hw.o \
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panthor_mmu.o \
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panthor_pwr.o \
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panthor_sched.o
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obj-$(CONFIG_DRM_PANTHOR) += panthor.o
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@ -21,6 +21,7 @@
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#include "panthor_gpu.h"
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#include "panthor_hw.h"
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#include "panthor_mmu.h"
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#include "panthor_pwr.h"
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#include "panthor_regs.h"
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#include "panthor_sched.h"
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@ -113,6 +114,7 @@ void panthor_device_unplug(struct panthor_device *ptdev)
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panthor_fw_unplug(ptdev);
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panthor_mmu_unplug(ptdev);
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panthor_gpu_unplug(ptdev);
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panthor_pwr_unplug(ptdev);
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pm_runtime_dont_use_autosuspend(ptdev->base.dev);
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pm_runtime_put_sync_suspend(ptdev->base.dev);
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@ -268,10 +270,14 @@ int panthor_device_init(struct panthor_device *ptdev)
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if (ret)
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goto err_rpm_put;
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ret = panthor_gpu_init(ptdev);
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ret = panthor_pwr_init(ptdev);
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if (ret)
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goto err_rpm_put;
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ret = panthor_gpu_init(ptdev);
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if (ret)
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goto err_unplug_pwr;
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ret = panthor_gpu_coherency_init(ptdev);
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if (ret)
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goto err_unplug_gpu;
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@ -312,6 +318,9 @@ int panthor_device_init(struct panthor_device *ptdev)
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err_unplug_gpu:
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panthor_gpu_unplug(ptdev);
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err_unplug_pwr:
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panthor_pwr_unplug(ptdev);
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err_rpm_put:
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pm_runtime_put_sync_suspend(ptdev->base.dev);
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return ret;
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@ -465,6 +474,7 @@ static int panthor_device_resume_hw_components(struct panthor_device *ptdev)
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{
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int ret;
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panthor_pwr_resume(ptdev);
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panthor_gpu_resume(ptdev);
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panthor_mmu_resume(ptdev);
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@ -474,6 +484,7 @@ static int panthor_device_resume_hw_components(struct panthor_device *ptdev)
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panthor_mmu_suspend(ptdev);
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panthor_gpu_suspend(ptdev);
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panthor_pwr_suspend(ptdev);
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return ret;
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}
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@ -587,6 +598,7 @@ int panthor_device_suspend(struct device *dev)
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panthor_fw_suspend(ptdev);
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panthor_mmu_suspend(ptdev);
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panthor_gpu_suspend(ptdev);
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panthor_pwr_suspend(ptdev);
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drm_dev_exit(cookie);
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}
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@ -29,6 +29,7 @@ struct panthor_job;
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struct panthor_mmu;
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struct panthor_fw;
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struct panthor_perfcnt;
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struct panthor_pwr;
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struct panthor_vm;
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struct panthor_vm_pool;
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@ -138,6 +139,9 @@ struct panthor_device {
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/** @hw: GPU-specific data. */
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struct panthor_hw *hw;
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/** @pwr: Power control management data. */
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struct panthor_pwr *pwr;
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/** @gpu: GPU management data. */
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struct panthor_gpu *gpu;
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@ -5,6 +5,7 @@
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#define __PANTHOR_HW_H__
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#include "panthor_device.h"
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#include "panthor_regs.h"
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/**
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* struct panthor_hw_ops - HW operations that are specific to a GPU
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@ -47,4 +48,9 @@ static inline void panthor_hw_l2_power_off(struct panthor_device *ptdev)
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ptdev->hw->ops.l2_power_off(ptdev);
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}
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static inline bool panthor_hw_has_pwr_ctrl(struct panthor_device *ptdev)
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{
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return GPU_ARCH_MAJOR(ptdev->gpu_info.gpu_id) >= 14;
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}
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#endif /* __PANTHOR_HW_H__ */
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121
drivers/gpu/drm/panthor/panthor_pwr.c
Normal file
121
drivers/gpu/drm/panthor/panthor_pwr.c
Normal file
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@ -0,0 +1,121 @@
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// SPDX-License-Identifier: GPL-2.0 or MIT
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/* Copyright 2025 ARM Limited. All rights reserved. */
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/iopoll.h>
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#include <linux/wait.h>
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#include <drm/drm_managed.h>
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#include <drm/drm_print.h>
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#include "panthor_device.h"
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#include "panthor_hw.h"
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#include "panthor_pwr.h"
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#include "panthor_regs.h"
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#define PWR_INTERRUPTS_MASK \
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(PWR_IRQ_POWER_CHANGED_SINGLE | \
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PWR_IRQ_POWER_CHANGED_ALL | \
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PWR_IRQ_DELEGATION_CHANGED | \
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PWR_IRQ_RESET_COMPLETED | \
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PWR_IRQ_RETRACT_COMPLETED | \
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PWR_IRQ_INSPECT_COMPLETED | \
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PWR_IRQ_COMMAND_NOT_ALLOWED | \
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PWR_IRQ_COMMAND_INVALID)
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/**
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* struct panthor_pwr - PWR_CONTROL block management data.
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*/
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struct panthor_pwr {
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/** @irq: PWR irq. */
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struct panthor_irq irq;
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/** @reqs_lock: Lock protecting access to pending_reqs. */
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spinlock_t reqs_lock;
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/** @pending_reqs: Pending PWR requests. */
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u32 pending_reqs;
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/** @reqs_acked: PWR request wait queue. */
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wait_queue_head_t reqs_acked;
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};
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static void panthor_pwr_irq_handler(struct panthor_device *ptdev, u32 status)
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{
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spin_lock(&ptdev->pwr->reqs_lock);
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gpu_write(ptdev, PWR_INT_CLEAR, status);
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if (unlikely(status & PWR_IRQ_COMMAND_NOT_ALLOWED))
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drm_err(&ptdev->base, "PWR_IRQ: COMMAND_NOT_ALLOWED");
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if (unlikely(status & PWR_IRQ_COMMAND_INVALID))
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drm_err(&ptdev->base, "PWR_IRQ: COMMAND_INVALID");
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if (status & ptdev->pwr->pending_reqs) {
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ptdev->pwr->pending_reqs &= ~status;
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wake_up_all(&ptdev->pwr->reqs_acked);
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}
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spin_unlock(&ptdev->pwr->reqs_lock);
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}
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PANTHOR_IRQ_HANDLER(pwr, PWR, panthor_pwr_irq_handler);
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void panthor_pwr_unplug(struct panthor_device *ptdev)
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{
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unsigned long flags;
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if (!ptdev->pwr)
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return;
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/* Make sure the IRQ handler is not running after that point. */
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panthor_pwr_irq_suspend(&ptdev->pwr->irq);
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/* Wake-up all waiters. */
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spin_lock_irqsave(&ptdev->pwr->reqs_lock, flags);
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ptdev->pwr->pending_reqs = 0;
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wake_up_all(&ptdev->pwr->reqs_acked);
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spin_unlock_irqrestore(&ptdev->pwr->reqs_lock, flags);
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}
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int panthor_pwr_init(struct panthor_device *ptdev)
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{
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struct panthor_pwr *pwr;
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int err, irq;
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if (!panthor_hw_has_pwr_ctrl(ptdev))
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return 0;
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pwr = drmm_kzalloc(&ptdev->base, sizeof(*pwr), GFP_KERNEL);
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if (!pwr)
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return -ENOMEM;
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spin_lock_init(&pwr->reqs_lock);
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init_waitqueue_head(&pwr->reqs_acked);
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ptdev->pwr = pwr;
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irq = platform_get_irq_byname(to_platform_device(ptdev->base.dev), "gpu");
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if (irq < 0)
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return irq;
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err = panthor_request_pwr_irq(ptdev, &pwr->irq, irq, PWR_INTERRUPTS_MASK);
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if (err)
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return err;
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return 0;
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}
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void panthor_pwr_suspend(struct panthor_device *ptdev)
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{
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if (!ptdev->pwr)
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return;
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panthor_pwr_irq_suspend(&ptdev->pwr->irq);
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}
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void panthor_pwr_resume(struct panthor_device *ptdev)
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{
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if (!ptdev->pwr)
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return;
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panthor_pwr_irq_resume(&ptdev->pwr->irq, PWR_INTERRUPTS_MASK);
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}
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17
drivers/gpu/drm/panthor/panthor_pwr.h
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17
drivers/gpu/drm/panthor/panthor_pwr.h
Normal file
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@ -0,0 +1,17 @@
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/* SPDX-License-Identifier: GPL-2.0 or MIT */
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/* Copyright 2025 ARM Limited. All rights reserved. */
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#ifndef __PANTHOR_PWR_H__
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#define __PANTHOR_PWR_H__
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struct panthor_device;
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void panthor_pwr_unplug(struct panthor_device *ptdev);
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int panthor_pwr_init(struct panthor_device *ptdev);
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void panthor_pwr_suspend(struct panthor_device *ptdev);
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void panthor_pwr_resume(struct panthor_device *ptdev);
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#endif /* __PANTHOR_PWR_H__ */
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@ -209,4 +209,82 @@
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#define CSF_DOORBELL(i) (0x80000 + ((i) * 0x10000))
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#define CSF_GLB_DOORBELL_ID 0
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/* PWR Control registers */
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#define PWR_CONTROL_BASE 0x800
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#define PWR_CTRL_REG(x) (PWR_CONTROL_BASE + (x))
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#define PWR_INT_RAWSTAT PWR_CTRL_REG(0x0)
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#define PWR_INT_CLEAR PWR_CTRL_REG(0x4)
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#define PWR_INT_MASK PWR_CTRL_REG(0x8)
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#define PWR_INT_STAT PWR_CTRL_REG(0xc)
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#define PWR_IRQ_POWER_CHANGED_SINGLE BIT(0)
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#define PWR_IRQ_POWER_CHANGED_ALL BIT(1)
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#define PWR_IRQ_DELEGATION_CHANGED BIT(2)
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#define PWR_IRQ_RESET_COMPLETED BIT(3)
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#define PWR_IRQ_RETRACT_COMPLETED BIT(4)
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#define PWR_IRQ_INSPECT_COMPLETED BIT(5)
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#define PWR_IRQ_COMMAND_NOT_ALLOWED BIT(30)
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#define PWR_IRQ_COMMAND_INVALID BIT(31)
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#define PWR_STATUS PWR_CTRL_REG(0x20)
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#define PWR_STATUS_ALLOW_L2 BIT_U64(0)
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#define PWR_STATUS_ALLOW_TILER BIT_U64(1)
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#define PWR_STATUS_ALLOW_SHADER BIT_U64(8)
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#define PWR_STATUS_ALLOW_BASE BIT_U64(14)
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#define PWR_STATUS_ALLOW_STACK BIT_U64(15)
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#define PWR_STATUS_DOMAIN_ALLOWED(x) BIT_U64(x)
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#define PWR_STATUS_DELEGATED_L2 BIT_U64(16)
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#define PWR_STATUS_DELEGATED_TILER BIT_U64(17)
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#define PWR_STATUS_DELEGATED_SHADER BIT_U64(24)
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#define PWR_STATUS_DELEGATED_BASE BIT_U64(30)
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#define PWR_STATUS_DELEGATED_STACK BIT_U64(31)
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#define PWR_STATUS_DELEGATED_SHIFT 16
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#define PWR_STATUS_DOMAIN_DELEGATED(x) BIT_U64((x) + PWR_STATUS_DELEGATED_SHIFT)
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#define PWR_STATUS_ALLOW_SOFT_RESET BIT_U64(33)
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#define PWR_STATUS_ALLOW_FAST_RESET BIT_U64(34)
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#define PWR_STATUS_POWER_PENDING BIT_U64(41)
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#define PWR_STATUS_RESET_PENDING BIT_U64(42)
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#define PWR_STATUS_RETRACT_PENDING BIT_U64(43)
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#define PWR_STATUS_INSPECT_PENDING BIT_U64(44)
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#define PWR_COMMAND PWR_CTRL_REG(0x28)
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#define PWR_COMMAND_POWER_UP 0x10
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#define PWR_COMMAND_POWER_DOWN 0x11
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#define PWR_COMMAND_DELEGATE 0x20
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#define PWR_COMMAND_RETRACT 0x21
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#define PWR_COMMAND_RESET_SOFT 0x31
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#define PWR_COMMAND_RESET_FAST 0x32
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#define PWR_COMMAND_INSPECT 0xF0
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#define PWR_COMMAND_DOMAIN_L2 0
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#define PWR_COMMAND_DOMAIN_TILER 1
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#define PWR_COMMAND_DOMAIN_SHADER 8
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#define PWR_COMMAND_DOMAIN_BASE 14
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#define PWR_COMMAND_DOMAIN_STACK 15
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#define PWR_COMMAND_SUBDOMAIN_RTU BIT(0)
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#define PWR_COMMAND_DEF(cmd, domain, subdomain) \
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(((subdomain) << 16) | ((domain) << 8) | (cmd))
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#define PWR_CMDARG PWR_CTRL_REG(0x30)
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#define PWR_L2_PRESENT PWR_CTRL_REG(0x100)
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#define PWR_L2_READY PWR_CTRL_REG(0x108)
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#define PWR_L2_PWRTRANS PWR_CTRL_REG(0x110)
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#define PWR_L2_PWRACTIVE PWR_CTRL_REG(0x118)
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#define PWR_TILER_PRESENT PWR_CTRL_REG(0x140)
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#define PWR_TILER_READY PWR_CTRL_REG(0x148)
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#define PWR_TILER_PWRTRANS PWR_CTRL_REG(0x150)
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#define PWR_TILER_PWRACTIVE PWR_CTRL_REG(0x158)
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#define PWR_SHADER_PRESENT PWR_CTRL_REG(0x200)
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#define PWR_SHADER_READY PWR_CTRL_REG(0x208)
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#define PWR_SHADER_PWRTRANS PWR_CTRL_REG(0x210)
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#define PWR_SHADER_PWRACTIVE PWR_CTRL_REG(0x218)
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#define PWR_BASE_PRESENT PWR_CTRL_REG(0x380)
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#define PWR_BASE_READY PWR_CTRL_REG(0x388)
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#define PWR_BASE_PWRTRANS PWR_CTRL_REG(0x390)
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#define PWR_BASE_PWRACTIVE PWR_CTRL_REG(0x398)
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#define PWR_STACK_PRESENT PWR_CTRL_REG(0x3c0)
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#define PWR_STACK_READY PWR_CTRL_REG(0x3c8)
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#define PWR_STACK_PWRTRANS PWR_CTRL_REG(0x3d0)
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#endif
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