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https://github.com/torvalds/linux.git
synced 2026-05-27 08:33:17 +02:00
Add DMA support for RZ/T2H RSPI
Merge series from Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>: The DMA controller can be used to transfer data to and from the SPI controller without involving the CPU for each word of a SPI transfer. Add support for DMA mode, and do some other cleanups while touching the same code.
This commit is contained in:
Mark Brown
commit
c20fce4ad1
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@ -57,6 +57,14 @@ properties:
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- const: presetn
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- const: tresetn
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dmas:
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maxItems: 2
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dma-names:
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items:
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- const: rx
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- const: tx
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power-domains:
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maxItems: 1
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@ -9,6 +9,7 @@
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#include <linux/bitops.h>
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#include <linux/bits.h>
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#include <linux/clk.h>
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#include <linux/dmaengine.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/limits.h>
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@ -21,6 +22,8 @@
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#include <linux/spi/spi.h>
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#include <linux/wait.h>
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#include "internals.h"
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/* Registers */
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#define RSPI_SPDR 0x00
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#define RSPI_SPCR 0x08
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@ -37,6 +40,7 @@
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/* Register SPCR */
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#define RSPI_SPCR_BPEN BIT(31)
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#define RSPI_SPCR_MSTR BIT(30)
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#define RSPI_SPCR_SPTIE BIT(20)
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#define RSPI_SPCR_SPRIE BIT(17)
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#define RSPI_SPCR_SCKASE BIT(12)
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#define RSPI_SPCR_SPE BIT(0)
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@ -93,31 +97,29 @@ struct rzv2h_rspi_info {
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};
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struct rzv2h_rspi_priv {
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struct reset_control_bulk_data resets[RSPI_RESET_NUM];
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struct spi_controller *controller;
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const struct rzv2h_rspi_info *info;
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struct platform_device *pdev;
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void __iomem *base;
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struct clk *tclk;
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struct clk *pclk;
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wait_queue_head_t wait;
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unsigned int bytes_per_word;
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int irq_rx;
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u32 last_speed_hz;
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u32 freq;
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u16 status;
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u8 spr;
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u8 brdv;
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bool use_pclk;
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bool dma_callbacked;
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};
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#define RZV2H_RSPI_TX(func, type) \
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static inline void rzv2h_rspi_tx_##type(struct rzv2h_rspi_priv *rspi, \
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const void *txbuf, \
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unsigned int index) { \
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type buf = 0; \
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\
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if (txbuf) \
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buf = ((type *)txbuf)[index]; \
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\
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type buf = ((type *)txbuf)[index]; \
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func(buf, rspi->base + RSPI_SPDR); \
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}
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@ -126,9 +128,7 @@ static inline void rzv2h_rspi_rx_##type(struct rzv2h_rspi_priv *rspi, \
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void *rxbuf, \
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unsigned int index) { \
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type buf = func(rspi->base + RSPI_SPDR); \
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\
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if (rxbuf) \
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((type *)rxbuf)[index] = buf; \
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((type *)rxbuf)[index] = buf; \
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}
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RZV2H_RSPI_TX(writel, u32)
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@ -224,16 +224,27 @@ static int rzv2h_rspi_receive(struct rzv2h_rspi_priv *rspi, void *rxbuf,
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return 0;
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}
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static int rzv2h_rspi_transfer_one(struct spi_controller *controller,
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struct spi_device *spi,
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struct spi_transfer *transfer)
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static bool rzv2h_rspi_can_dma(struct spi_controller *ctlr, struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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struct rzv2h_rspi_priv *rspi = spi_controller_get_devdata(controller);
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unsigned int words_to_transfer, i;
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int ret = 0;
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struct rzv2h_rspi_priv *rspi = spi_controller_get_devdata(ctlr);
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transfer->effective_speed_hz = rspi->freq;
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words_to_transfer = transfer->len / rspi->bytes_per_word;
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if (ctlr->fallback)
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return false;
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if (!ctlr->dma_tx || !ctlr->dma_rx)
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return false;
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return xfer->len > rspi->info->fifo_size;
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}
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static int rzv2h_rspi_transfer_pio(struct rzv2h_rspi_priv *rspi,
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struct spi_device *spi,
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struct spi_transfer *transfer,
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unsigned int words_to_transfer)
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{
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unsigned int i;
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int ret = 0;
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for (i = 0; i < words_to_transfer; i++) {
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rzv2h_rspi_clear_all_irqs(rspi);
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@ -245,12 +256,151 @@ static int rzv2h_rspi_transfer_one(struct spi_controller *controller,
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break;
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}
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return ret;
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}
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static void rzv2h_rspi_dma_complete(void *arg)
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{
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struct rzv2h_rspi_priv *rspi = arg;
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rspi->dma_callbacked = 1;
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wake_up_interruptible(&rspi->wait);
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}
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static struct dma_async_tx_descriptor *
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rzv2h_rspi_setup_dma_channel(struct rzv2h_rspi_priv *rspi,
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struct dma_chan *chan, struct sg_table *sg,
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enum dma_slave_buswidth width,
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enum dma_transfer_direction direction)
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{
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struct dma_slave_config config = {
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.dst_addr = rspi->pdev->resource->start + RSPI_SPDR,
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.src_addr = rspi->pdev->resource->start + RSPI_SPDR,
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.dst_addr_width = width,
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.src_addr_width = width,
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.direction = direction,
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};
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struct dma_async_tx_descriptor *desc;
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int ret;
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ret = dmaengine_slave_config(chan, &config);
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if (ret)
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return ERR_PTR(ret);
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desc = dmaengine_prep_slave_sg(chan, sg->sgl, sg->nents, direction,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!desc)
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return ERR_PTR(-EAGAIN);
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if (direction == DMA_DEV_TO_MEM) {
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desc->callback = rzv2h_rspi_dma_complete;
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desc->callback_param = rspi;
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}
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return desc;
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}
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static enum dma_slave_buswidth
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rzv2h_rspi_dma_width(struct rzv2h_rspi_priv *rspi)
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{
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switch (rspi->bytes_per_word) {
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case 4:
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return DMA_SLAVE_BUSWIDTH_4_BYTES;
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case 2:
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return DMA_SLAVE_BUSWIDTH_2_BYTES;
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case 1:
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return DMA_SLAVE_BUSWIDTH_1_BYTE;
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default:
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return DMA_SLAVE_BUSWIDTH_UNDEFINED;
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}
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}
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static int rzv2h_rspi_transfer_dma(struct rzv2h_rspi_priv *rspi,
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struct spi_device *spi,
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struct spi_transfer *transfer,
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unsigned int words_to_transfer)
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{
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struct dma_async_tx_descriptor *tx_desc = NULL, *rx_desc = NULL;
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enum dma_slave_buswidth width;
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dma_cookie_t cookie;
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int ret;
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width = rzv2h_rspi_dma_width(rspi);
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if (width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
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return -EINVAL;
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rx_desc = rzv2h_rspi_setup_dma_channel(rspi, rspi->controller->dma_rx,
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&transfer->rx_sg, width,
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DMA_DEV_TO_MEM);
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if (IS_ERR(rx_desc))
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return PTR_ERR(rx_desc);
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tx_desc = rzv2h_rspi_setup_dma_channel(rspi, rspi->controller->dma_tx,
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&transfer->tx_sg, width,
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DMA_MEM_TO_DEV);
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if (IS_ERR(tx_desc))
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return PTR_ERR(tx_desc);
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cookie = dmaengine_submit(rx_desc);
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if (dma_submit_error(cookie))
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return cookie;
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cookie = dmaengine_submit(tx_desc);
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if (dma_submit_error(cookie)) {
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dmaengine_terminate_sync(rspi->controller->dma_rx);
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return cookie;
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}
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/*
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* DMA transfer does not need IRQs to be enabled.
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* For PIO, we only use RX IRQ, so disable that.
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*/
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disable_irq(rspi->irq_rx);
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rspi->dma_callbacked = 0;
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dma_async_issue_pending(rspi->controller->dma_rx);
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dma_async_issue_pending(rspi->controller->dma_tx);
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rzv2h_rspi_clear_all_irqs(rspi);
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if (ret)
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transfer->error = SPI_TRANS_FAIL_IO;
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ret = wait_event_interruptible_timeout(rspi->wait, rspi->dma_callbacked, HZ);
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if (ret) {
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dmaengine_synchronize(rspi->controller->dma_tx);
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dmaengine_synchronize(rspi->controller->dma_rx);
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ret = 0;
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} else {
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dmaengine_terminate_sync(rspi->controller->dma_tx);
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dmaengine_terminate_sync(rspi->controller->dma_rx);
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ret = -ETIMEDOUT;
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}
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spi_finalize_current_transfer(controller);
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enable_irq(rspi->irq_rx);
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return ret;
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}
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static int rzv2h_rspi_transfer_one(struct spi_controller *controller,
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struct spi_device *spi,
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struct spi_transfer *transfer)
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{
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struct rzv2h_rspi_priv *rspi = spi_controller_get_devdata(controller);
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bool is_dma = spi_xfer_is_dma_mapped(controller, spi, transfer);
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unsigned int words_to_transfer;
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int ret;
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transfer->effective_speed_hz = rspi->freq;
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words_to_transfer = transfer->len / rspi->bytes_per_word;
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if (is_dma)
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ret = rzv2h_rspi_transfer_dma(rspi, spi, transfer, words_to_transfer);
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else
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ret = rzv2h_rspi_transfer_pio(rspi, spi, transfer, words_to_transfer);
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rzv2h_rspi_clear_all_irqs(rspi);
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if (is_dma && ret == -EAGAIN)
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/* Retry with PIO */
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transfer->error = SPI_TRANS_FAIL_NO_START;
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return ret;
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}
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@ -485,6 +635,9 @@ static int rzv2h_rspi_prepare_message(struct spi_controller *ctlr,
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/* SPI receive buffer full interrupt enable */
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conf32 |= RSPI_SPCR_SPRIE;
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/* SPI transmit buffer empty interrupt enable */
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conf32 |= RSPI_SPCR_SPTIE;
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/* Bypass synchronization circuit */
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conf32 |= FIELD_PREP(RSPI_SPCR_BPEN, rspi->use_pclk);
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@ -512,7 +665,7 @@ static int rzv2h_rspi_prepare_message(struct spi_controller *ctlr,
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writeb(0, rspi->base + RSPI_SSLP);
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/* Setup FIFO thresholds */
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conf16 = FIELD_PREP(RSPI_SPDCR2_TTRG, rspi->info->fifo_size - 1);
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conf16 = FIELD_PREP(RSPI_SPDCR2_TTRG, 0);
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conf16 |= FIELD_PREP(RSPI_SPDCR2_RTRG, 0);
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writew(conf16, rspi->base + RSPI_SPDCR2);
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@ -538,9 +691,10 @@ static int rzv2h_rspi_probe(struct platform_device *pdev)
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struct spi_controller *controller;
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struct device *dev = &pdev->dev;
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struct rzv2h_rspi_priv *rspi;
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struct reset_control *reset;
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struct clk_bulk_data *clks;
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int irq_rx, ret, i;
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long tclk_rate;
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int ret, i;
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controller = devm_spi_alloc_host(dev, sizeof(*rspi));
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if (!controller)
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@ -550,6 +704,7 @@ static int rzv2h_rspi_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, rspi);
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rspi->controller = controller;
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rspi->pdev = pdev;
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rspi->info = device_get_match_data(dev);
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@ -573,83 +728,84 @@ static int rzv2h_rspi_probe(struct platform_device *pdev)
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if (!rspi->tclk)
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return dev_err_probe(dev, -EINVAL, "Failed to get tclk\n");
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rspi->resets[0].id = "presetn";
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rspi->resets[1].id = "tresetn";
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ret = devm_reset_control_bulk_get_optional_exclusive(dev, RSPI_RESET_NUM,
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rspi->resets);
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if (ret)
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return dev_err_probe(dev, ret, "cannot get resets\n");
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reset = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev,
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"presetn");
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if (IS_ERR(reset))
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return dev_err_probe(&pdev->dev, PTR_ERR(reset),
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"cannot get presetn reset\n");
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irq_rx = platform_get_irq_byname(pdev, "rx");
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if (irq_rx < 0)
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return dev_err_probe(dev, irq_rx, "cannot get IRQ 'rx'\n");
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reset = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev,
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"tresetn");
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if (IS_ERR(reset))
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return dev_err_probe(&pdev->dev, PTR_ERR(reset),
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"cannot get tresetn reset\n");
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ret = reset_control_bulk_deassert(RSPI_RESET_NUM, rspi->resets);
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if (ret)
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return dev_err_probe(dev, ret, "failed to deassert resets\n");
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rspi->irq_rx = platform_get_irq_byname(pdev, "rx");
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if (rspi->irq_rx < 0)
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return dev_err_probe(dev, rspi->irq_rx, "cannot get IRQ 'rx'\n");
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init_waitqueue_head(&rspi->wait);
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ret = devm_request_irq(dev, irq_rx, rzv2h_rx_irq_handler, 0,
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ret = devm_request_irq(dev, rspi->irq_rx, rzv2h_rx_irq_handler, 0,
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dev_name(dev), rspi);
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if (ret) {
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dev_err(dev, "cannot request `rx` IRQ\n");
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goto quit_resets;
|
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return ret;
|
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}
|
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|
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controller->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH |
|
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SPI_LSB_FIRST | SPI_LOOP;
|
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controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
|
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controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
|
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controller->prepare_message = rzv2h_rspi_prepare_message;
|
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controller->unprepare_message = rzv2h_rspi_unprepare_message;
|
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controller->num_chipselect = 4;
|
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controller->transfer_one = rzv2h_rspi_transfer_one;
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controller->can_dma = rzv2h_rspi_can_dma;
|
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|
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tclk_rate = clk_round_rate(rspi->tclk, 0);
|
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if (tclk_rate < 0) {
|
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ret = tclk_rate;
|
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goto quit_resets;
|
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}
|
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if (tclk_rate < 0)
|
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return tclk_rate;
|
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|
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controller->min_speed_hz = rzv2h_rspi_calc_bitrate(tclk_rate,
|
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RSPI_SPBR_SPR_MAX,
|
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RSPI_SPCMD_BRDV_MAX);
|
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|
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tclk_rate = clk_round_rate(rspi->tclk, ULONG_MAX);
|
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if (tclk_rate < 0) {
|
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ret = tclk_rate;
|
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goto quit_resets;
|
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}
|
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if (tclk_rate < 0)
|
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return tclk_rate;
|
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|
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controller->max_speed_hz = rzv2h_rspi_calc_bitrate(tclk_rate,
|
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RSPI_SPBR_SPR_MIN,
|
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RSPI_SPCMD_BRDV_MIN);
|
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|
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device_set_node(&controller->dev, dev_fwnode(dev));
|
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|
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ret = spi_register_controller(controller);
|
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if (ret) {
|
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dev_err(dev, "register controller failed\n");
|
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goto quit_resets;
|
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controller->dma_tx = devm_dma_request_chan(dev, "tx");
|
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if (IS_ERR(controller->dma_tx)) {
|
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ret = dev_warn_probe(dev, PTR_ERR(controller->dma_tx),
|
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"failed to request TX DMA channel\n");
|
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if (ret == -EPROBE_DEFER)
|
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return ret;
|
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controller->dma_tx = NULL;
|
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}
|
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|
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return 0;
|
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controller->dma_rx = devm_dma_request_chan(dev, "rx");
|
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if (IS_ERR(controller->dma_rx)) {
|
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ret = dev_warn_probe(dev, PTR_ERR(controller->dma_rx),
|
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"failed to request RX DMA channel\n");
|
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if (ret == -EPROBE_DEFER)
|
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return ret;
|
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controller->dma_rx = NULL;
|
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}
|
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|
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quit_resets:
|
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reset_control_bulk_assert(RSPI_RESET_NUM, rspi->resets);
|
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device_set_node(&controller->dev, dev_fwnode(dev));
|
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|
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ret = devm_spi_register_controller(dev, controller);
|
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if (ret)
|
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dev_err(dev, "register controller failed\n");
|
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|
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return ret;
|
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}
|
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|
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static void rzv2h_rspi_remove(struct platform_device *pdev)
|
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{
|
||||
struct rzv2h_rspi_priv *rspi = platform_get_drvdata(pdev);
|
||||
|
||||
spi_unregister_controller(rspi->controller);
|
||||
|
||||
reset_control_bulk_assert(RSPI_RESET_NUM, rspi->resets);
|
||||
}
|
||||
|
||||
static const struct rzv2h_rspi_info rzv2h_info = {
|
||||
.find_tclk_rate = rzv2h_rspi_find_rate_fixed,
|
||||
.tclk_name = "tclk",
|
||||
|
|
@ -674,7 +830,6 @@ MODULE_DEVICE_TABLE(of, rzv2h_rspi_match);
|
|||
|
||||
static struct platform_driver rzv2h_rspi_drv = {
|
||||
.probe = rzv2h_rspi_probe,
|
||||
.remove = rzv2h_rspi_remove,
|
||||
.driver = {
|
||||
.name = "rzv2h_rspi",
|
||||
.of_match_table = rzv2h_rspi_match,
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user