From e4c4f5a1ae18a7828c2bfaf9dfe2473632b92d1b Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 3 Oct 2025 20:14:38 +0200 Subject: [PATCH 001/138] dt-bindings: clock: qcom,x1e80100-gcc: Add missing USB4 clocks/resets Some of the USB4 muxes, RCGs and resets were not initially described. Add indices for them to allow extending the driver. Acked-by: Rob Herring (Arm) Reviewed-by: Bryan O'Donoghue Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251003-topic-hamoa_gcc_usb4-v2-1-61d27a14ee65@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,x1e80100-gcc.yaml | 62 +++++++++++++++++-- include/dt-bindings/clock/qcom,x1e80100-gcc.h | 61 ++++++++++++++++++ 2 files changed, 119 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml index 68dde0720c71..1b15b5070954 100644 --- a/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml @@ -32,9 +32,36 @@ properties: - description: PCIe 5 pipe clock - description: PCIe 6a pipe clock - description: PCIe 6b pipe clock - - description: USB QMP Phy 0 clock source - - description: USB QMP Phy 1 clock source - - description: USB QMP Phy 2 clock source + - description: USB4_0 QMPPHY clock source + - description: USB4_1 QMPPHY clock source + - description: USB4_2 QMPPHY clock source + - description: USB4_0 PHY DP0 GMUX clock source + - description: USB4_0 PHY DP1 GMUX clock source + - description: USB4_0 PHY PCIE PIPEGMUX clock source + - description: USB4_0 PHY PIPEGMUX clock source + - description: USB4_0 PHY SYS PCIE PIPEGMUX clock source + - description: USB4_1 PHY DP0 GMUX 2 clock source + - description: USB4_1 PHY DP1 GMUX 2 clock source + - description: USB4_1 PHY PCIE PIPEGMUX clock source + - description: USB4_1 PHY PIPEGMUX clock source + - description: USB4_1 PHY SYS PCIE PIPEGMUX clock source + - description: USB4_2 PHY DP0 GMUX 2 clock source + - description: USB4_2 PHY DP1 GMUX 2 clock source + - description: USB4_2 PHY PCIE PIPEGMUX clock source + - description: USB4_2 PHY PIPEGMUX clock source + - description: USB4_2 PHY SYS PCIE PIPEGMUX clock source + - description: USB4_0 PHY RX 0 clock source + - description: USB4_0 PHY RX 1 clock source + - description: USB4_1 PHY RX 0 clock source + - description: USB4_1 PHY RX 1 clock source + - description: USB4_2 PHY RX 0 clock source + - description: USB4_2 PHY RX 1 clock source + - description: USB4_0 PHY PCIE PIPE clock source + - description: USB4_0 PHY max PIPE clock source + - description: USB4_1 PHY PCIE PIPE clock source + - description: USB4_1 PHY max PIPE clock source + - description: USB4_2 PHY PCIE PIPE clock source + - description: USB4_2 PHY max PIPE clock source power-domains: description: @@ -67,7 +94,34 @@ examples: <&pcie6b_phy>, <&usb_1_ss0_qmpphy 0>, <&usb_1_ss1_qmpphy 1>, - <&usb_1_ss2_qmpphy 2>; + <&usb_1_ss2_qmpphy 2>, + <&usb4_0_phy_dp0_gmux_clk>, + <&usb4_0_phy_dp1_gmux_clk>, + <&usb4_0_phy_pcie_pipegmux_clk>, + <&usb4_0_phy_pipegmux_clk>, + <&usb4_0_phy_sys_pcie_pipegmux_clk>, + <&usb4_1_phy_dp0_gmux_2_clk>, + <&usb4_1_phy_dp1_gmux_2_clk>, + <&usb4_1_phy_pcie_pipegmux_clk>, + <&usb4_1_phy_pipegmux_clk>, + <&usb4_1_phy_sys_pcie_pipegmux_clk>, + <&usb4_2_phy_dp0_gmux_2_clk>, + <&usb4_2_phy_dp1_gmux_2_clk>, + <&usb4_2_phy_pcie_pipegmux_clk>, + <&usb4_2_phy_pipegmux_clk>, + <&usb4_2_phy_sys_pcie_pipegmux_clk>, + <&usb4_0_phy_rx_0_clk>, + <&usb4_0_phy_rx_1_clk>, + <&usb4_1_phy_rx_0_clk>, + <&usb4_1_phy_rx_1_clk>, + <&usb4_2_phy_rx_0_clk>, + <&usb4_2_phy_rx_1_clk>, + <&usb4_0_phy_pcie_pipe_clk>, + <&usb4_0_phy_max_pipe_clk>, + <&usb4_1_phy_pcie_pipe_clk>, + <&usb4_1_phy_max_pipe_clk>, + <&usb4_2_phy_pcie_pipe_clk>, + <&usb4_2_phy_max_pipe_clk>; power-domains = <&rpmhpd RPMHPD_CX>; #clock-cells = <1>; #reset-cells = <1>; diff --git a/include/dt-bindings/clock/qcom,x1e80100-gcc.h b/include/dt-bindings/clock/qcom,x1e80100-gcc.h index 710c340f24a5..62aa12425592 100644 --- a/include/dt-bindings/clock/qcom,x1e80100-gcc.h +++ b/include/dt-bindings/clock/qcom,x1e80100-gcc.h @@ -363,6 +363,30 @@ #define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 353 #define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 354 #define GCC_USB3_TERT_PHY_PIPE_CLK_SRC 355 +#define GCC_USB34_PRIM_PHY_PIPE_CLK_SRC 356 +#define GCC_USB34_SEC_PHY_PIPE_CLK_SRC 357 +#define GCC_USB34_TERT_PHY_PIPE_CLK_SRC 358 +#define GCC_USB4_0_PHY_DP0_CLK_SRC 359 +#define GCC_USB4_0_PHY_DP1_CLK_SRC 360 +#define GCC_USB4_0_PHY_P2RR2P_PIPE_CLK_SRC 361 +#define GCC_USB4_0_PHY_PCIE_PIPE_MUX_CLK_SRC 362 +#define GCC_USB4_0_PHY_RX0_CLK_SRC 363 +#define GCC_USB4_0_PHY_RX1_CLK_SRC 364 +#define GCC_USB4_0_PHY_SYS_CLK_SRC 365 +#define GCC_USB4_1_PHY_DP0_CLK_SRC 366 +#define GCC_USB4_1_PHY_DP1_CLK_SRC 367 +#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC 368 +#define GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC 369 +#define GCC_USB4_1_PHY_RX0_CLK_SRC 370 +#define GCC_USB4_1_PHY_RX1_CLK_SRC 371 +#define GCC_USB4_1_PHY_SYS_CLK_SRC 372 +#define GCC_USB4_2_PHY_DP0_CLK_SRC 373 +#define GCC_USB4_2_PHY_DP1_CLK_SRC 374 +#define GCC_USB4_2_PHY_P2RR2P_PIPE_CLK_SRC 375 +#define GCC_USB4_2_PHY_PCIE_PIPE_MUX_CLK_SRC 376 +#define GCC_USB4_2_PHY_RX0_CLK_SRC 377 +#define GCC_USB4_2_PHY_RX1_CLK_SRC 378 +#define GCC_USB4_2_PHY_SYS_CLK_SRC 379 /* GCC power domains */ #define GCC_PCIE_0_TUNNEL_GDSC 0 @@ -484,4 +508,41 @@ #define GCC_VIDEO_BCR 87 #define GCC_VIDEO_AXI0_CLK_ARES 88 #define GCC_VIDEO_AXI1_CLK_ARES 89 +#define GCC_USB4_0_MISC_USB4_SYS_BCR 90 +#define GCC_USB4_0_MISC_RX_CLK_0_BCR 91 +#define GCC_USB4_0_MISC_RX_CLK_1_BCR 92 +#define GCC_USB4_0_MISC_USB_PIPE_BCR 93 +#define GCC_USB4_0_MISC_PCIE_PIPE_BCR 94 +#define GCC_USB4_0_MISC_TMU_BCR 95 +#define GCC_USB4_0_MISC_SB_IF_BCR 96 +#define GCC_USB4_0_MISC_HIA_MSTR_BCR 97 +#define GCC_USB4_0_MISC_AHB_BCR 98 +#define GCC_USB4_0_MISC_DP0_MAX_PCLK_BCR 99 +#define GCC_USB4_0_MISC_DP1_MAX_PCLK_BCR 100 +#define GCC_USB4_1_MISC_USB4_SYS_BCR 101 +#define GCC_USB4_1_MISC_RX_CLK_0_BCR 102 +#define GCC_USB4_1_MISC_RX_CLK_1_BCR 103 +#define GCC_USB4_1_MISC_USB_PIPE_BCR 104 +#define GCC_USB4_1_MISC_PCIE_PIPE_BCR 105 +#define GCC_USB4_1_MISC_TMU_BCR 106 +#define GCC_USB4_1_MISC_SB_IF_BCR 107 +#define GCC_USB4_1_MISC_HIA_MSTR_BCR 108 +#define GCC_USB4_1_MISC_AHB_BCR 109 +#define GCC_USB4_1_MISC_DP0_MAX_PCLK_BCR 110 +#define GCC_USB4_1_MISC_DP1_MAX_PCLK_BCR 111 +#define GCC_USB4_2_MISC_USB4_SYS_BCR 112 +#define GCC_USB4_2_MISC_RX_CLK_0_BCR 113 +#define GCC_USB4_2_MISC_RX_CLK_1_BCR 114 +#define GCC_USB4_2_MISC_USB_PIPE_BCR 115 +#define GCC_USB4_2_MISC_PCIE_PIPE_BCR 116 +#define GCC_USB4_2_MISC_TMU_BCR 117 +#define GCC_USB4_2_MISC_SB_IF_BCR 118 +#define GCC_USB4_2_MISC_HIA_MSTR_BCR 119 +#define GCC_USB4_2_MISC_AHB_BCR 120 +#define GCC_USB4_2_MISC_DP0_MAX_PCLK_BCR 121 +#define GCC_USB4_2_MISC_DP1_MAX_PCLK_BCR 122 +#define GCC_USB4PHY_PHY_PRIM_BCR 123 +#define GCC_USB4PHY_PHY_SEC_BCR 124 +#define GCC_USB4PHY_PHY_TERT_BCR 125 + #endif From 28803705b552a0a711fa849490f14dca2bc5296e Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Tue, 14 Oct 2025 10:25:01 +0530 Subject: [PATCH 002/138] arm64: dts: qcom: ipq5424: correct the TF-A reserved memory to 512K Correct the reserved memory size for TF-A to 512K, as it was mistakenly marked as 500K. Update the reserved memory node accordingly. Fixes: 8517204c982b ("arm64: dts: qcom: ipq5424: Add reserved memory for TF-A") Signed-off-by: Kathiravan Thirumoorthy Link: https://lore.kernel.org/r/20251014-tfa-reserved-mem-v1-1-48c82033c8a7@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5424.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index ef2b52f3597d..227d5ce29751 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -213,7 +213,7 @@ smem@8a800000 { }; tfa@8a832000 { - reg = <0x0 0x8a832000 0x0 0x7d000>; + reg = <0x0 0x8a832000 0x0 0x80000>; no-map; status = "disabled"; }; From fcf8517850bf8f015bb7308c8520375938caea5c Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 3 Oct 2025 20:14:40 +0200 Subject: [PATCH 003/138] arm64: dts: qcom: x1e80100: Extend the gcc input clock list With the recent dt-bindings update, the missing USB4 clocks have been added. Extend the existing list to make sure the DT contains the expected amount of 'clocks' entries. Reviewed-by: Bryan O'Donoghue Signed-off-by: Konrad Dybcio Reviewed-by: Abel Vesa Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251003-topic-hamoa_gcc_usb4-v2-3-61d27a14ee65@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 29 +++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 51576d9c935d..cc76b9933a9b 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -807,7 +807,34 @@ gcc: clock-controller@100000 { <0>, <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, - <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; + <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; power-domains = <&rpmhpd RPMHPD_CX>; #clock-cells = <1>; From e38c92b8770038153045b97955988d06cb9567f9 Mon Sep 17 00:00:00 2001 From: Raymond Hackley Date: Sat, 4 Oct 2025 12:45:16 +0000 Subject: [PATCH 004/138] arm64: dts: qcom: msm8916-samsung-rossa: Move touchscreen to common device tree Every Core Prime uses an Imagis IST3038 touchscreen that is connected to &blsp_i2c5. Move it to the common device tree. Signed-off-by: Raymond Hackley Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251004123907.84270-1-raymondhackley@protonmail.com Signed-off-by: Bjorn Andersson --- .../qcom/msm8916-samsung-rossa-common.dtsi | 22 ++++++++++++++++++- .../boot/dts/qcom/msm8916-samsung-rossa.dts | 20 ----------------- 2 files changed, 21 insertions(+), 21 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi index e7f265e3c2ab..e33453c3e51e 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi @@ -5,7 +5,7 @@ /* SM5504 MUIC instead of SM5502 */ /delete-node/ &muic; -/* Touchscreen varies depending on model variant */ +/* IST3038 instead of Zinitix BT541 */ /delete-node/ &touchscreen; &blsp_i2c1 { @@ -24,6 +24,26 @@ usb_con: connector { }; }; +&blsp_i2c5 { + touchscreen: touchscreen@50 { + compatible = "imagis,ist3038"; + reg = <0x50>; + + interrupts-extended = <&tlmm 13 IRQ_TYPE_EDGE_FALLING>; + + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + + vdd-supply = <®_vdd_tsp_a>; + vddio-supply = <&pm8916_l6>; + + pinctrl-0 = <&tsp_int_default>; + pinctrl-names = "default"; + + linux,keycodes = ; + }; +}; + /* On rossa backlight is controlled with MIPI DCS commands */ &clk_pwm { status = "disabled"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa.dts index 3413b0970c4a..1981bb71f6a9 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa.dts @@ -16,26 +16,6 @@ &battery { constant-charge-voltage-max-microvolt = <4400000>; }; -&blsp_i2c5 { - touchscreen@50 { - compatible = "imagis,ist3038"; - reg = <0x50>; - - interrupts-extended = <&tlmm 13 IRQ_TYPE_EDGE_FALLING>; - - touchscreen-size-x = <480>; - touchscreen-size-y = <800>; - - vdd-supply = <®_vdd_tsp_a>; - vddio-supply = <&pm8916_l6>; - - pinctrl-0 = <&tsp_int_default>; - pinctrl-names = "default"; - - linux,keycodes = ; - }; -}; - &mpss_mem { /* Firmware for rossa needs more space */ reg = <0x0 0x86800000 0x0 0x5800000>; From 78473494a7bc7f4a10c4948e10ca95b4419cb1be Mon Sep 17 00:00:00 2001 From: Antony Kurniawan Soemardi Date: Sat, 4 Oct 2025 13:12:16 +0000 Subject: [PATCH 005/138] arm64: dts: qcom: pmi8950: Add missing VADC channels When booting msm8953-based devices, the following kernel message appears: [ 13.090800] qcom-spmi-vadc 200f000.spmi:pmic@2:adc@3100: Please define VDD channel It turns out the pmi8950 uses same VDD and GND channels as other Qualcomm's PMICs, so we can simply copy the channel definition from the other Qualcomm's PMIC dtsi. Signed-off-by: Antony Kurniawan Soemardi Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251004-fix-pmi8950-vadc-v1-1-3143ecab99e9@smankusors.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pmi8950.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmi8950.dtsi b/arch/arm64/boot/dts/qcom/pmi8950.dtsi index 3d3b1cd97cc3..16e436b68a7c 100644 --- a/arch/arm64/boot/dts/qcom/pmi8950.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8950.dtsi @@ -55,6 +55,14 @@ channel@d { qcom,pre-scaling = <1 1>; label = "chg_temp"; }; + + channel@e { + reg = ; + }; + + channel@f { + reg = ; + }; }; pmi8950_mpps: mpps@a000 { From c26a725087b00c8b9d67ab7cf983c2a26d4b6f56 Mon Sep 17 00:00:00 2001 From: Antony Kurniawan Soemardi Date: Sat, 4 Oct 2025 13:12:19 +0000 Subject: [PATCH 006/138] arm64: dts: qcom: pmi8950: Fix VADC channel scaling factors Fix USBIN/DCIN scaling to match the downstream implementation [1]. Downstream defines the following scaling mappings [2], corresponding to mainline pre-scaling values: <4> -> <1 20> <1> -> <1 3> [1] https://github.com/LineageOS/android_kernel_qcom_msm8953/blob/e6b46fc6f52e754eef5ce6265c7d82a3622e0b0f/arch/arm64/boot/dts/qcom/pmi8950.dtsi#L55-L86 [2] https://github.com/LineageOS/android_kernel_qcom_msm8953/blob/e6b46fc6f52e754eef5ce6265c7d82a3622e0b0f/include/linux/qpnp/qpnp-adc.h#L342-L357 Signed-off-by: Antony Kurniawan Soemardi Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251004-fix-pmi8950-vadc-v1-2-3143ecab99e9@smankusors.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pmi8950.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pmi8950.dtsi b/arch/arm64/boot/dts/qcom/pmi8950.dtsi index 16e436b68a7c..5bd91a5cd124 100644 --- a/arch/arm64/boot/dts/qcom/pmi8950.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8950.dtsi @@ -22,19 +22,19 @@ pmi8950_vadc: adc@3100 { channel@0 { reg = ; - qcom,pre-scaling = <1 4>; + qcom,pre-scaling = <1 20>; label = "usbin"; }; channel@1 { reg = ; - qcom,pre-scaling = <1 4>; + qcom,pre-scaling = <1 20>; label = "dcin"; }; channel@2 { reg = ; - qcom,pre-scaling = <1 1>; + qcom,pre-scaling = <1 3>; label = "vchg_sns"; }; From 30f89840f1d95f98b18882975487ff4ea90c96a4 Mon Sep 17 00:00:00 2001 From: Valentine Burley Date: Tue, 14 Oct 2025 10:48:07 +0200 Subject: [PATCH 007/138] arm64: dts: qcom: apq8096-db820c: Specify zap shader location The zap shader was previously loaded from "qcom/a530_zap.mdt", which is a symlink to "qcom/apq8096/a530_zap.mbn". Update the DTS to reference the actual firmware file in linux-firmware directly. This avoids relying on the symlink and ensures a more robust firmware load path. Signed-off-by: Valentine Burley Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251014084808.112097-1-valentine.burley@collabora.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index 5b2e88915c2f..99658b0bca84 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -201,6 +201,10 @@ &camss { &gpu { status = "okay"; + + zap-shader { + firmware-name = "qcom/apq8096/a530_zap.mbn"; + }; }; &hsusb_phy1 { From e090dc10c65eac35dcdb7c1b9cd6adcf0b590d3a Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 19 Sep 2025 11:57:23 +0200 Subject: [PATCH 008/138] dt-bindings: clock: dispcc-sm6350: Add MDSS_CORE & MDSS_RSCC resets Add the indexes for two resets inside the dispcc on SM6350 SoC. Signed-off-by: Luca Weiss Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250919-sm6350-mdss-reset-v1-1-48dcac917c73@fairphone.com Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,dispcc-sm6350.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/qcom,dispcc-sm6350.h b/include/dt-bindings/clock/qcom,dispcc-sm6350.h index cb54aae2723e..61426a80e620 100644 --- a/include/dt-bindings/clock/qcom,dispcc-sm6350.h +++ b/include/dt-bindings/clock/qcom,dispcc-sm6350.h @@ -42,6 +42,10 @@ #define DISP_CC_SLEEP_CLK 31 #define DISP_CC_XO_CLK 32 +/* Resets */ +#define DISP_CC_MDSS_CORE_BCR 0 +#define DISP_CC_MDSS_RSCC_BCR 1 + /* GDSCs */ #define MDSS_GDSC 0 From fbfbc68852edc17c825796419936ea1aed521c95 Mon Sep 17 00:00:00 2001 From: Luo Jie Date: Tue, 14 Oct 2025 22:35:27 +0800 Subject: [PATCH 009/138] dt-bindings: clock: Add "#interconnect-cells" property in IPQ9574 example The Networking Subsystem (NSS) clock controller acts as both a clock provider and an interconnect provider. The #interconnect-cells property is needed in the Device Tree Source (DTS) to ensure that client drivers such as the PPE driver can correctly acquire ICC clocks from the NSS ICC provider. Add the #interconnect-cells property to the IPQ9574 Device Tree binding example to complete it. Fixes: 28300ecedce4 ("dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions") Acked-by: Rob Herring (Arm) Signed-off-by: Luo Jie Link: https://lore.kernel.org/r/20251014-qcom_ipq5424_nsscc-v7-2-081f4956be02@quicinc.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml index 17252b6ea3be..5d35925e60d0 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml @@ -94,5 +94,6 @@ examples: "bus"; #clock-cells = <1>; #reset-cells = <1>; + #interconnect-cells = <1>; }; ... From 2985e76c66e15a6953c77d0b924e3a78d495208e Mon Sep 17 00:00:00 2001 From: Luo Jie Date: Tue, 14 Oct 2025 22:35:28 +0800 Subject: [PATCH 010/138] dt-bindings: interconnect: Add Qualcomm IPQ5424 NSSNOC IDs Add the NSSNOC master/slave ids for Qualcomm IPQ5424 network subsystem (NSS) hardware blocks. These will be used by the gcc-ipq5424 driver that provides the interconnect services by using the icc-clk framework. Acked-by: Rob Herring (Arm) Signed-off-by: Luo Jie Acked-by: Georgi Djakov Link: https://lore.kernel.org/r/20251014-qcom_ipq5424_nsscc-v7-3-081f4956be02@quicinc.com Signed-off-by: Bjorn Andersson --- .../dt-bindings/interconnect/qcom,ipq5424.h | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/include/dt-bindings/interconnect/qcom,ipq5424.h b/include/dt-bindings/interconnect/qcom,ipq5424.h index afd7e0683a24..c5e0dec0b300 100644 --- a/include/dt-bindings/interconnect/qcom,ipq5424.h +++ b/include/dt-bindings/interconnect/qcom,ipq5424.h @@ -20,6 +20,26 @@ #define SLAVE_CNOC_PCIE3 15 #define MASTER_CNOC_USB 16 #define SLAVE_CNOC_USB 17 +#define MASTER_NSSNOC_NSSCC 18 +#define SLAVE_NSSNOC_NSSCC 19 +#define MASTER_NSSNOC_SNOC_0 20 +#define SLAVE_NSSNOC_SNOC_0 21 +#define MASTER_NSSNOC_SNOC_1 22 +#define SLAVE_NSSNOC_SNOC_1 23 +#define MASTER_NSSNOC_PCNOC_1 24 +#define SLAVE_NSSNOC_PCNOC_1 25 +#define MASTER_NSSNOC_QOSGEN_REF 26 +#define SLAVE_NSSNOC_QOSGEN_REF 27 +#define MASTER_NSSNOC_TIMEOUT_REF 28 +#define SLAVE_NSSNOC_TIMEOUT_REF 29 +#define MASTER_NSSNOC_XO_DCD 30 +#define SLAVE_NSSNOC_XO_DCD 31 +#define MASTER_NSSNOC_ATB 32 +#define SLAVE_NSSNOC_ATB 33 +#define MASTER_CNOC_LPASS_CFG 34 +#define SLAVE_CNOC_LPASS_CFG 35 +#define MASTER_SNOC_LPASS 36 +#define SLAVE_SNOC_LPASS 37 #define MASTER_CPU 0 #define SLAVE_L3 1 From 60c8b7569c10c4b2ad5645cd093ff4577487314b Mon Sep 17 00:00:00 2001 From: Luo Jie Date: Tue, 14 Oct 2025 22:35:30 +0800 Subject: [PATCH 011/138] dt-bindings: clock: gcc-ipq5424: Add definition for GPLL0_OUT_AUX The GCC clock GPLL0_OUT_AUX is one of source clocks for IPQ5424 NSS clock controller. Acked-by: Rob Herring (Arm) Signed-off-by: Luo Jie Link: https://lore.kernel.org/r/20251014-qcom_ipq5424_nsscc-v7-5-081f4956be02@quicinc.com Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,ipq5424-gcc.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/qcom,ipq5424-gcc.h b/include/dt-bindings/clock/qcom,ipq5424-gcc.h index c15ad16923bd..3ae33a0fa002 100644 --- a/include/dt-bindings/clock/qcom,ipq5424-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq5424-gcc.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* * Copyright (c) 2018,2020 The Linux Foundation. All rights reserved. - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5424_H @@ -152,5 +152,6 @@ #define GCC_PCIE3_RCHNG_CLK 143 #define GCC_IM_SLEEP_CLK 144 #define GCC_XO_CLK 145 +#define GPLL0_OUT_AUX 146 #endif From 06ac2566e73d9d9fa2be62315e182945f7934882 Mon Sep 17 00:00:00 2001 From: Luo Jie Date: Tue, 14 Oct 2025 22:35:32 +0800 Subject: [PATCH 012/138] dt-bindings: clock: qcom: Add NSS clock controller for IPQ5424 SoC NSS clock controller provides the clocks and resets to the networking blocks such as PPE (Packet Process Engine) and UNIPHY (PCS) on IPQ5424 devices. Add support for the compatible string "qcom,ipq5424-nsscc" based on the existing IPQ9574 NSS clock controller Device Tree binding. Additionally, update the clock names for PPE and NSS for newer SoC additions like IPQ5424 to use generic and reusable identifiers "nss" and "ppe" without the clock rate suffix. Also add master/slave ids for IPQ5424 networking interfaces, which is used by nss-ipq5424 driver for providing interconnect services using icc-clk framework. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Luo Jie Link: https://lore.kernel.org/r/20251014-qcom_ipq5424_nsscc-v7-7-081f4956be02@quicinc.com Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,ipq9574-nsscc.yaml | 62 +++++++++++++++--- .../dt-bindings/clock/qcom,ipq5424-nsscc.h | 65 +++++++++++++++++++ .../dt-bindings/interconnect/qcom,ipq5424.h | 13 ++++ .../dt-bindings/reset/qcom,ipq5424-nsscc.h | 46 +++++++++++++ 4 files changed, 178 insertions(+), 8 deletions(-) create mode 100644 include/dt-bindings/clock/qcom,ipq5424-nsscc.h create mode 100644 include/dt-bindings/reset/qcom,ipq5424-nsscc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml index 5d35925e60d0..7ff4ff3587ca 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 +title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 and IPQ5424 maintainers: - Bjorn Andersson @@ -12,21 +12,29 @@ maintainers: description: | Qualcomm networking sub system clock control module provides the clocks, - resets on IPQ9574 + resets on IPQ9574 and IPQ5424 - See also:: + See also: + include/dt-bindings/clock/qcom,ipq5424-nsscc.h include/dt-bindings/clock/qcom,ipq9574-nsscc.h + include/dt-bindings/reset/qcom,ipq5424-nsscc.h include/dt-bindings/reset/qcom,ipq9574-nsscc.h properties: compatible: - const: qcom,ipq9574-nsscc + enum: + - qcom,ipq5424-nsscc + - qcom,ipq9574-nsscc clocks: items: - description: Board XO source - - description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source - - description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source + - description: CMN_PLL NSS (Bias PLL cc) clock source. This clock rate + can vary for different IPQ SoCs. For example, it is 1200 MHz on the + IPQ9574 and 300 MHz on the IPQ5424. + - description: CMN_PLL PPE (Bias PLL ubi nc) clock source. The clock + rate can vary for different IPQ SoCs. For example, it is 353 MHz + on the IPQ9574 and 375 MHz on the IPQ5424. - description: GCC GPLL0 OUT AUX clock source - description: Uniphy0 NSS Rx clock source - description: Uniphy0 NSS Tx clock source @@ -42,8 +50,12 @@ properties: clock-names: items: - const: xo - - const: nss_1200 - - const: ppe_353 + - enum: + - nss_1200 + - nss + - enum: + - ppe_353 + - ppe - const: gpll0_out - const: uniphy0_rx - const: uniphy0_tx @@ -60,6 +72,40 @@ required: allOf: - $ref: qcom,gcc.yaml# + - if: + properties: + compatible: + const: qcom,ipq9574-nsscc + then: + properties: + clock-names: + items: + - const: xo + - const: nss_1200 + - const: ppe_353 + - const: gpll0_out + - const: uniphy0_rx + - const: uniphy0_tx + - const: uniphy1_rx + - const: uniphy1_tx + - const: uniphy2_rx + - const: uniphy2_tx + - const: bus + else: + properties: + clock-names: + items: + - const: xo + - const: nss + - const: ppe + - const: gpll0_out + - const: uniphy0_rx + - const: uniphy0_tx + - const: uniphy1_rx + - const: uniphy1_tx + - const: uniphy2_rx + - const: uniphy2_tx + - const: bus unevaluatedProperties: false diff --git a/include/dt-bindings/clock/qcom,ipq5424-nsscc.h b/include/dt-bindings/clock/qcom,ipq5424-nsscc.h new file mode 100644 index 000000000000..eeae0dc38042 --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq5424-nsscc.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLOCK_QCOM_IPQ5424_NSSCC_H +#define _DT_BINDINGS_CLOCK_QCOM_IPQ5424_NSSCC_H + +/* NSS_CC clocks */ +#define NSS_CC_CE_APB_CLK 0 +#define NSS_CC_CE_AXI_CLK 1 +#define NSS_CC_CE_CLK_SRC 2 +#define NSS_CC_CFG_CLK_SRC 3 +#define NSS_CC_DEBUG_CLK 4 +#define NSS_CC_EIP_BFDCD_CLK_SRC 5 +#define NSS_CC_EIP_CLK 6 +#define NSS_CC_NSS_CSR_CLK 7 +#define NSS_CC_NSSNOC_CE_APB_CLK 8 +#define NSS_CC_NSSNOC_CE_AXI_CLK 9 +#define NSS_CC_NSSNOC_EIP_CLK 10 +#define NSS_CC_NSSNOC_NSS_CSR_CLK 11 +#define NSS_CC_NSSNOC_PPE_CFG_CLK 12 +#define NSS_CC_NSSNOC_PPE_CLK 13 +#define NSS_CC_PORT1_MAC_CLK 14 +#define NSS_CC_PORT1_RX_CLK 15 +#define NSS_CC_PORT1_RX_CLK_SRC 16 +#define NSS_CC_PORT1_RX_DIV_CLK_SRC 17 +#define NSS_CC_PORT1_TX_CLK 18 +#define NSS_CC_PORT1_TX_CLK_SRC 19 +#define NSS_CC_PORT1_TX_DIV_CLK_SRC 20 +#define NSS_CC_PORT2_MAC_CLK 21 +#define NSS_CC_PORT2_RX_CLK 22 +#define NSS_CC_PORT2_RX_CLK_SRC 23 +#define NSS_CC_PORT2_RX_DIV_CLK_SRC 24 +#define NSS_CC_PORT2_TX_CLK 25 +#define NSS_CC_PORT2_TX_CLK_SRC 26 +#define NSS_CC_PORT2_TX_DIV_CLK_SRC 27 +#define NSS_CC_PORT3_MAC_CLK 28 +#define NSS_CC_PORT3_RX_CLK 29 +#define NSS_CC_PORT3_RX_CLK_SRC 30 +#define NSS_CC_PORT3_RX_DIV_CLK_SRC 31 +#define NSS_CC_PORT3_TX_CLK 32 +#define NSS_CC_PORT3_TX_CLK_SRC 33 +#define NSS_CC_PORT3_TX_DIV_CLK_SRC 34 +#define NSS_CC_PPE_CLK_SRC 35 +#define NSS_CC_PPE_EDMA_CFG_CLK 36 +#define NSS_CC_PPE_EDMA_CLK 37 +#define NSS_CC_PPE_SWITCH_BTQ_CLK 38 +#define NSS_CC_PPE_SWITCH_CFG_CLK 39 +#define NSS_CC_PPE_SWITCH_CLK 40 +#define NSS_CC_PPE_SWITCH_IPE_CLK 41 +#define NSS_CC_UNIPHY_PORT1_RX_CLK 42 +#define NSS_CC_UNIPHY_PORT1_TX_CLK 43 +#define NSS_CC_UNIPHY_PORT2_RX_CLK 44 +#define NSS_CC_UNIPHY_PORT2_TX_CLK 45 +#define NSS_CC_UNIPHY_PORT3_RX_CLK 46 +#define NSS_CC_UNIPHY_PORT3_TX_CLK 47 +#define NSS_CC_XGMAC0_PTP_REF_CLK 48 +#define NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC 49 +#define NSS_CC_XGMAC1_PTP_REF_CLK 50 +#define NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC 51 +#define NSS_CC_XGMAC2_PTP_REF_CLK 52 +#define NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC 53 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,ipq5424.h b/include/dt-bindings/interconnect/qcom,ipq5424.h index c5e0dec0b300..07b786bee7d6 100644 --- a/include/dt-bindings/interconnect/qcom,ipq5424.h +++ b/include/dt-bindings/interconnect/qcom,ipq5424.h @@ -44,4 +44,17 @@ #define MASTER_CPU 0 #define SLAVE_L3 1 +#define MASTER_NSSNOC_PPE 0 +#define SLAVE_NSSNOC_PPE 1 +#define MASTER_NSSNOC_PPE_CFG 2 +#define SLAVE_NSSNOC_PPE_CFG 3 +#define MASTER_NSSNOC_NSS_CSR 4 +#define SLAVE_NSSNOC_NSS_CSR 5 +#define MASTER_NSSNOC_CE_AXI 6 +#define SLAVE_NSSNOC_CE_AXI 7 +#define MASTER_NSSNOC_CE_APB 8 +#define SLAVE_NSSNOC_CE_APB 9 +#define MASTER_NSSNOC_EIP 10 +#define SLAVE_NSSNOC_EIP 11 + #endif /* INTERCONNECT_QCOM_IPQ5424_H */ diff --git a/include/dt-bindings/reset/qcom,ipq5424-nsscc.h b/include/dt-bindings/reset/qcom,ipq5424-nsscc.h new file mode 100644 index 000000000000..9627e3b0ad30 --- /dev/null +++ b/include/dt-bindings/reset/qcom,ipq5424-nsscc.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_RESET_QCOM_IPQ5424_NSSCC_H +#define _DT_BINDINGS_RESET_QCOM_IPQ5424_NSSCC_H + +#define NSS_CC_CE_APB_CLK_ARES 0 +#define NSS_CC_CE_AXI_CLK_ARES 1 +#define NSS_CC_DEBUG_CLK_ARES 2 +#define NSS_CC_EIP_CLK_ARES 3 +#define NSS_CC_NSS_CSR_CLK_ARES 4 +#define NSS_CC_NSSNOC_CE_APB_CLK_ARES 5 +#define NSS_CC_NSSNOC_CE_AXI_CLK_ARES 6 +#define NSS_CC_NSSNOC_EIP_CLK_ARES 7 +#define NSS_CC_NSSNOC_NSS_CSR_CLK_ARES 8 +#define NSS_CC_NSSNOC_PPE_CLK_ARES 9 +#define NSS_CC_NSSNOC_PPE_CFG_CLK_ARES 10 +#define NSS_CC_PORT1_MAC_CLK_ARES 11 +#define NSS_CC_PORT1_RX_CLK_ARES 12 +#define NSS_CC_PORT1_TX_CLK_ARES 13 +#define NSS_CC_PORT2_MAC_CLK_ARES 14 +#define NSS_CC_PORT2_RX_CLK_ARES 15 +#define NSS_CC_PORT2_TX_CLK_ARES 16 +#define NSS_CC_PORT3_MAC_CLK_ARES 17 +#define NSS_CC_PORT3_RX_CLK_ARES 18 +#define NSS_CC_PORT3_TX_CLK_ARES 19 +#define NSS_CC_PPE_BCR 20 +#define NSS_CC_PPE_EDMA_CLK_ARES 21 +#define NSS_CC_PPE_EDMA_CFG_CLK_ARES 22 +#define NSS_CC_PPE_SWITCH_BTQ_CLK_ARES 23 +#define NSS_CC_PPE_SWITCH_CLK_ARES 24 +#define NSS_CC_PPE_SWITCH_CFG_CLK_ARES 25 +#define NSS_CC_PPE_SWITCH_IPE_CLK_ARES 26 +#define NSS_CC_UNIPHY_PORT1_RX_CLK_ARES 27 +#define NSS_CC_UNIPHY_PORT1_TX_CLK_ARES 28 +#define NSS_CC_UNIPHY_PORT2_RX_CLK_ARES 29 +#define NSS_CC_UNIPHY_PORT2_TX_CLK_ARES 30 +#define NSS_CC_UNIPHY_PORT3_RX_CLK_ARES 31 +#define NSS_CC_UNIPHY_PORT3_TX_CLK_ARES 32 +#define NSS_CC_XGMAC0_PTP_REF_CLK_ARES 33 +#define NSS_CC_XGMAC1_PTP_REF_CLK_ARES 34 +#define NSS_CC_XGMAC2_PTP_REF_CLK_ARES 35 + +#endif From 0dab10c38282e6ef87ef88efb99d4106cce7ed33 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Sun, 19 Oct 2025 17:26:30 +0530 Subject: [PATCH 013/138] arm64: dts: qcom: x1e80100: Fix compile warnings for USB HS controller With W=1, the following error comes up: Warning (graph_child_address): /soc@0/usb@a2f8800/usb@a200000/ports: graph node has single child node 'port@0', #address-cells/#size-cells are not necessary This could be since the controller is only HS capable and only one port node is added. Fixes: 4af46b7bd66f ("arm64: dts: qcom: x1e80100: Add USB nodes") Signed-off-by: Krishna Kurapati Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251019115630.2222720-1-krishna.kurapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index cc76b9933a9b..633b7402ae84 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -4966,15 +4966,8 @@ usb_2_dwc3: usb@a200000 { dma-coherent; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usb_2_dwc3_hs: endpoint { - }; + port { + usb_2_dwc3_hs: endpoint { }; }; }; From 6b3e8a5d6c88609d9ce93789524f818cca0aa485 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Fri, 24 Oct 2025 16:20:18 +0530 Subject: [PATCH 014/138] arm64: dts: qcom: x1e80100: Add missing quirk for HS only USB controller The PIPE clock is provided by the USB3 PHY, which is predictably not connected to the HS-only controller. Add "qcom,select-utmi-as-pipe-clk" quirk to HS only USB controller to disable pipe clock requirement. Fixes: 4af46b7bd66f ("arm64: dts: qcom: x1e80100: Add USB nodes") Signed-off-by: Krishna Kurapati Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20251024105019.2220832-2-krishna.kurapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 633b7402ae84..087465f028f5 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -4949,6 +4949,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, interconnect-names = "usb-ddr", "apps-usb"; + qcom,select-utmi-as-pipe-clk; wakeup-source; status = "disabled"; From 0903296efd0b4e17c8d556ce8c33347147301870 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Fri, 24 Oct 2025 16:20:19 +0530 Subject: [PATCH 015/138] arm64: dts: qcom: lemans: Add missing quirk for HS only USB controller The PIPE clock is provided by the USB3 PHY, which is predictably not connected to the HS-only controller. Add "qcom,select-utmi-as-pipe-clk" quirk to HS only USB controller to disable pipe clock requirement. Fixes: de1001525c1a ("arm64: dts: qcom: sa8775p: add USB nodes") Signed-off-by: Krishna Kurapati Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20251024105019.2220832-3-krishna.kurapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index cf685cb186ed..c2d2200d845b 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -4106,6 +4106,7 @@ usb_2: usb@a400000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>; interconnect-names = "usb-ddr", "apps-usb"; + qcom,select-utmi-as-pipe-clk; wakeup-source; iommus = <&apps_smmu 0x020 0x0>; From fe9829de17d3c01072cb45ef564b33101c62f58b Mon Sep 17 00:00:00 2001 From: Wenmeng Liu Date: Fri, 15 Aug 2025 15:07:19 +0800 Subject: [PATCH 016/138] arm64: dts: qcom: lemans-evk-camera: Add DT overlay Enable IMX577 via CCI1 on Lemans EVK. Signed-off-by: Wenmeng Liu Reviewed-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20250815-rb8_camera-v2-3-6806242913ed@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../boot/dts/qcom/lemans-evk-camera.dtso | 105 ++++++++++++++++++ 2 files changed, 107 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/lemans-evk-camera.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 296688f7cb26..65a0e26b148c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -33,8 +33,10 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb dtb-$(CONFIG_ARCH_QCOM) += lemans-evk.dtb lemans-evk-camera-csi1-imx577-dtbs := lemans-evk.dtb lemans-evk-camera-csi1-imx577.dtbo +lemans-evk-camera-dtbs := lemans-evk.dtb lemans-evk-camera.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camera-csi1-imx577.dtb +dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camera.dtb dtb-$(CONFIG_ARCH_QCOM) += monaco-evk.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8216-samsung-fortuna3g.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-camera.dtso b/arch/arm64/boot/dts/qcom/lemans-evk-camera.dtso new file mode 100644 index 000000000000..4600d5441cce --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-evk-camera.dtso @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/* + * Camera Sensor overlay on top of leman evk core kit. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + vreg_cam1_1p8: vreg_cam1_1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_cam1_1p8"; + startup-delay-us = <10000>; + enable-active-high; + gpio = <&pmm8654au_0_gpios 8 GPIO_ACTIVE_HIGH>; + }; +}; + +&camcc { + status = "okay"; +}; + +&camss { + vdda-pll-supply = <&vreg_l1c>; + vdda-phy-supply = <&vreg_l4a>; + + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + csiphy1_ep: endpoint { + clock-lanes = <7>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&imx577_ep1>; + }; + }; + }; +}; + +&cci1 { + pinctrl-0 = <&cci1_0_default>; + pinctrl-1 = <&cci1_0_sleep>; + + status = "okay"; +}; + +&cci1_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + camera@1a { + compatible = "sony,imx577"; + reg = <0x1a>; + + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&cam1_default>; + pinctrl-names = "default"; + + clocks = <&camcc CAM_CC_MCLK1_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK1_CLK>; + assigned-clock-rates = <24000000>; + + dovdd-supply = <&vreg_s4a>; + avdd-supply = <&vreg_cam1_1p8>; + + port { + imx577_ep1: endpoint { + clock-lanes = <7>; + link-frequencies = /bits/ 64 <600000000>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&csiphy1_ep>; + }; + }; + }; +}; + +&tlmm { + cam1_default: cam1-default-state { + mclk-pins { + pins = "gpio73"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + rst-pins { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; +}; From 44562f5918907b2e0d7e265540afebe7a42c48d2 Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Tue, 19 Aug 2025 11:24:47 +0000 Subject: [PATCH 017/138] arm64: dts: qcom: qcs615: Add OSM l3 interconnect provider node and CPU OPP tables to scale DDR/L3 Add Operation State Manager (OSM) L3 interconnect provide node and OPP tables required to scale DDR and L3 per freq-domain on QCS615 SoC. As QCS615 and SM8150 SoCs have same OSM hardware, added SM8150 compatible as fallback for QCS615 OSM device node. Signed-off-by: Imran Shaik Signed-off-by: Raviteja Laggyshetty Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250819-talos-l3-icc-v3-2-04529e85dac7@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6150.dtsi | 148 +++++++++++++++++++++++++++ 1 file changed, 148 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qcom/sm6150.dtsi index 3d2a1cb02b62..eb6f69be4a82 100644 --- a/arch/arm64/boot/dts/qcom/sm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -39,6 +40,10 @@ cpu0: cpu@0 { clocks = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_0: l2-cache { compatible = "cache"; @@ -60,6 +65,10 @@ cpu1: cpu@100 { next-level-cache = <&l2_100>; clocks = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_100: l2-cache { compatible = "cache"; @@ -81,6 +90,10 @@ cpu2: cpu@200 { next-level-cache = <&l2_200>; clocks = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_200: l2-cache { compatible = "cache"; @@ -102,6 +115,10 @@ cpu3: cpu@300 { next-level-cache = <&l2_300>; clocks = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_300: l2-cache { compatible = "cache"; @@ -123,6 +140,10 @@ cpu4: cpu@400 { next-level-cache = <&l2_400>; clocks = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_400: l2-cache { compatible = "cache"; @@ -144,6 +165,10 @@ cpu5: cpu@500 { next-level-cache = <&l2_500>; clocks = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_500: l2-cache { compatible = "cache"; @@ -166,6 +191,10 @@ cpu6: cpu@600 { clocks = <&cpufreq_hw 1>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; + operating-points-v2 = <&cpu6_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_600: l2-cache { compatible = "cache"; @@ -187,6 +216,10 @@ cpu7: cpu@700 { next-level-cache = <&l2_700>; clocks = <&cpufreq_hw 1>; qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu6_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_700: l2-cache { compatible = "cache"; @@ -239,6 +272,111 @@ l3_0: l3-cache { }; }; + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <(300000 * 4) (300000 * 16)>; + }; + + opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + opp-peak-kBps = <(300000 * 4) (576000 * 16)>; + }; + + opp-748800000 { + opp-hz = /bits/ 64 <748800000>; + opp-peak-kBps = <(300000 * 4) (576000 * 16)>; + }; + + opp-998400000 { + opp-hz = /bits/ 64 <998400000>; + opp-peak-kBps = <(451000 * 4) (806400 * 16)>; + }; + + opp-1209600000 { + opp-hz = /bits/ 64 <1209600000>; + opp-peak-kBps = <(547000 * 4) (1017600 * 16)>; + }; + + opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + opp-peak-kBps = <(768000 * 4) (1209600 * 16)>; + }; + + opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <(768000 * 4) (1209600 * 16)>; + }; + + opp-1593600000 { + opp-hz = /bits/ 64 <1593600000>; + opp-peak-kBps = <(1017000 * 4) (1363200 * 16)>; + }; + }; + + cpu6_opp_table: opp-table-cpu6 { + compatible = "operating-points-v2"; + opp-shared; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <(451000 * 4) (300000 * 16)>; + }; + + opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + opp-peak-kBps = <(451000 * 4) (576000 * 16)>; + }; + + opp-768000000 { + opp-hz = /bits/ 64 <768000000>; + opp-peak-kBps = <(451000 * 4) (576000 * 16)>; + }; + + opp-979200000 { + opp-hz = /bits/ 64 <979200000>; + opp-peak-kBps = <(547000 * 4) (806400 * 16)>; + }; + + opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + opp-peak-kBps = <(547000 * 4) (806400 * 16)>; + }; + + opp-1094400000 { + opp-hz = /bits/ 64 <109440000>; + opp-peak-kBps = <(1017600 * 4) (940800 * 16)>; + }; + + opp-1209600000 { + opp-hz = /bits/ 64 <1209600000>; + opp-peak-kBps = <(1017600 * 4) (1017600 * 16)>; + }; + + opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + opp-peak-kBps = <(1555000 * 4) (1209600 * 16)>; + }; + + opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <(1555000 * 4) (1209600 * 16)>; + }; + + opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <(1555000 * 4) (1363200 * 16)>; + }; + + opp-1900800000 { + opp-hz = /bits/ 64 <1900800000>; + opp-peak-kBps = <(1555000 * 4) (1363200 * 16)>; + }; + }; + dummy_eud: dummy-sink { compatible = "arm,coresight-dummy-sink"; @@ -3978,6 +4116,16 @@ rpmhpd_opp_turbo_l1: opp-9 { }; }; + osm_l3: interconnect@18321000 { + compatible = "qcom,qcs615-osm-l3", "qcom,sm8150-osm-l3", "qcom,osm-l3"; + reg = <0x0 0x18321000 0x0 0x1400>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; + usb_1_hsphy: phy@88e2000 { compatible = "qcom,qcs615-qusb2-phy"; reg = <0x0 0x88e2000 0x0 0x180>; From 03e928442d469f7d8dafc549638730647202d9ce Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 28 Aug 2025 13:04:22 +0530 Subject: [PATCH 018/138] arm64: dts: qcom: sc7280: Increase config size to 256MB for ECAM feature PCIe ECAM(Enhanced Configuration Access Mechanism) feature requires maximum of 256MB configuration space. To enable this feature increase configuration space size to 256MB. If the config space is increased, the BAR space needs to be truncated as it resides in the same location. To avoid the bar space truncation move config space, DBI, ELBI, iATU to upper PCIe region and use lower PCIe iregion entirely for BAR region. This depends on the commit: '10ba0854c5e6 ("PCI: qcom: Disable mirroring of DBI and iATU register space in BAR region")' Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Krishna Chaitanya Chundru Link: https://lore.kernel.org/r/20250828-ecam_v4-v8-1-92a30e0fa02d@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 4b04dea57ec8..e503c467b2c6 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2332,11 +2332,11 @@ pcie0_phy: phy@1c06000 { pcie1: pcie@1c08000 { compatible = "qcom,pcie-sc7280"; - reg = <0 0x01c08000 0 0x3000>, - <0 0x40000000 0 0xf1d>, - <0 0x40000f20 0 0xa8>, - <0 0x40001000 0 0x1000>, - <0 0x40100000 0 0x100000>; + reg = <0x0 0x01c08000 0 0x3000>, + <0x4 0x10001000 0 0xf1d>, + <0x4 0x10001f20 0 0xa8>, + <0x4 0x10000000 0 0x1000>, + <0x4 0x00000000 0 0x10000000>; reg-names = "parf", "dbi", "elbi", "atu", "config"; device_type = "pci"; @@ -2347,8 +2347,8 @@ pcie1: pcie@1c08000 { #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, - <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x40000000 0x0 0x100000>, + <0x02000000 0x0 0x40100000 0x0 0x40100000 0x0 0x1ff00000>; interrupts = , , From 883e20433fe586a6d3e1332d25f5e675921fefd9 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 21 Sep 2025 10:09:18 +0300 Subject: [PATCH 019/138] arm64: dts: qcom: lemans: move USB PHYs to a proper place Sort the lemans.dtsi, moving USB1 and USB2 PHYs to a proper place, making the DT file sorted by the address. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250921-refgen-v1-2-9d93e64133ea@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 100 +++++++++++++-------------- 1 file changed, 50 insertions(+), 50 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index c2d2200d845b..5fb083a19918 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -3901,6 +3901,32 @@ usb_0_hsphy: phy@88e4000 { status = "disabled"; }; + usb_1_hsphy: phy@88e6000 { + compatible = "qcom,sa8775p-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg = <0 0x088e6000 0 0x120>; + clocks = <&gcc GCC_USB_CLKREF_EN>; + clock-names = "ref"; + resets = <&gcc GCC_USB2_PHY_SEC_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_2_hsphy: phy@88e7000 { + compatible = "qcom,sa8775p-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg = <0 0x088e7000 0 0x120>; + clocks = <&gcc GCC_USB_CLKREF_EN>; + clock-names = "ref"; + resets = <&gcc GCC_USB3_PHY_TERT_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + usb_0_qmpphy: phy@88e8000 { compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; reg = <0 0x088e8000 0 0x2000>; @@ -3925,6 +3951,30 @@ usb_0_qmpphy: phy@88e8000 { status = "disabled"; }; + usb_1_qmpphy: phy@88ea000 { + compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; + reg = <0 0x088ea000 0 0x2000>; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&gcc GCC_USB_CLKREF_EN>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + clock-names = "aux", "ref", "com_aux", "pipe"; + + resets = <&gcc GCC_USB3_PHY_SEC_BCR>, + <&gcc GCC_USB3PHY_PHY_SEC_BCR>; + reset-names = "phy", "phy_phy"; + + power-domains = <&gcc USB30_SEC_GDSC>; + + #clock-cells = <0>; + clock-output-names = "usb3_sec_phy_pipe_clk_src"; + + #phy-cells = <0>; + + status = "disabled"; + }; + usb_0: usb@a600000 { compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; reg = <0 0x0a600000 0 0xfc100>; @@ -3973,43 +4023,6 @@ usb_0: usb@a600000 { status = "disabled"; }; - usb_1_hsphy: phy@88e6000 { - compatible = "qcom,sa8775p-usb-hs-phy", - "qcom,usb-snps-hs-5nm-phy"; - reg = <0 0x088e6000 0 0x120>; - clocks = <&gcc GCC_USB_CLKREF_EN>; - clock-names = "ref"; - resets = <&gcc GCC_USB2_PHY_SEC_BCR>; - - #phy-cells = <0>; - - status = "disabled"; - }; - - usb_1_qmpphy: phy@88ea000 { - compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; - reg = <0 0x088ea000 0 0x2000>; - - clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, - <&gcc GCC_USB_CLKREF_EN>, - <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, - <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; - clock-names = "aux", "ref", "com_aux", "pipe"; - - resets = <&gcc GCC_USB3_PHY_SEC_BCR>, - <&gcc GCC_USB3PHY_PHY_SEC_BCR>; - reset-names = "phy", "phy_phy"; - - power-domains = <&gcc USB30_SEC_GDSC>; - - #clock-cells = <0>; - clock-output-names = "usb3_sec_phy_pipe_clk_src"; - - #phy-cells = <0>; - - status = "disabled"; - }; - usb_1: usb@a800000 { compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; reg = <0 0x0a800000 0 0xfc100>; @@ -4058,19 +4071,6 @@ usb_1: usb@a800000 { status = "disabled"; }; - usb_2_hsphy: phy@88e7000 { - compatible = "qcom,sa8775p-usb-hs-phy", - "qcom,usb-snps-hs-5nm-phy"; - reg = <0 0x088e7000 0 0x120>; - clocks = <&gcc GCC_USB_CLKREF_EN>; - clock-names = "ref"; - resets = <&gcc GCC_USB3_PHY_TERT_BCR>; - - #phy-cells = <0>; - - status = "disabled"; - }; - usb_2: usb@a400000 { compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; reg = <0 0x0a400000 0 0xfc100>; From 7522c9ffaa97041a1a5dfdcb460d2a2b89f860b1 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 21 Sep 2025 10:09:19 +0300 Subject: [PATCH 020/138] arm64: dts: qcom: lemans: add refgen regulator and use it for DSI Add the refgen regulator block and use it for the DSI controllers. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250921-refgen-v1-3-9d93e64133ea@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 5fb083a19918..ae8cf9203ace 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -3975,6 +3975,12 @@ usb_1_qmpphy: phy@88ea000 { status = "disabled"; }; + refgen: regulator@891c000 { + compatible = "qcom,sa8775p-refgen-regulator", + "qcom,sm8250-refgen-regulator"; + reg = <0x0 0x0891c000 0x0 0x84>; + }; + usb_0: usb@a600000 { compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; reg = <0 0x0a600000 0 0xfc100>; @@ -4900,6 +4906,8 @@ mdss0_dsi0: dsi@ae94000 { operating-points-v2 = <&mdss_dsi_opp_table>; power-domains = <&rpmhpd SA8775P_MMCX>; + refgen-supply = <&refgen>; + #address-cells = <1>; #size-cells = <0>; @@ -4982,6 +4990,8 @@ mdss0_dsi1: dsi@ae96000 { operating-points-v2 = <&mdss_dsi_opp_table>; power-domains = <&rpmhpd SA8775P_MMCX>; + refgen-supply = <&refgen>; + #address-cells = <1>; #size-cells = <0>; From ac44b60f5d12cc5531dd04619b6fc31d84ee4091 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 21 Sep 2025 10:09:20 +0300 Subject: [PATCH 021/138] arm64: dts: qcom: sc7180: add refgen regulator and use it for DSI Add the refgen regulator block and use it for the DSI controller. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250921-refgen-v1-4-9d93e64133ea@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index a0df10a97c7f..a47182994c56 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1474,6 +1474,12 @@ uart11: serial@a94000 { }; }; + refgen: regulator@ff1000 { + compatible = "qcom,sc7180-refgen-regulator", + "qcom,sdm845-refgen-regulator"; + reg = <0x0 0x00ff1000 0x0 0x60>; + }; + config_noc: interconnect@1500000 { compatible = "qcom,sc7180-config-noc"; reg = <0 0x01500000 0 0x28000>; @@ -3332,6 +3338,8 @@ mdss_dsi0: dsi@ae94000 { phys = <&mdss_dsi0_phy>; + refgen-supply = <&refgen>; + #address-cells = <1>; #size-cells = <0>; From f8cfb1932ce35c149bec81ea50fdf9b7472c6013 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 21 Sep 2025 10:09:21 +0300 Subject: [PATCH 022/138] arm64: dts: qcom: sc7280: add refgen regulator and use it for DSI Add the refgen regulator block and use it for the DSI controller. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250921-refgen-v1-5-9d93e64133ea@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index e503c467b2c6..3ef61af2ed8a 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3885,6 +3885,12 @@ usb_2_hsphy: phy@88e4000 { resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; }; + refgen: regulator@88e7000 { + compatible = "qcom,sc7280-refgen-regulator", + "qcom,sm8250-refgen-regulator"; + reg = <0x0 0x088e7000 0x0 0x84>; + }; + usb_1_qmpphy: phy@88e8000 { compatible = "qcom,sc7280-qmp-usb3-dp-phy"; reg = <0 0x088e8000 0 0x3000>; @@ -5074,6 +5080,8 @@ mdss_dsi: dsi@ae94000 { phys = <&mdss_dsi_phy>; + refgen-supply = <&refgen>; + #address-cells = <1>; #size-cells = <0>; From 4be2ab8c4e7d35e287962f640a0994982776d4ce Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 21 Sep 2025 10:09:22 +0300 Subject: [PATCH 023/138] arm64: dts: qcom: sc8180x: add refgen regulator and use it for DSI Add the refgen regulator block and use it for the DSI controllers. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250921-refgen-v1-6-9d93e64133ea@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 85c2afcb417d..e3143a4a41c9 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -2530,6 +2530,12 @@ usb_mp_hsphy1: phy@88e5000 { status = "disabled"; }; + refgen: regulator@88e7000 { + compatible = "qcom,sc8180x-refgen-regulator", + "qcom,sdm845-refgen-regulator"; + reg = <0x0 0x088e7000 0x0 0x60>; + }; + usb_prim_qmpphy: phy@88e8000 { compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; reg = <0 0x088e8000 0 0x3000>; @@ -3116,6 +3122,8 @@ mdss_dsi0: dsi@ae94000 { phys = <&mdss_dsi0_phy>; phy-names = "dsi"; + refgen-supply = <&refgen>; + status = "disabled"; ports { @@ -3203,6 +3211,8 @@ mdss_dsi1: dsi@ae96000 { phys = <&mdss_dsi1_phy>; phy-names = "dsi"; + refgen-supply = <&refgen>; + status = "disabled"; ports { From 7223744176ef40969da0caa9dcc3588baa773b99 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 21 Sep 2025 10:09:23 +0300 Subject: [PATCH 024/138] arm64: dts: qcom: sdm670: add refgen regulator and use it for DSI Add the refgen regulator block and use it for the DSI controllers. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250921-refgen-v1-7-9d93e64133ea@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index c33f3de779f6..c3264a31bccf 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -1124,6 +1124,12 @@ i2c15: i2c@a9c000 { }; }; + refgen: regulator@ff1000 { + compatible = "qcom,sdm670-refgen-regulator", + "qcom,sdm845-refgen-regulator"; + reg = <0x0 0x00ff1000 0x0 0x60>; + }; + mem_noc: interconnect@1380000 { compatible = "qcom,sdm670-mem-noc"; reg = <0 0x01380000 0 0x27200>; @@ -1926,6 +1932,8 @@ mdss_dsi0: dsi@ae94000 { phys = <&mdss_dsi0_phy>; + refgen-supply = <&refgen>; + #address-cells = <1>; #size-cells = <0>; @@ -2000,6 +2008,8 @@ mdss_dsi1: dsi@ae96000 { phys = <&mdss_dsi1_phy>; + refgen-supply = <&refgen>; + #address-cells = <1>; #size-cells = <0>; From ca031c24bf66dc51e9304917243ca4d1a5dfa110 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 21 Sep 2025 10:09:24 +0300 Subject: [PATCH 025/138] arm64: dts: qcom: sdm845: add refgen regulator and use it for DSI Add the refgen regulator block and use it for the DSI controllers. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250921-refgen-v1-8-9d93e64133ea@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 13c9515260ef..1c3a7371a2d3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2218,6 +2218,11 @@ uart15: serial@a9c000 { }; }; + refgen: regulator@ff1000 { + compatible = "qcom,sdm845-refgen-regulator"; + reg = <0x0 0x00ff1000 0x0 0x60>; + }; + llcc: system-cache-controller@1100000 { compatible = "qcom,sdm845-llcc"; reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>, @@ -4750,6 +4755,8 @@ mdss_dsi0: dsi@ae94000 { phys = <&mdss_dsi0_phy>; + refgen-supply = <&refgen>; + status = "disabled"; #address-cells = <1>; @@ -4824,6 +4831,8 @@ mdss_dsi1: dsi@ae96000 { phys = <&mdss_dsi1_phy>; + refgen-supply = <&refgen>; + status = "disabled"; #address-cells = <1>; From e53107df09622c3a6c534ff4bffad9634d05c41e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 21 Sep 2025 10:09:25 +0300 Subject: [PATCH 026/138] arm64: dts: qcom: sm6350: add refgen regulator and use it for DSI Add the refgen regulator block and use it for the DSI controller. Signed-off-by: Dmitry Baryshkov Reviewed-by: Luca Weiss Link: https://lore.kernel.org/r/20250921-refgen-v1-9-9d93e64133ea@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 8459b27cacc7..dd009569a668 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1768,6 +1768,12 @@ usb_1_hsphy: phy@88e3000 { resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; }; + refgen: regulator@88e7000 { + compatible = "qcom,sm6350-refgen-regulator", + "qcom,sm8250-refgen-regulator"; + reg = <0x0 0x088e7000 0x0 0x84>; + }; + usb_1_qmpphy: phy@88e8000 { compatible = "qcom,sm6350-qmp-usb3-dp-phy"; reg = <0x0 0x088e8000 0x0 0x3000>; @@ -2360,6 +2366,8 @@ mdss_dsi0: dsi@ae94000 { phys = <&mdss_dsi0_phy>; phy-names = "dsi"; + refgen-supply = <&refgen>; + #address-cells = <1>; #size-cells = <0>; From 0aa588760dd9f2f3d35eecd0a2120afe332b636d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 21 Sep 2025 10:09:26 +0300 Subject: [PATCH 027/138] arm64: dts: qcom: sm8150: add refgen regulator and use it for DSI Add the refgen regulator block and use it for the DSI controller. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250921-refgen-v1-10-9d93e64133ea@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index acdba79612aa..1ea2beb9e2ea 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3469,6 +3469,12 @@ usb_2_hsphy: phy@88e3000 { resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; }; + refgen: regulator@88e7000 { + compatible = "qcom,sm8150-refgen-regulator", + "qcom,sdm845-refgen-regulator"; + reg = <0x0 0x088e7000 0x0 0x60>; + }; + usb_1_qmpphy: phy@88e8000 { compatible = "qcom,sm8150-qmp-usb3-dp-phy"; reg = <0 0x088e8000 0 0x3000>; @@ -3992,6 +3998,8 @@ mdss_dsi0: dsi@ae94000 { phys = <&mdss_dsi0_phy>; + refgen-supply = <&refgen>; + status = "disabled"; #address-cells = <1>; @@ -4085,6 +4093,8 @@ mdss_dsi1: dsi@ae96000 { phys = <&mdss_dsi1_phy>; + refgen-supply = <&refgen>; + status = "disabled"; #address-cells = <1>; From 3aedde1859f341f0f631330928872c535769e20b Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 21 Sep 2025 10:09:27 +0300 Subject: [PATCH 028/138] arm64: dts: qcom: sm8250: add refgen regulator and use it for DSI Add the refgen regulator block and use it for the DSI controller. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250921-refgen-v1-11-9d93e64133ea@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 50dd11432bb2..8248ac3119f1 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3901,6 +3901,11 @@ usb_2_hsphy: phy@88e4000 { resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; }; + refgen: regulator@88e7000 { + compatible = "qcom,sm8250-refgen-regulator"; + reg = <0x0 0x088e7000 0x0 0x84>; + }; + usb_1_qmpphy: phy@88e8000 { compatible = "qcom,sm8250-qmp-usb3-dp-phy"; reg = <0 0x088e8000 0 0x3000>; @@ -4873,6 +4878,8 @@ mdss_dsi0: dsi@ae94000 { phys = <&mdss_dsi0_phy>; + refgen-supply = <&refgen>; + status = "disabled"; #address-cells = <1>; @@ -4967,6 +4974,8 @@ mdss_dsi1: dsi@ae96000 { phys = <&mdss_dsi1_phy>; + refgen-supply = <&refgen>; + status = "disabled"; #address-cells = <1>; From 2c9e4d7c6896ef285e884f0abf5c15d198cea469 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 21 Sep 2025 10:09:28 +0300 Subject: [PATCH 029/138] arm64: dts: qcom: qcs8300: add refgen regulator Add the refgen regulator block. It should be used for DSI controllers once they are added. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250921-refgen-v1-12-9d93e64133ea@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 8d78ccac411e..816fa2af8a9a 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -20,6 +20,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -4294,6 +4295,12 @@ serdes0: phy@8909000 { status = "disabled"; }; + refgen: regulator@891c000 { + compatible = "qcom,qcs8300-refgen-regulator", + "qcom,sm8250-refgen-regulator"; + reg = <0x0 0x0891c000 0x0 0x84>; + }; + gpu: gpu@3d00000 { compatible = "qcom,adreno-623.0", "qcom,adreno"; reg = <0x0 0x03d00000 0x0 0x40000>, From d4d1e799e9bf98ddd05023dd98860079e641c547 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 21 Sep 2025 10:09:29 +0300 Subject: [PATCH 030/138] arm64: dts: qcom: sc8280xp: add refgen regulator Add the refgen regulator block. It should be used for DSI controllers once they are added. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250921-refgen-v1-13-9d93e64133ea@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 279e5e6beae2..e48efbd13bfa 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -3723,6 +3723,12 @@ usb_2_qmpphy1: phy@88f1000 { status = "disabled"; }; + refgen: regulator@8900000 { + compatible = "qcom,sc8280xp-refgen-regulator", + "qcom,sm8250-refgen-regulator"; + reg = <0x0 0x08900000 0x0 0x96>; + }; + usb_1_hsphy: phy@8902000 { compatible = "qcom,sc8280xp-usb-hs-phy", "qcom,usb-snps-hs-5nm-phy"; From afec70ac038bbd3666677436eb1ec0faf0504f72 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 21 Sep 2025 10:09:30 +0300 Subject: [PATCH 031/138] arm64: dts: qcom: sm6375: add refgen regulator Add the refgen regulator block. It should be used for DSI controllers once they are added. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250921-refgen-v1-14-9d93e64133ea@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 0faa3a40ff82..87d6600ccbd9 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -971,6 +971,12 @@ usb_1_hsphy: phy@162b000 { status = "disabled"; }; + refgen: regulator@162f000 { + compatible = "qcom,sm6375-refgen-regulator", + "qcom,sm8250-refgen-regulator"; + reg = <0x0 0x0162f000 0x0 0x84>; + }; + spmi_bus: spmi@1c40000 { compatible = "qcom,spmi-pmic-arb"; reg = <0 0x01c40000 0 0x1100>, From e50e601ef5b96def44c9ca9685cda6832eb7578e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 23 Sep 2025 14:01:54 +0300 Subject: [PATCH 032/138] arm64: dts: qcom: rename qcs8300 to monaco The QCS8300 and QCS8275 are two variants of the same die with no difference visible to the Linux kernel, which are collectively named as 'monaco'. Rather than trying to using the name, which is not always relevant, follow the example of 'lemans' and rename qcs8300.dtsi to monaco.dtsi (and qcs8300-pmics.dtsi to monaco-pmics.dtsi). Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250923-rename-dts-v1-1-21888b68c781@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco-evk.dts | 4 ++-- .../boot/dts/qcom/{qcs8300-pmics.dtsi => monaco-pmics.dtsi} | 0 arch/arm64/boot/dts/qcom/{qcs8300.dtsi => monaco.dtsi} | 0 arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 4 ++-- 4 files changed, 4 insertions(+), 4 deletions(-) rename arch/arm64/boot/dts/qcom/{qcs8300-pmics.dtsi => monaco-pmics.dtsi} (100%) rename arch/arm64/boot/dts/qcom/{qcs8300.dtsi => monaco.dtsi} (100%) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts index e72cf6725a52..d9e9e65a137d 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk.dts +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts @@ -9,8 +9,8 @@ #include #include -#include "qcs8300.dtsi" -#include "qcs8300-pmics.dtsi" +#include "monaco.dtsi" +#include "monaco-pmics.dtsi" / { model = "Qualcomm Technologies, Inc. Monaco EVK"; diff --git a/arch/arm64/boot/dts/qcom/qcs8300-pmics.dtsi b/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi similarity index 100% rename from arch/arm64/boot/dts/qcom/qcs8300-pmics.dtsi rename to arch/arm64/boot/dts/qcom/monaco-pmics.dtsi diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi similarity index 100% rename from arch/arm64/boot/dts/qcom/qcs8300.dtsi rename to arch/arm64/boot/dts/qcom/monaco.dtsi diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index cabb3f508704..9bcb869dd270 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -8,8 +8,8 @@ #include #include -#include "qcs8300.dtsi" -#include "qcs8300-pmics.dtsi" +#include "monaco.dtsi" +#include "monaco-pmics.dtsi" / { model = "Qualcomm Technologies, Inc. QCS8300 Ride"; compatible = "qcom,qcs8300-ride", "qcom,qcs8300"; From 8c0b058ab5983a4be6690a76be9b0294853e8e55 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 23 Sep 2025 14:01:55 +0300 Subject: [PATCH 033/138] arm64: dts: qcom: rename x1e80100 to hamoa The X1E80100 and several other similar names (X1E78100, X1E001DE) all belong to the platform now known as 'hamoa'. Follow the example of 'lemans' and rename the x1e80100.dtsi to hamoa.dtsi and x1e80100-pmics.dtsi to hamoa-pmics.dtsi. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250923-rename-dts-v1-2-21888b68c781@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi | 4 ++-- .../boot/dts/qcom/{x1e80100-pmics.dtsi => hamoa-pmics.dtsi} | 0 arch/arm64/boot/dts/qcom/{x1e80100.dtsi => hamoa.dtsi} | 0 arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi | 2 +- arch/arm64/boot/dts/qcom/x1-crd.dtsi | 2 +- arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi | 2 +- arch/arm64/boot/dts/qcom/x1e001de-devkit.dts | 4 ++-- arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts | 4 ++-- arch/arm64/boot/dts/qcom/x1e80100-asus-zenbook-a14.dts | 2 +- arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 2 +- .../boot/dts/qcom/x1e80100-dell-inspiron-14-plus-7441.dts | 2 +- arch/arm64/boot/dts/qcom/x1e80100-dell-latitude-7455.dts | 2 +- arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts | 4 ++-- arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts | 4 ++-- arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts | 4 ++-- arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 4 ++-- arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts | 2 +- arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts | 2 +- arch/arm64/boot/dts/qcom/x1p42100.dtsi | 4 ++-- 21 files changed, 29 insertions(+), 29 deletions(-) rename arch/arm64/boot/dts/qcom/{x1e80100-pmics.dtsi => hamoa-pmics.dtsi} (100%) rename arch/arm64/boot/dts/qcom/{x1e80100.dtsi => hamoa.dtsi} (100%) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi index 1aead50b8920..4de7c0abb25a 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi @@ -3,8 +3,8 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ -#include "x1e80100.dtsi" -#include "x1e80100-pmics.dtsi" +#include "hamoa.dtsi" +#include "hamoa-pmics.dtsi" #include #include diff --git a/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi b/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi similarity index 100% rename from arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi rename to arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi similarity index 100% rename from arch/arm64/boot/dts/qcom/x1e80100.dtsi rename to arch/arm64/boot/dts/qcom/hamoa.dtsi diff --git a/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi b/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi index ee3c8c5e2c50..69eccad1a09c 100644 --- a/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi @@ -11,7 +11,7 @@ #include #include -#include "x1e80100-pmics.dtsi" +#include "hamoa-pmics.dtsi" / { model = "ASUS Zenbook A14"; diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi index 3c9455fede5c..5e324f35547a 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -9,7 +9,7 @@ #include #include -#include "x1e80100-pmics.dtsi" +#include "hamoa-pmics.dtsi" / { model = "Qualcomm Technologies, Inc. X1E80100 CRD"; diff --git a/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi index cc64558ed5e6..10dc191c193a 100644 --- a/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi @@ -12,7 +12,7 @@ #include #include -#include "x1e80100-pmics.dtsi" +#include "hamoa-pmics.dtsi" / { chassis-type = "laptop"; diff --git a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts index bfc649d4b643..701f35af7d5c 100644 --- a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts +++ b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts @@ -8,8 +8,8 @@ #include #include -#include "x1e80100.dtsi" -#include "x1e80100-pmics.dtsi" +#include "hamoa.dtsi" +#include "hamoa-pmics.dtsi" / { model = "Qualcomm Technologies, Inc. X1E001DE Snapdragon Devkit for Windows"; diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi index 654cbce9d6ec..169726984d3b 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi @@ -12,8 +12,8 @@ #include #include -#include "x1e80100.dtsi" -#include "x1e80100-pmics.dtsi" +#include "hamoa.dtsi" +#include "hamoa-pmics.dtsi" / { model = "Lenovo ThinkPad T14s Gen 6"; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts index 0113d856b3ad..f2960953e608 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts @@ -11,8 +11,8 @@ #include #include -#include "x1e80100.dtsi" -#include "x1e80100-pmics.dtsi" +#include "hamoa.dtsi" +#include "hamoa-pmics.dtsi" / { model = "ASUS Vivobook S 15"; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-asus-zenbook-a14.dts b/arch/arm64/boot/dts/qcom/x1e80100-asus-zenbook-a14.dts index 0d0bcc50207d..c3cd04c9703d 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-asus-zenbook-a14.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-asus-zenbook-a14.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include "x1e80100.dtsi" +#include "hamoa.dtsi" #include "x1-asus-zenbook-a14.dtsi" / { diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts index dfc378e1a056..429deffcf3e9 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts @@ -5,7 +5,7 @@ /dts-v1/; -#include "x1e80100.dtsi" +#include "hamoa.dtsi" #include "x1-crd.dtsi" / { diff --git a/arch/arm64/boot/dts/qcom/x1e80100-dell-inspiron-14-plus-7441.dts b/arch/arm64/boot/dts/qcom/x1e80100-dell-inspiron-14-plus-7441.dts index cf2a7c262888..75e10d97c386 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-dell-inspiron-14-plus-7441.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-dell-inspiron-14-plus-7441.dts @@ -4,7 +4,7 @@ */ /dts-v1/; -#include "x1e80100.dtsi" +#include "hamoa.dtsi" #include "x1-dell-thena.dtsi" / { diff --git a/arch/arm64/boot/dts/qcom/x1e80100-dell-latitude-7455.dts b/arch/arm64/boot/dts/qcom/x1e80100-dell-latitude-7455.dts index 32ad9679550e..a8ff7ef258a1 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-dell-latitude-7455.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-dell-latitude-7455.dts @@ -4,7 +4,7 @@ */ /dts-v1/; -#include "x1e80100.dtsi" +#include "hamoa.dtsi" #include "x1-dell-thena.dtsi" / { diff --git a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts index 58f8caaa7258..c1f49cba61fc 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts @@ -12,8 +12,8 @@ #include #include -#include "x1e80100.dtsi" -#include "x1e80100-pmics.dtsi" +#include "hamoa.dtsi" +#include "hamoa-pmics.dtsi" / { model = "Dell XPS 13 9345"; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts b/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts index e5a839d45840..b79e59e1c413 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts @@ -6,8 +6,8 @@ /dts-v1/; -#include "x1e80100.dtsi" -#include "x1e80100-pmics.dtsi" +#include "hamoa.dtsi" +#include "hamoa-pmics.dtsi" #include "x1-hp-omnibook-x14.dtsi" / { diff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts index e0642fe8343f..56e4d13cca11 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts @@ -9,8 +9,8 @@ #include #include -#include "x1e80100.dtsi" -#include "x1e80100-pmics.dtsi" +#include "hamoa.dtsi" +#include "hamoa-pmics.dtsi" / { model = "Lenovo Yoga Slim 7x"; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi index ed468b93ba50..3b319f65dde1 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi @@ -9,8 +9,8 @@ #include #include -#include "x1e80100.dtsi" -#include "x1e80100-pmics.dtsi" +#include "hamoa.dtsi" +#include "hamoa-pmics.dtsi" / { aliases { diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index 4a9b6d791e7f..5a121fc44940 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -8,8 +8,8 @@ #include #include -#include "x1e80100.dtsi" -#include "x1e80100-pmics.dtsi" +#include "hamoa.dtsi" +#include "hamoa-pmics.dtsi" / { model = "Qualcomm Technologies, Inc. X1E80100 QCP"; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts b/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts index 6696cab2de3e..47ab0c5b3034 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts +++ b/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts @@ -3,7 +3,7 @@ /dts-v1/; #include "x1p42100.dtsi" -#include "x1e80100-pmics.dtsi" +#include "hamoa-pmics.dtsi" #include "x1-hp-omnibook-x14.dtsi" /delete-node/ &pmc8380_6; /delete-node/ &pmc8380_6_thermal; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts index 1ac46cdc4386..f7d372d2e961 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts +++ b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts @@ -14,7 +14,7 @@ #include #include "x1p42100.dtsi" -#include "x1e80100-pmics.dtsi" +#include "hamoa-pmics.dtsi" /delete-node/ &pmc8380_6; /delete-node/ &pmc8380_6_thermal; diff --git a/arch/arm64/boot/dts/qcom/x1p42100.dtsi b/arch/arm64/boot/dts/qcom/x1p42100.dtsi index 10d26958d3c6..2cecd2dd0de8 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1p42100.dtsi @@ -3,8 +3,8 @@ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. */ -/* X1P42100 is heavily based on X1E80100, with some meaningful differences */ -#include "x1e80100.dtsi" +/* X1P42100 is heavily based on hamoa, with some meaningful differences */ +#include "hamoa.dtsi" /delete-node/ &bwmon_cluster0; /delete-node/ &cluster_pd2; From 9a5b294dcc21f0b20b586206e5bab9969b4add1c Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 23 Sep 2025 14:01:56 +0300 Subject: [PATCH 034/138] arm64: dts: qcom: rename sm6150 to talos SM6150 and QCS615 are two names for the same die, collectively known as 'talos'. Follow the example of other platforms and rename SM6150 to talos.dtsi. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250923-rename-dts-v1-3-21888b68c781@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 2 +- arch/arm64/boot/dts/qcom/{sm6150.dtsi => talos.dtsi} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename arch/arm64/boot/dts/qcom/{sm6150.dtsi => talos.dtsi} (100%) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index 705ea71b07a1..e8faa25da79f 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -7,7 +7,7 @@ #include #include #include -#include "sm6150.dtsi" +#include "talos.dtsi" #include "pm8150.dtsi" / { model = "Qualcomm Technologies, Inc. QCS615 Ride"; diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi similarity index 100% rename from arch/arm64/boot/dts/qcom/sm6150.dtsi rename to arch/arm64/boot/dts/qcom/talos.dtsi From 4654433409914017618233daccfbf79876b2adfe Mon Sep 17 00:00:00 2001 From: Tingguo Cheng Date: Fri, 26 Sep 2025 12:09:27 +0800 Subject: [PATCH 035/138] arm64: dts: qcom: qcs8300-pmics: Remove 'allow-set-time' property Remove the 'allow-set-time' property from the rtc node because APPS is prohibited from setting the hardware RTC time. Signed-off-by: Tingguo Cheng Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250926-remove-rtc-allow-set-time-v1-1-76895a666939@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco-pmics.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi b/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi index a94b0bfa98dc..e990d7367719 100644 --- a/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi @@ -18,7 +18,6 @@ pmm8620au_0_rtc: rtc@6100 { reg = <0x6100>, <0x6200>; reg-names = "rtc", "alarm"; interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; - allow-set-time; }; pmm8620au_0_gpios: gpio@8800 { From f618fef3f1a97395f73d028d925b021b0b204bea Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 19 Sep 2025 11:57:25 +0200 Subject: [PATCH 036/138] arm64: dts: qcom: sm6350: Add MDSS_CORE reset to mdss Like on other platforms, if the OS does not support recovering the state left by the bootloader it needs access to MDSS_CORE, so that it can clear the MDSS configuration. Add a reference to the relevant reset. This also fixes display init on Linux v6.17. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250919-sm6350-mdss-reset-v1-3-48dcac917c73@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index dd009569a668..14788d60faf0 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -2164,6 +2164,8 @@ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, power-domains = <&dispcc MDSS_GDSC>; iommus = <&apps_smmu 0x800 0x2>; + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + #address-cells = <2>; #size-cells = <2>; ranges; From 172ca2d802482a622b84f24bb872760d71a4e368 Mon Sep 17 00:00:00 2001 From: Rakesh Kota Date: Fri, 19 Sep 2025 16:09:24 +0530 Subject: [PATCH 037/138] arm64: dts: qcom: qcs6490-rb3gen2: Update regulator settings Update min/max voltage settings for regulators below to align with the HW specification vreg_l3b_0p504 vreg_l6b_1p2 vreg_l11b_1p504 vreg_l14b_1p08 vreg_l16b_1p1 vreg_l17b_1p7 vreg_s1c_2p19 vreg_l8c_1p62 vreg_l9c_2p96 vreg_l12c_1p65. While at it, remove RPMH regulator rails (listed below) as these are not to be used on APPS, and any client accidently voting on it can potentially cause issues. vreg_s2b_0p876 vreg_s2c_0p752 vreg_s5c_0p752 vreg_s7c_0p752 vreg_s10c_0p752 vreg_l4b_0p752 vreg_l5b_0p752. Signed-off-by: Rakesh Kota Link: https://lore.kernel.org/r/20250919-b4-rb3gen2-update-regulator-v1-1-1ea9e70d01cb@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 58 +++----------------- 1 file changed, 9 insertions(+), 49 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 18cea8812001..6355c1e2c581 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -335,8 +335,6 @@ regulators-0 { vdd-s8-supply = <&vph_pwr>; vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p972>; vdd-l2-l7-supply = <&vreg_bob_3p296>; - vdd-l3-supply = <&vreg_s2b_0p876>; - vdd-l5-supply = <&vreg_s2b_0p876>; vdd-l6-l9-l10-supply = <&vreg_s8b_1p272>; vdd-l8-supply = <&vreg_s7b_0p972>; vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p872>; @@ -349,12 +347,6 @@ vreg_s1b_1p872: smps1 { regulator-max-microvolt = <2040000>; }; - vreg_s2b_0p876: smps2 { - regulator-name = "vreg_s2b_0p876"; - regulator-min-microvolt = <570070>; - regulator-max-microvolt = <1050000>; - }; - vreg_s7b_0p972: smps7 { regulator-name = "vreg_s7b_0p972"; regulator-min-microvolt = <535000>; @@ -385,27 +377,13 @@ vreg_l2b_3p072: ldo2 { vreg_l3b_0p504: ldo3 { regulator-name = "vreg_l3b_0p504"; regulator-min-microvolt = <312000>; - regulator-max-microvolt = <910000>; - regulator-initial-mode = ; - }; - - vreg_l4b_0p752: ldo4 { - regulator-name = "vreg_l4b_0p752"; - regulator-min-microvolt = <752000>; - regulator-max-microvolt = <820000>; - regulator-initial-mode = ; - }; - - reg_l5b_0p752: ldo5 { - regulator-name = "reg_l5b_0p752"; - regulator-min-microvolt = <552000>; - regulator-max-microvolt = <832000>; + regulator-max-microvolt = <650000>; regulator-initial-mode = ; }; vreg_l6b_1p2: ldo6 { regulator-name = "vreg_l6b_1p2"; - regulator-min-microvolt = <1140000>; + regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1260000>; regulator-initial-mode = ; }; @@ -436,7 +414,7 @@ vreg_l9b_1p2: ldo9 { vreg_l11b_1p504: ldo11 { regulator-name = "vreg_l11b_1p504"; - regulator-min-microvolt = <1504000>; + regulator-min-microvolt = <1776000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; @@ -457,7 +435,7 @@ vreg_l13b_0p53: ldo13 { vreg_l14b_1p08: ldo14 { regulator-name = "vreg_l14b_1p08"; - regulator-min-microvolt = <1080000>; + regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1304000>; regulator-initial-mode = ; }; @@ -521,26 +499,8 @@ regulators-1 { vreg_s1c_2p19: smps1 { regulator-name = "vreg_s1c_2p19"; - regulator-min-microvolt = <2190000>; - regulator-max-microvolt = <2210000>; - }; - - vreg_s2c_0p752: smps2 { - regulator-name = "vreg_s2c_0p752"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <800000>; - }; - - vreg_s5c_0p752: smps5 { - regulator-name = "vreg_s5c_0p752"; - regulator-min-microvolt = <465000>; - regulator-max-microvolt = <1050000>; - }; - - vreg_s7c_0p752: smps7 { - regulator-name = "vreg_s7c_0p752"; - regulator-min-microvolt = <465000>; - regulator-max-microvolt = <800000>; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2208000>; }; vreg_s9c_1p084: smps9 { @@ -600,7 +560,7 @@ vreg_l7c_3p0: ldo7 { vreg_l8c_1p62: ldo8 { regulator-name = "vreg_l8c_1p62"; - regulator-min-microvolt = <1620000>; + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; @@ -608,7 +568,7 @@ vreg_l8c_1p62: ldo8 { vreg_l9c_2p96: ldo9 { regulator-name = "vreg_l9c_2p96"; regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <35440000>; + regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; @@ -628,7 +588,7 @@ vreg_l11c_2p8: ldo11 { vreg_l12c_1p65: ldo12 { regulator-name = "vreg_l12c_1p65"; - regulator-min-microvolt = <1650000>; + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; From b91f5d73b67b1f49c250cd443e853ca72b81eaaa Mon Sep 17 00:00:00 2001 From: Jonathan Albrieux Date: Fri, 19 Sep 2025 16:49:32 +0200 Subject: [PATCH 038/138] arm64: dts: qcom: msm8916-longcheer-l8910: Add touchscreen The BQ Aquaris X5 (Longcheer L8910) has a Himax HX852x-ES touchscreen, which can now be described with the bindings recently added to linux-next. Add it to the device tree to allow using the touchscreen. Signed-off-by: Jonathan Albrieux Co-developed-by: Stephan Gerhold Signed-off-by: Stephan Gerhold Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250919-msm8916-l8910-touchscreen-v1-1-c46e56ec0a3b@gerhold.net Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8916-longcheer-l8910.dts | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts index 887764dc55b2..93d5ea279cff 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts @@ -79,6 +79,19 @@ led-0 { }; }; + reg_ts_vcca: regulator-vcca-ts { + compatible = "regulator-fixed"; + regulator-name = "regulator-vcca-ts"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 78 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&ts_vcca_default>; + pinctrl-names = "default"; + }; + usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; @@ -176,6 +189,25 @@ imu@68 { }; }; +&blsp_i2c5 { + status = "okay"; + + touchscreen@48 { + compatible = "himax,hx8527e", "himax,hx852es"; + reg = <0x48>; + + interrupts-extended = <&tlmm 13 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>; + vcca-supply = <®_ts_vcca>; + vccd-supply = <&pm8916_l6>; + + pinctrl-0 = <&ts_int_reset_default>; + pinctrl-names = "default"; + + linux,keycodes = ; + }; +}; + &blsp_uart2 { status = "okay"; pinctrl-0 = <&blsp_uart2_console_default>; @@ -338,6 +370,20 @@ spk_ext_pa_default: spk-ext-pa-default-state { bias-disable; }; + ts_int_reset_default: ts-int-reset-default-state { + pins = "gpio12", "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + ts_vcca_default: ts-vcca-default-state { + pins = "gpio78"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + usb_id_default: usb-id-default-state { pins = "gpio110"; function = "gpio"; From 5af8a9e8430ce62a4e12e58c687c43bae0d5863f Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Tue, 23 Sep 2025 21:41:07 +0530 Subject: [PATCH 039/138] arm64: dts: qcom: qcs6490-rb3gen2: Add firmware-name to QUPv3 nodes Traditionally, firmware loading for Serial Engines (SE) in the QUP hardware of Qualcomm SoCs has been managed by TrustZone (TZ). While this approach ensures secure SE assignment and access control, it limits flexibility for developers who need to enable various protocols on different SEs. Add the firmware-name property to QUPv3 nodes in the device tree to enable firmware loading from the Linux environment. Handle SE assignments and access control permissions directly within Linux, removing the dependency on TrustZone. Signed-off-by: Viken Dadhaniya Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250923161107.3541698-1-viken.dadhaniya@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 6355c1e2c581..721a26d49cca 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -969,10 +969,12 @@ &qup_uart7_tx { }; &qupv3_id_0 { + firmware-name = "qcom/qcs6490/qupv3fw.elf"; status = "okay"; }; &qupv3_id_1 { + firmware-name = "qcom/qcs6490/qupv3fw.elf"; status = "okay"; }; From 3f9fa03b7eb1f1105ace0f5981f97607e0c35b59 Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Wed, 24 Sep 2025 09:24:09 +0530 Subject: [PATCH 040/138] arm64: dts: qcom: lemans-evk: Add firmware-name to QUPv3 nodes Traditionally, firmware loading for Serial Engines (SE) in the QUP hardware of Qualcomm SoCs has been managed by TrustZone (TZ). While this approach ensures secure SE assignment and access control, it limits flexibility for developers who need to enable various protocols on different SEs. Add the firmware-name property to QUPv3 nodes in the device tree to enable firmware loading from the Linux environment. Handle SE assignments and access control permissions directly within Linux, removing the dependency on TrustZone. Signed-off-by: Viken Dadhaniya Reviewed-by: Dmitry Baryshkov Acked-by: Mukesh Kumar Savaliya Link: https://lore.kernel.org/r/20250924035409.3976652-1-viken.dadhaniya@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index c7dc9b8f4457..b21fa6bc36cf 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -588,14 +588,17 @@ &pcie1_phy { }; &qupv3_id_0 { + firmware-name = "qcom/sa8775p/qupv3fw.elf"; status = "okay"; }; &qupv3_id_1 { + firmware-name = "qcom/sa8775p/qupv3fw.elf"; status = "okay"; }; &qupv3_id_2 { + firmware-name = "qcom/sa8775p/qupv3fw.elf"; status = "okay"; }; From 30b5167b808c5a7eb8559bbd296fce14cb62e58d Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Thu, 25 Sep 2025 09:56:05 +0530 Subject: [PATCH 041/138] arm64: dts: qcom: monaco-evk: Add firmware-name to QUPv3 nodes Traditionally, firmware loading for Serial Engines (SE) in the QUP hardware of Qualcomm SoCs has been managed by TrustZone (TZ). While this approach ensures secure SE assignment and access control, it limits flexibility for developers who need to enable various protocols on different SEs. Add the firmware-name property to QUPv3 nodes in the device tree to enable firmware loading from the Linux environment. Handle SE assignments and access control permissions directly within Linux, removing the dependency on TrustZone. Signed-off-by: Viken Dadhaniya Link: https://lore.kernel.org/r/20250925042605.1388951-1-viken.dadhaniya@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco-evk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts index d9e9e65a137d..bb35893da73d 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk.dts +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts @@ -401,10 +401,12 @@ &iris { }; &qupv3_id_0 { + firmware-name = "qcom/qcs8300/qupv3fw.elf"; status = "okay"; }; &qupv3_id_1 { + firmware-name = "qcom/qcs8300/qupv3fw.elf"; status = "okay"; }; From ebb14a39c059694b588fc71bde72f88f9e72a11c Mon Sep 17 00:00:00 2001 From: Griffin Kroah-Hartman Date: Thu, 25 Sep 2025 12:07:30 +0200 Subject: [PATCH 042/138] arm64: dts: qcom: qcm6490-fairphone-fp5: Add vibrator support Add the required node for haptic playback (Awinic AW86927). Reviewed-by: Konrad Dybcio Signed-off-by: Griffin Kroah-Hartman Link: https://lore.kernel.org/r/20250925-aw86927-v3-3-1fc6265b42de@fairphone.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/qcm6490-fairphone-fp5.dts | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index 519e458e1a89..0ac3dbc2377d 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -780,7 +780,16 @@ ocp96011_sbu_mux: endpoint { }; }; - /* AW86927FCR haptics @ 5a */ + vibrator@5a { + compatible = "awinic,aw86927"; + reg = <0x5a>; + + interrupts-extended = <&tlmm 101 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&aw86927_int_default>; + pinctrl-names = "default"; + }; }; &i2c2 { @@ -1318,6 +1327,13 @@ usb_redrive_1v8_en_default: usb-redrive-1v8-en-default-state { bias-disable; output-high; }; + + aw86927_int_default: aw86927-int-default-state { + pins = "gpio101"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; }; &uart5 { From 4133486382364f60ea7e4f2c9070555689d9606e Mon Sep 17 00:00:00 2001 From: Dzmitry Sankouski Date: Fri, 26 Sep 2025 20:13:26 +0300 Subject: [PATCH 043/138] arm64: dts: qcom: sdm845-starqltechn: remove (address|size)-cells Drop the unused address/size-cells properties to silence the DT checker warning: pmic@66 (maxim,max77705): '#address-cells', '#size-cells' do not match any of the regexes: '^pinctrl-[0-9]+$' Fixes: 7a88a931d095 ("arm64: dts: qcom: sdm845-starqltechn: add max77705 PMIC") Reviewed-by: Konrad Dybcio Signed-off-by: Dzmitry Sankouski Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250926-starqltechn-correct_max77705_nodes-v5-1-c6ab35165534@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts index 75a53f0bbebd..45c7aa0f602d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts @@ -606,8 +606,6 @@ pmic@66 { interrupts = <11 IRQ_TYPE_LEVEL_LOW>; pinctrl-0 = <&pmic_int_default>; pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; leds { compatible = "maxim,max77705-rgb"; From 4372b15d89e253e40816f0bde100890cddd25a81 Mon Sep 17 00:00:00 2001 From: Dzmitry Sankouski Date: Fri, 26 Sep 2025 20:13:27 +0300 Subject: [PATCH 044/138] arm64: dts: qcom: sdm845-starqltechn: fix max77705 interrupts Since max77705 has a register, which indicates interrupt source, it acts as an interrupt controller. Direct MAX77705's subdevices to use the IC's internal interrupt controller, instead of listening to every interrupt fired by the chip towards the host device. Fixes: 7a88a931d095 ("arm64: dts: qcom: sdm845-starqltechn: add max77705 PMIC") Reviewed-by: Dmitry Baryshkov Signed-off-by: Dzmitry Sankouski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250926-starqltechn-correct_max77705_nodes-v5-2-c6ab35165534@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm845-samsung-starqltechn.dts | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts index 45c7aa0f602d..215e1491f3e9 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts @@ -599,11 +599,13 @@ &uart9 { &i2c14 { status = "okay"; - pmic@66 { + max77705: pmic@66 { compatible = "maxim,max77705"; reg = <0x66>; + #interrupt-cells = <1>; interrupt-parent = <&pm8998_gpios>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; pinctrl-0 = <&pmic_int_default>; pinctrl-names = "default"; @@ -644,8 +646,8 @@ max77705_charger: charger@69 { reg = <0x69>; compatible = "maxim,max77705-charger"; monitored-battery = <&battery>; - interrupt-parent = <&pm8998_gpios>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&max77705>; + interrupts = <0>; }; fuel-gauge@36 { @@ -653,8 +655,8 @@ fuel-gauge@36 { compatible = "maxim,max77705-battery"; power-supplies = <&max77705_charger>; maxim,rsns-microohm = <5000>; - interrupt-parent = <&pm8998_gpios>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&max77705>; + interrupts = <2>; }; }; From d7ec7d34237498fab7a6afed8da4b7139b0e387c Mon Sep 17 00:00:00 2001 From: Gergo Koteles Date: Sat, 27 Sep 2025 13:20:28 +0200 Subject: [PATCH 045/138] arm64: dts: qcom: sdm845-oneplus: Correct gpio used for slider The previous GPIO numbers were wrong. Update them to the correct ones and fix the label. Fixes: 288ef8a42612 ("arm64: dts: sdm845: add oneplus6/6t devices") Signed-off-by: Gergo Koteles Signed-off-by: David Heidelberg Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250927-slider-correct-v1-1-fb8cc7fdcedf@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index dcfffb271fcf..51a9a276399a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -803,8 +803,8 @@ hall_sensor_default: hall-sensor-default-state { bias-disable; }; - tri_state_key_default: tri-state-key-default-state { - pins = "gpio40", "gpio42", "gpio26"; + alert_slider_default: alert-slider-default-state { + pins = "gpio126", "gpio52", "gpio24"; function = "gpio"; drive-strength = <2>; bias-disable; From 1ade4b89d84656744acd60d5c826923451f5c23b Mon Sep 17 00:00:00 2001 From: Aleksandrs Vinarskis Date: Sat, 27 Sep 2025 15:21:35 +0200 Subject: [PATCH 046/138] dt-bindings: arm: qcom: Add Asus Zenbook A14 UX3407QA LCD/OLED variants X1/X1 Plus variant of the said device comes in either FHD+ OLED or FHD+ LCD panel, and shares the same model number UX3407QA. It appears LCD panel's brightness adjustment is PWM backlight controlled, so a dedicated device-tree is required. Introduce dedicated compatibles with fallback to 'asus,zenbook-a14-ux3407qa' as they are otherwise the same. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Aleksandrs Vinarskis Link: https://lore.kernel.org/r/20250927-zenbook-improvements-v3-1-d46c7368dc70@vinarskis.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 18b5ed044f9f..abdc39c025aa 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1083,7 +1083,13 @@ properties: - items: - enum: - - asus,zenbook-a14-ux3407qa + - asus,zenbook-a14-ux3407qa-lcd + - asus,zenbook-a14-ux3407qa-oled + - const: asus,zenbook-a14-ux3407qa + - const: qcom,x1p42100 + + - items: + - enum: - hp,omnibook-x14-fe1 - lenovo,thinkbook-16 - qcom,x1p42100-crd From 462b39931cab3415ffc47863a58372399e600f4f Mon Sep 17 00:00:00 2001 From: Aleksandrs Vinarskis Date: Sat, 27 Sep 2025 15:21:36 +0200 Subject: [PATCH 047/138] arm64: dts: qcom: Rework X1-based Asus Zenbook A14's displays The laptop comes in two variants: * UX3407RA, higher end, FHD+ OLED or WOXGA+ OLED panels * UX3407QA, lower end, FHD+ OLED or FHD+ LCD panels Even though all three panels work with "edp-panel", unfortunately the brightness adjustmenet of LCD panel is PWM based, requiring a dedicated device-tree. Convert "x1p42100-asus-zenbook-a14.dts" into ".dtsi" to allow for this split, introduce new LCD variant. Leave current variant without postfix and with the unchanged model name, as some distros (eg. Ubuntu) rely on this for automatic device-tree detection during kernel installation/upgrade. As dedicated device-tree is required, update compatibles of OLED variants to correct ones. Keep "edp-panel" as fallback, since it is enough to make the panels work. While at it moving .dts, .dtsi around, drop 'model' from the top level x1-asus-zenbook-a14.dtsi as well. Co-developed-by: Jens Glathe Signed-off-by: Jens Glathe Reviewed-by: Konrad Dybcio Signed-off-by: Aleksandrs Vinarskis Link: https://lore.kernel.org/r/20250927-zenbook-improvements-v3-2-d46c7368dc70@vinarskis.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../boot/dts/qcom/x1-asus-zenbook-a14.dtsi | 7 +- .../dts/qcom/x1e80100-asus-zenbook-a14.dts | 8 + .../qcom/x1p42100-asus-zenbook-a14-lcd.dts | 62 ++++++++ .../dts/qcom/x1p42100-asus-zenbook-a14.dts | 135 +---------------- .../dts/qcom/x1p42100-asus-zenbook-a14.dtsi | 138 ++++++++++++++++++ 6 files changed, 219 insertions(+), 133 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14-lcd.dts create mode 100644 arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 65a0e26b148c..e9f06fe17cbd 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -346,6 +346,8 @@ x1e80100-qcp-el2-dtbs := x1e80100-qcp.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e80100-qcp.dtb x1e80100-qcp-el2.dtb x1p42100-asus-zenbook-a14-el2-dtbs := x1p42100-asus-zenbook-a14.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p42100-asus-zenbook-a14.dtb x1p42100-asus-zenbook-a14-el2.dtb +x1p42100-asus-zenbook-a14-lcd-el2-dtbs := x1p42100-asus-zenbook-a14-lcd.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1p42100-asus-zenbook-a14-lcd.dtb x1p42100-asus-zenbook-a14-lcd-el2.dtb x1p42100-crd-el2-dtbs := x1p42100-crd.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p42100-crd.dtb x1p42100-crd-el2.dtb x1p42100-hp-omnibook-x14-el2-dtbs := x1p42100-hp-omnibook-x14.dtb x1-el2.dtbo diff --git a/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi b/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi index 69eccad1a09c..8e5c5575a532 100644 --- a/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi @@ -14,7 +14,6 @@ #include "hamoa-pmics.dtsi" / { - model = "ASUS Zenbook A14"; chassis-type = "laptop"; aliases { @@ -1005,14 +1004,10 @@ &mdss_dp3 { status = "okay"; aux-bus { - panel { + panel: panel { compatible = "edp-panel"; - enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; power-supply = <&vreg_edp_3p3>; - pinctrl-0 = <&edp_bl_en>; - pinctrl-names = "default"; - port { edp_panel_in: endpoint { remote-endpoint = <&mdss_dp3_out>; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-asus-zenbook-a14.dts b/arch/arm64/boot/dts/qcom/x1e80100-asus-zenbook-a14.dts index c3cd04c9703d..49b12a0a7cb1 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-asus-zenbook-a14.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-asus-zenbook-a14.dts @@ -22,6 +22,14 @@ &gpu_zap_shader { firmware-name = "qcom/x1e80100/ASUSTeK/zenbook-a14/qcdxkmsuc8380.mbn"; }; +&panel { + compatible = "samsung,atna40cu11", "samsung,atna33xc20"; + enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&edp_bl_en>; + pinctrl-names = "default"; +}; + &remoteproc_adsp { firmware-name = "qcom/x1e80100/ASUSTeK/zenbook-a14/qcadsp8380.mbn", "qcom/x1e80100/ASUSTeK/zenbook-a14/adsp_dtbs.elf"; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14-lcd.dts b/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14-lcd.dts new file mode 100644 index 000000000000..be756069131d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14-lcd.dts @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2025 Aleksandrs Vinarskis + */ + +/dts-v1/; + +#include "x1p42100-asus-zenbook-a14.dtsi" + +/ { + model = "ASUS Zenbook A14 (UX3407QA, LCD)"; + compatible = "asus,zenbook-a14-ux3407qa-lcd", "asus,zenbook-a14-ux3407qa", "qcom,x1p42100"; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pmk8550_pwm 0 416667>; + enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_bl>; + + pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>; + pinctrl-names = "default"; + }; + + vreg_edp_bl: regulator-edp-bl { + compatible = "regulator-fixed"; + + regulator-name = "VBL9"; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + + gpio = <&pmc8380_3_gpios 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_bl_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; +}; + +&panel { + backlight = <&backlight>; +}; + +&pmc8380_3_gpios { + edp_bl_reg_en: edp-bl-reg-en-state { + pins = "gpio10"; + function = "normal"; + }; +}; + +&pmk8550_gpios { + edp_bl_pwm: edp-bl-pwm-state { + pins = "gpio5"; + function = "func3"; + }; +}; + +&pmk8550_pwm { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dts b/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dts index bd75ff898601..68cd318d6907 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dts +++ b/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dts @@ -6,136 +6,17 @@ /dts-v1/; -#include "x1p42100.dtsi" -#include "x1-asus-zenbook-a14.dtsi" - -/delete-node/ &pmc8380_6; -/delete-node/ &pmc8380_6_thermal; +#include "x1p42100-asus-zenbook-a14.dtsi" / { model = "ASUS Zenbook A14 (UX3407QA)"; - compatible = "asus,zenbook-a14-ux3407qa", "qcom,x1p42100"; - - wcn6855-pmu { - compatible = "qcom,wcn6855-pmu"; - - vddaon-supply = <&vreg_wcn_0p95>; - vddio-supply = <&vreg_wcn_1p9>; - vddpcie1p3-supply = <&vreg_wcn_1p9>; - vddpcie1p9-supply = <&vreg_wcn_1p9>; - vddpmu-supply = <&vreg_wcn_0p95>; - vddpmucx-supply = <&vreg_wcn_0p95>; - vddpmumx-supply = <&vreg_wcn_0p95>; - vddrfa0p95-supply = <&vreg_wcn_0p95>; - vddrfa1p3-supply = <&vreg_wcn_1p9>; - vddrfa1p9-supply = <&vreg_wcn_1p9>; - - bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; - wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; - - pinctrl-0 = <&wcn_bt_en>, <&wcn_wlan_en>; - pinctrl-names = "default"; - - regulators { - vreg_pmu_rfa_cmn_0p8: ldo0 { - regulator-name = "vreg_pmu_rfa_cmn_0p8"; - }; - - vreg_pmu_aon_0p8: ldo1 { - regulator-name = "vreg_pmu_aon_0p8"; - }; - - vreg_pmu_wlcx_0p8: ldo2 { - regulator-name = "vreg_pmu_wlcx_0p8"; - }; - - vreg_pmu_wlmx_0p8: ldo3 { - regulator-name = "vreg_pmu_wlmx_0p8"; - }; - - vreg_pmu_btcmx_0p8: ldo4 { - regulator-name = "vreg_pmu_btcmx_0p8"; - }; - - vreg_pmu_pcie_1p8: ldo5 { - regulator-name = "vreg_pmu_pcie_1p8"; - }; - - vreg_pmu_pcie_0p9: ldo6 { - regulator-name = "vreg_pmu_pcie_0p9"; - }; - - vreg_pmu_rfa_0p8: ldo7 { - regulator-name = "vreg_pmu_rfa_0p8"; - }; - - vreg_pmu_rfa_1p2: ldo8 { - regulator-name = "vreg_pmu_rfa_1p2"; - }; - - vreg_pmu_rfa_1p7: ldo9 { - regulator-name = "vreg_pmu_rfa_1p7"; - }; - }; - }; + compatible = "asus,zenbook-a14-ux3407qa-oled", "asus,zenbook-a14-ux3407qa", "qcom,x1p42100"; }; -&gpu { - status = "okay"; -}; - -&gpu_zap_shader { - firmware-name = "qcom/x1p42100/ASUSTeK/zenbook-a14/qcdxkmsucpurwa.mbn"; -}; - -&pcie4_port0 { - wifi@0 { - compatible = "pci17cb,1103"; - reg = <0x10000 0x0 0x0 0x0 0x0>; - - vddaon-supply = <&vreg_pmu_aon_0p8>; - vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; - vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; - vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; - vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; - vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>; - vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; - vddwlmx-supply = <&vreg_pmu_wlmx_0p8>; - - qcom,calibration-variant = "UX3407Q"; - }; -}; - -&remoteproc_adsp { - firmware-name = "qcom/x1p42100/ASUSTeK/zenbook-a14/qcadsp8380.mbn", - "qcom/x1p42100/ASUSTeK/zenbook-a14/adsp_dtbs.elf"; - - status = "okay"; -}; - -&remoteproc_cdsp { - firmware-name = "qcom/x1p42100/ASUSTeK/zenbook-a14/qccdsp8380.mbn", - "qcom/x1p42100/ASUSTeK/zenbook-a14/cdsp_dtbs.elf"; - - status = "okay"; -}; - -&uart14 { - status = "okay"; - - bluetooth { - compatible = "qcom,wcn6855-bt"; - - vddaon-supply = <&vreg_pmu_aon_0p8>; - vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>; - vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; - vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; - vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>; - vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; - vddwlmx-supply = <&vreg_pmu_wlmx_0p8>; - - max-speed = <3000000>; - }; +&panel { + compatible = "samsung,atna40ct06", "samsung,atna33xc20"; + enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&edp_bl_en>; + pinctrl-names = "default"; }; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi b/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi new file mode 100644 index 000000000000..7ccb2076bab6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2025 Aleksandrs Vinarskis + */ + +/dts-v1/; + +#include "x1p42100.dtsi" +#include "x1-asus-zenbook-a14.dtsi" + +/delete-node/ &pmc8380_6; +/delete-node/ &pmc8380_6_thermal; + +/ { + wcn6855-pmu { + compatible = "qcom,wcn6855-pmu"; + + vddaon-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_wcn_1p9>; + vddpcie1p3-supply = <&vreg_wcn_1p9>; + vddpcie1p9-supply = <&vreg_wcn_1p9>; + vddpmu-supply = <&vreg_wcn_0p95>; + vddpmucx-supply = <&vreg_wcn_0p95>; + vddpmumx-supply = <&vreg_wcn_0p95>; + vddrfa0p95-supply = <&vreg_wcn_0p95>; + vddrfa1p3-supply = <&vreg_wcn_1p9>; + vddrfa1p9-supply = <&vreg_wcn_1p9>; + + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_bt_en>, <&wcn_wlan_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn_0p8: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn_0p8"; + }; + + vreg_pmu_aon_0p8: ldo1 { + regulator-name = "vreg_pmu_aon_0p8"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p8: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p8"; + }; + + vreg_pmu_btcmx_0p8: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p8"; + }; + + vreg_pmu_pcie_1p8: ldo5 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo6 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_rfa_0p8: ldo7 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo8 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p7: ldo9 { + regulator-name = "vreg_pmu_rfa_1p7"; + }; + }; + }; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1p42100/ASUSTeK/zenbook-a14/qcdxkmsucpurwa.mbn"; +}; + +&pcie4_port0 { + wifi@0 { + compatible = "pci17cb,1103"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p8>; + + qcom,calibration-variant = "UX3407Q"; + }; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1p42100/ASUSTeK/zenbook-a14/qcadsp8380.mbn", + "qcom/x1p42100/ASUSTeK/zenbook-a14/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1p42100/ASUSTeK/zenbook-a14/qccdsp8380.mbn", + "qcom/x1p42100/ASUSTeK/zenbook-a14/cdsp_dtbs.elf"; + + status = "okay"; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn6855-bt"; + + vddaon-supply = <&vreg_pmu_aon_0p8>; + vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p8>; + + max-speed = <3000000>; + }; +}; From c2ca1cc0d465ca56be7ddde40b366b5fc63c2f99 Mon Sep 17 00:00:00 2001 From: Aleksandrs Vinarskis Date: Sat, 27 Sep 2025 15:21:37 +0200 Subject: [PATCH 048/138] arm64: dts: qcom: x1e80100-asus-zenbook-a14: Enable WiFi, Bluetooth Unlike UX3407QA with WCN6855, UX3407RA comes with WCN7850. Definitions were not added during initial bringup due to lack of hardware to test it. Add missing definitions that were now confirmed to work. Reviewed-by: Konrad Dybcio Signed-off-by: Aleksandrs Vinarskis Link: https://lore.kernel.org/r/20250927-zenbook-improvements-v3-3-d46c7368dc70@vinarskis.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/x1e80100-asus-zenbook-a14.dts | 94 +++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-asus-zenbook-a14.dts b/arch/arm64/boot/dts/qcom/x1e80100-asus-zenbook-a14.dts index 49b12a0a7cb1..0408ade7150f 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-asus-zenbook-a14.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-asus-zenbook-a14.dts @@ -12,6 +12,65 @@ / { model = "ASUS Zenbook A14 (UX3407RA)"; compatible = "asus,zenbook-a14-ux3407ra", "qcom,x1e80100"; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_bt_en>, <&wcn_wlan_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &gpu { @@ -22,6 +81,23 @@ &gpu_zap_shader { firmware-name = "qcom/x1e80100/ASUSTeK/zenbook-a14/qcdxkmsuc8380.mbn"; }; +&pcie4_port0 { + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + }; +}; + &panel { compatible = "samsung,atna40cu11", "samsung,atna33xc20"; enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; @@ -43,3 +119,21 @@ &remoteproc_cdsp { status = "okay"; }; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + + max-speed = <3000000>; + }; +}; From 8388ebac980201382941600d4d9a2dc0bc1c9db4 Mon Sep 17 00:00:00 2001 From: Xilin Wu Date: Mon, 29 Sep 2025 14:46:41 +0800 Subject: [PATCH 049/138] dt-bindings: arm: qcom: Add Radxa Dragon Q6A Radxa Dragon Q6A is a single board computer, based on the Qualcomm QCS6490 platform. Document the top-level compatible for this board. Acked-by: Krzysztof Kozlowski Signed-off-by: Xilin Wu Link: https://lore.kernel.org/r/20250929-radxa-dragon-q6a-v5-1-aa96ffc352f8@radxa.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index abdc39c025aa..850bd9180bab 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -340,6 +340,7 @@ properties: - particle,tachyon - qcom,qcm6490-idp - qcom,qcs6490-rb3gen2 + - radxa,dragon-q6a - shift,otter - const: qcom,qcm6490 From ef254b12ec60c2672c18dbf423bd16476a7fb62e Mon Sep 17 00:00:00 2001 From: Xilin Wu Date: Mon, 29 Sep 2025 14:46:42 +0800 Subject: [PATCH 050/138] arm64: dts: qcom: qcs6490: Introduce Radxa Dragon Q6A Radxa Dragon Q6A is a single board computer, based on the Qualcomm QCS6490 platform. Features enabled and working: - Configurable I2C/SPI/UART from 40-Pin GPIO - Three USB-A 2.0 ports - RTL8111K Ethernet connected to PCIe0 - eMMC module - SD card - M.2 M-Key 2230 PCIe 3.0 x2 - Headphone jack - Onboard thermal sensors - QSPI controller for updating boot firmware - ADSP remoteproc (Type-C and charging features disabled in firmware) - CDSP remoteproc (for AI applications using QNN) - Venus video encode and decode accelerator Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Xilin Wu Link: https://lore.kernel.org/r/20250929-radxa-dragon-q6a-v5-2-aa96ffc352f8@radxa.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../dts/qcom/qcs6490-radxa-dragon-q6a.dts | 1095 +++++++++++++++++ 2 files changed, 1096 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index e9f06fe17cbd..44391fd19939 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -128,6 +128,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcs6490-radxa-dragon-q6a.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb qcs6490-rb3gen2-vision-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2-vision-mezzanine.dtbo diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts new file mode 100644 index 000000000000..a63f79b0844c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts @@ -0,0 +1,1095 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Radxa Computer (Shenzhen) Co., Ltd. + */ + +/dts-v1/; + +/* PM7250B is configured to use SID8/9 */ +#define PM7250B_SID 8 +#define PM7250B_SID1 9 + +#include +#include +#include +#include +#include +#include "sc7280.dtsi" +#include "pm7250b.dtsi" +#include "pm7325.dtsi" +#include "pm8350c.dtsi" /* PM7350C */ +#include "pmk8350.dtsi" /* PMK7325 */ +#include "qcs6490-audioreach.dtsi" + +/delete-node/ &adsp_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &mpss_mem; +/delete-node/ &remoteproc_mpss; +/delete-node/ &remoteproc_wpss; +/delete-node/ &rmtfs_mem; +/delete-node/ &video_mem; +/delete-node/ &wifi; +/delete-node/ &wlan_ce_mem; +/delete-node/ &wlan_fw_mem; +/delete-node/ &wpss_mem; +/delete-node/ &xbl_mem; + +/ { + model = "Radxa Dragon Q6A"; + compatible = "radxa,dragon-q6a", "qcom,qcm6490"; + chassis-type = "embedded"; + + aliases { + mmc0 = &sdhc_1; + mmc1 = &sdhc_2; + serial0 = &uart5; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9380-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + reset-gpios = <&tlmm 83 GPIO_ACTIVE_LOW>; + + vdd-rxtx-supply = <&vreg_l18b_1p8>; + vdd-io-supply = <&vreg_l18b_1p8>; + vdd-buck-supply = <&vreg_l17b_1p8>; + vdd-mic-bias-supply = <&vreg_bob_3p296>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + qcom,hphl-jack-type-normally-closed; + + #sound-dai-cells = <1>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + usb2_1_con: connector-0 { + compatible = "usb-a-connector"; + vbus-supply = <&vcc_5v_peri>; + + port { + usb2_1_connector: endpoint { + remote-endpoint = <&usb_hub_2_1>; + }; + }; + }; + + usb2_2_con: connector-1 { + compatible = "usb-a-connector"; + vbus-supply = <&vcc_5v_peri>; + + port { + usb2_2_connector: endpoint { + remote-endpoint = <&usb_hub_2_2>; + }; + }; + }; + + usb2_3_con: connector-2 { + compatible = "usb-a-connector"; + vbus-supply = <&vcc_5v_peri>; + + port { + usb2_3_connector: endpoint { + remote-endpoint = <&usb_hub_2_3>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&user_led>; + pinctrl-names = "default"; + + user-led { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + panic-indicator; + }; + }; + + reserved-memory { + xbl_mem: xbl@80700000 { + reg = <0x0 0x80700000 0x0 0x100000>; + no-map; + }; + + cdsp_secure_heap_mem: cdsp-secure-heap@81800000 { + reg = <0x0 0x81800000 0x0 0x1e00000>; + no-map; + }; + + camera_mem: camera@84300000 { + reg = <0x0 0x84300000 0x0 0x500000>; + no-map; + }; + + adsp_mem: adsp@84800000 { + reg = <0x0 0x84800000 0x0 0x2800000>; + no-map; + }; + + cdsp_mem: cdsp@87000000 { + reg = <0x0 0x87000000 0x0 0x1e00000>; + no-map; + }; + + video_mem: video@88e00000 { + reg = <0x0 0x88e00000 0x0 0x700000>; + no-map; + }; + + cvp_mem: cvp@89500000 { + reg = <0x0 0x89500000 0x0 0x500000>; + no-map; + }; + + gpu_microcode_mem: gpu-microcode@89a00000 { + reg = <0x0 0x89a00000 0x0 0x2000>; + no-map; + }; + + tz_stat_mem: tz-stat@c0000000 { + reg = <0x0 0xc0000000 0x0 0x100000>; + no-map; + }; + + tags_mem: tags@c0100000 { + reg = <0x0 0xc0100000 0x0 0x1200000>; + no-map; + }; + + qtee_mem: qtee@c1300000 { + reg = <0x0 0xc1300000 0x0 0x500000>; + no-map; + }; + + trusted_apps_mem: trusted-apps@c1800000 { + reg = <0x0 0xc1800000 0x0 0x1c00000>; + no-map; + }; + + debug_vm_mem: debug-vm@d0600000 { + reg = <0x0 0xd0600000 0x0 0x100000>; + no-map; + }; + }; + + thermal-zones { + msm-skin-thermal { + polling-delay-passive = <0>; + thermal-sensors = <&pmk8350_adc_tm 2>; + }; + + quiet-thermal { + polling-delay-passive = <0>; + thermal-sensors = <&pmk8350_adc_tm 1>; + }; + + ufs-thermal { + polling-delay-passive = <0>; + thermal-sensors = <&pmk8350_adc_tm 3>; + }; + + xo-thermal { + polling-delay-passive = <0>; + thermal-sensors = <&pmk8350_adc_tm 0>; + }; + }; + + vcc_1v8: regulator-vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_5v_peri>; + + regulator-boot-on; + regulator-always-on; + }; + + vcc_3v3: regulator-vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_5v_peri>; + + regulator-boot-on; + regulator-always-on; + }; + + vcc_5v_peri: regulator-vcc-5v-peri { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v_peri"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vph_pwr>; + + regulator-boot-on; + regulator-always-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-boot-on; + regulator-always-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm7325-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p536>; + vdd-l2-l7-supply = <&vreg_bob_3p296>; + vdd-l6-l9-l10-supply = <&vreg_s8b_1p2>; + vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p84>; + + vreg_s1b_1p84: smps1 { + regulator-name = "vreg_s1b_1p84"; + regulator-min-microvolt = <1840000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7b_0p536: smps7 { + regulator-name = "vreg_s7b_0p536"; + regulator-min-microvolt = <536000>; + regulator-max-microvolt = <1120000>; + }; + + vreg_s8b_1p2: smps8 { + regulator-name = "vreg_s8b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1496000>; + regulator-initial-mode = ; + }; + + vreg_l1b_0p912: ldo1 { + regulator-name = "vreg_l1b_0p912"; + regulator-min-microvolt = <832000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2b_3p072: ldo2 { + regulator-name = "vreg_l2b_3p072"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l6b_1p2: ldo6 { + regulator-name = "vreg_l6b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7b_2p96: ldo7 { + regulator-name = "vreg_l7b_2p96"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9b_1p2: ldo9 { + regulator-name = "vreg_l9b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l17b_1p8: ldo17 { + regulator-name = "vreg_l17b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1896000>; + regulator-initial-mode = ; + }; + + vreg_l18b_1p8: ldo18 { + regulator-name = "vreg_l18b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l19b_1p8: ldo19 { + regulator-name = "vreg_l19b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-l1-l12-supply = <&vreg_s1b_1p84>; + vdd-l6-l9-l11-supply = <&vreg_bob_3p296>; + vdd-l10-supply = <&vreg_s7b_0p536>; + vdd-bob-supply = <&vph_pwr>; + + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1976000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l6c_2p96: ldo6 { + regulator-name = "vreg_l6c_2p96"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9c_2p96: ldo9 { + regulator-name = "vreg_l9c_2p96"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l10c_0p88: ldo10 { + regulator-name = "vreg_l10c_0p88"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1048000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_bob_3p296: bob { + regulator-name = "vreg_bob_3p296"; + regulator-min-microvolt = <3032000>; + regulator-max-microvolt = <3960000>; + }; + }; +}; + +&gcc { + protected-clocks = , + , + , + , + , + , + , + , + , + , + ; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcs6490/a660_zap.mbn"; +}; + +/* Pin 13, 15 in GPIO header */ +&i2c0 { + qcom,enable-gsi-dma; + status = "okay"; +}; + +/* Pin 27, 28 in GPIO header */ +&i2c2 { + qcom,enable-gsi-dma; + status = "okay"; +}; + +/* Pin 3, 5 in GPIO header */ +&i2c6 { + qcom,enable-gsi-dma; + status = "okay"; +}; + +&i2c10 { + qcom,enable-gsi-dma; + status = "okay"; + + rtc: rtc@68 { + compatible = "st,m41t11"; + reg = <0x68>; + }; +}; + +/* External touchscreen */ +&i2c13 { + qcom,enable-gsi-dma; + status = "okay"; +}; + +&lpass_audiocc { + compatible = "qcom,qcm6490-lpassaudiocc"; + /delete-property/ power-domains; +}; + +&lpass_rx_macro { + status = "okay"; +}; + +&lpass_tx_macro { + status = "okay"; +}; + +&lpass_va_macro { + status = "okay"; +}; + +&pcie0 { + perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&pcie1 { + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie1_clkreq_n>, <&pcie1_reset_n>, <&pcie1_wake_n>; + pinctrl-names = "default"; + + /* Support for QPS615 PCIe switch */ + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>, + <0x208 &apps_smmu 0x1c84 0x1>, + <0x210 &apps_smmu 0x1c85 0x1>, + <0x218 &apps_smmu 0x1c86 0x1>, + <0x300 &apps_smmu 0x1c87 0x1>, + <0x400 &apps_smmu 0x1c88 0x1>, + <0x500 &apps_smmu 0x1c89 0x1>, + <0x501 &apps_smmu 0x1c90 0x1>; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&pm7325_gpios { + pm7325_adc_default: adc-default-state { + pins = "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-high-impedance; + }; +}; + +&pm7325_temp_alarm { + io-channels = <&pmk8350_vadc PM7325_ADC7_DIE_TEMP>; + io-channel-names = "thermal"; +}; + +&pmk8350_adc_tm { + status = "okay"; + + xo-therm@0 { + reg = <0>; + io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + quiet-therm@1 { + reg = <1>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + msm-skin-therm@2 { + reg = <2>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + ufs-therm@3 { + reg = <3>; + io-channels = <&pmk8350_vadc PM7325_ADC7_GPIO1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pmk8350_vadc { + pinctrl-0 = <&pm7325_adc_default>; + pinctrl-names = "default"; + + channel@3 { + reg = ; + label = "pmk7325_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@44 { + reg = ; + label = "xo_therm"; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + }; + + channel@103 { + reg = ; + label = "pm7325_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@144 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "quiet_therm"; + }; + + channel@146 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "msm_skin_therm"; + }; + + channel@14a { + /* According to datasheet, 0x4a = AMUX1_GPIO = GPIO_02 */ + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "ufs_therm"; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&qspi { + /* It's not possible to use QSPI with iommu */ + /* due to an error in qcom_smmu_write_s2cr */ + /delete-property/ iommus; + + pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, + <&qspi_data1>, <&qspi_data23>; + pinctrl-1 = <&qspi_sleep>; + pinctrl-names = "default", "sleep"; + + status = "okay"; + + spi_flash: flash@0 { + compatible = "winbond,w25q256", "jedec,spi-nor"; + reg = <0>; + + spi-max-frequency = <104000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&qupv3_id_0 { + firmware-name = "qcom/qcm6490/qupv3fw.elf"; + status = "okay"; +}; + +&qupv3_id_1 { + firmware-name = "qcom/qcm6490/qupv3fw.elf"; + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/qcs6490/radxa/dragon-q6a/adsp.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcs6490/cdsp.mbn"; + status = "okay"; +}; + +&sdhc_1 { + non-removable; + no-sd; + no-sdio; + + vmmc-supply = <&vreg_l7b_2p96>; + vqmmc-supply = <&vreg_l19b_1p8>; + + status = "okay"; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>, <&sd_cd>; + pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>, <&sd_cd>; + + vmmc-supply = <&vreg_l9c_2p96>; + vqmmc-supply = <&vreg_l6c_2p96>; + + cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&sound { + compatible = "qcom,qcs6490-rb3gen2-sndcard"; + model = "QCS6490-Radxa-Dragon-Q6A"; + + audio-routing = "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "TX SWR_ADC1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + codec { + sound-dai = <&wcd938x 0>, <&swr0 0>, <&lpass_rx_macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + codec { + sound-dai = <&wcd938x 1>, <&swr1 0>, <&lpass_tx_macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; +}; + +/* Pin 11, 29, 31, 32 in GPIO header */ +&spi7 { + qcom,enable-gsi-dma; + status = "okay"; +}; + +/* Pin 19, 21, 23, 24, 26 in GPIO header */ +&spi12 { + qcom,enable-gsi-dma; + status = "okay"; +}; + +/* Pin 22, 33, 36, 37 in GPIO header */ +&spi14 { + qcom,enable-gsi-dma; + status = "okay"; +}; + +&swr0 { + status = "okay"; + + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr1 { + status = "okay"; + + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <1 1 2 3>; + }; +}; + +&tlmm { + gpio-line-names = + /* GPIO_0 ~ GPIO_3 */ + "PIN_13", "PIN_15", "", "", + /* GPIO_4 ~ GPIO_7 */ + "", "", "", "", + /* GPIO_8 ~ GPIO_11 */ + "PIN_27", "PIN_28", "", "", + /* GPIO_12 ~ GPIO_15 */ + "", "", "", "", + /* GPIO_16 ~ GPIO_19 */ + "", "", "", "", + /* GPIO_20 ~ GPIO_23 */ + "", "", "PIN_8", "PIN_10", + /* GPIO_24 ~ GPIO_27 */ + "PIN_3", "PIN_5", "PIN_16", "PIN_27", + /* GPIO_28 ~ GPIO_31 */ + "PIN_31", "PIN_11", "PIN_32", "PIN_29", + /* GPIO_32 ~ GPIO_35 */ + "", "", "", "", + /* GPIO_36 ~ GPIO_39 */ + "", "", "", "", + /* GPIO_40 ~ GPIO_43 */ + "", "", "", "", + /* GPIO_44 ~ GPIO_47 */ + "", "", "", "", + /* GPIO_48 ~ GPIO_51 */ + "PIN_21", "PIN_19", "PIN_23", "PIN_24", + /* GPIO_52 ~ GPIO_55 */ + "", "", "", "PIN_26", + /* GPIO_56 ~ GPIO_59 */ + "PIN_33", "PIN_22", "PIN_37", "PIN_36", + /* GPIO_60 ~ GPIO_63 */ + "", "", "", "", + /* GPIO_64 ~ GPIO_67 */ + "", "", "", "", + /* GPIO_68 ~ GPIO_71 */ + "", "", "", "", + /* GPIO_72 ~ GPIO_75 */ + "", "", "", "", + /* GPIO_76 ~ GPIO_79 */ + "", "", "", "", + /* GPIO_80 ~ GPIO_83 */ + "", "", "", "", + /* GPIO_84 ~ GPIO_87 */ + "", "", "", "", + /* GPIO_88 ~ GPIO_91 */ + "", "", "", "", + /* GPIO_92 ~ GPIO_95 */ + "", "", "", "", + /* GPIO_96 ~ GPIO_99 */ + "PIN_7", "PIN_12", "PIN_38", "PIN_40", + /* GPIO_100 ~ GPIO_103 */ + "PIN_35", "", "", "", + /* GPIO_104 ~ GPIO_107 */ + "", "", "", "", + /* GPIO_108 ~ GPIO_111 */ + "", "", "", "", + /* GPIO_112 ~ GPIO_115 */ + "", "", "", "", + /* GPIO_116 ~ GPIO_119 */ + "", "", "", "", + /* GPIO_120 ~ GPIO_123 */ + "", "", "", "", + /* GPIO_124 ~ GPIO_127 */ + "", "", "", "", + /* GPIO_128 ~ GPIO_131 */ + "", "", "", "", + /* GPIO_132 ~ GPIO_135 */ + "", "", "", "", + /* GPIO_136 ~ GPIO_139 */ + "", "", "", "", + /* GPIO_140 ~ GPIO_143 */ + "", "", "", "", + /* GPIO_144 ~ GPIO_147 */ + "", "", "", "", + /* GPIO_148 ~ GPIO_151 */ + "", "", "", "", + /* GPIO_152 ~ GPIO_155 */ + "", "", "", "", + /* GPIO_156 ~ GPIO_159 */ + "", "", "", "", + /* GPIO_160 ~ GPIO_163 */ + "", "", "", "", + /* GPIO_164 ~ GPIO_167 */ + "", "", "", "", + /* GPIO_168 ~ GPIO_171 */ + "", "", "", "", + /* GPIO_172 ~ GPIO_174 */ + "", "", ""; + + pcie0_reset_n: pcie0-reset-n-state { + pins = "gpio87"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie0_wake_n: pcie0-wake-n-state { + pins = "gpio89"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + pcie1_reset_n: pcie1-reset-n-state { + pins = "gpio2"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie1_wake_n: pcie1-wake-n-state { + pins = "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + qspi_sleep: qspi-sleep-state { + pins = "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17"; + function = "gpio"; + output-disable; + }; + + sd_cd: sd-cd-state { + pins = "gpio91"; + function = "gpio"; + bias-pull-up; + }; + + user_led: user-led-state { + pins = "gpio42"; + function = "gpio"; + bias-pull-up; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio83"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&uart5 { + status = "okay"; +}; + +&usb_2 { + dr_mode = "host"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + /* Onboard USB 2.0 hub */ + usb_hub_2_x: hub@1 { + compatible = "usb1a40,0101"; + reg = <1>; + vdd-supply = <&vcc_5v_peri>; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + usb_hub_2_1: endpoint { + remote-endpoint = <&usb2_1_connector>; + }; + }; + + port@2 { + reg = <2>; + + usb_hub_2_2: endpoint { + remote-endpoint = <&usb2_2_connector>; + }; + }; + + port@3 { + reg = <3>; + + usb_hub_2_3: endpoint { + remote-endpoint = <&usb2_3_connector>; + }; + }; + }; + + /* FCU760K Wi-Fi & Bluetooth module */ + wifi@4 { + compatible = "usba69c,8d80"; + reg = <4>; + }; + }; +}; + +&usb_2_hsphy { + vdda-pll-supply = <&vreg_l10c_0p88>; + vdda33-supply = <&vreg_l2b_3p072>; + vdda18-supply = <&vreg_l1c_1p8>; + + status = "okay"; +}; + +&venus { + status = "okay"; +}; + +/* PINCTRL - additions to nodes defined in sc7280.dtsi */ +&pcie0_clkreq_n { + bias-pull-up; + drive-strength = <2>; +}; + +&pcie1_clkreq_n { + bias-pull-up; + drive-strength = <2>; +}; + +&qspi_clk { + bias-disable; + drive-strength = <16>; +}; + +&qspi_cs0 { + bias-disable; + drive-strength = <8>; +}; + +&qspi_data0 { + bias-disable; + drive-strength = <8>; +}; + +&qspi_data1 { + bias-disable; + drive-strength = <8>; +}; + +&qspi_data23 { + bias-disable; + drive-strength = <8>; +}; + +&sdc1_clk { + bias-disable; + drive-strength = <16>; +}; + +&sdc1_cmd { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc1_data { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc1_rclk { + bias-pull-down; +}; + +&sdc2_clk { + bias-disable; + drive-strength = <16>; +}; + +&sdc2_cmd { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc2_data { + bias-pull-up; + drive-strength = <10>; +}; From 8b4faf419d601cead68d7821618369e2c0338b86 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Tue, 30 Sep 2025 09:37:22 +0200 Subject: [PATCH 051/138] arm64: dts: qcom: sm8250: Add MDSS_CORE reset to mdss Like on other platforms, if the OS does not support recovering the state left by the bootloader it needs access to MDSS_CORE, so that it can clear the MDSS configuration. Add a reference to the relevant reset. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Tested-by: Dmitry Baryshkov # RB5 Link: https://lore.kernel.org/r/20250930-sm8250-mdss-reset-v1-1-a64522d91f12@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 8248ac3119f1..d30b3bc2db9e 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4684,6 +4684,8 @@ mdss: display-subsystem@ae00000 { iommus = <&apps_smmu 0x820 0x402>; + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + status = "disabled"; #address-cells = <2>; From 3d4142cac46b4dde4e60908c509c4cf107067114 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Tue, 30 Sep 2025 15:57:01 +0200 Subject: [PATCH 052/138] arm64: dts: qcom: qcm6490-fairphone-fp5: Add supplies to simple-fb node Add the OLED power supplies to the simple-framebuffer node, so that the regulators don't get turned off while the simple-fb is being used. Fixes: c365a026155c ("arm64: dts: qcom: qcm6490-fairphone-fp5: Enable display") Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250930-sc7280-dts-misc-v1-1-5a45923ef705@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index 0ac3dbc2377d..a8314656e6b5 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -47,6 +47,8 @@ framebuffer0: framebuffer@a000000 { stride = <(1224 * 4)>; format = "a8r8g8b8"; clocks = <&gcc GCC_DISP_HF_AXI_CLK>; + vci-supply = <&vreg_oled_vci>; + dvdd-supply = <&vreg_oled_dvdd>; }; }; From 99dc57012dd67c251cfbfd0ba501ecc524b621fc Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Tue, 30 Sep 2025 15:57:02 +0200 Subject: [PATCH 053/138] arm64: dts: qcom: qcm6490-fairphone-fp5: Add VTOF_LDO_2P8 regulator Describe yet another regulator-fixed on this board, powering the ToF sensor. Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20250930-sc7280-dts-misc-v1-2-5a45923ef705@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index a8314656e6b5..2813251a42cd 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -195,6 +195,19 @@ vreg_usb_redrive_1v8: regulator-usb-redrive-1v8 { pinctrl-names = "default"; }; + vreg_vtof_ldo_2p8: regulator-vtof-ldo-2p8 { + compatible = "regulator-fixed"; + regulator-name = "VTOF_LDO_2P8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <233>; + + gpio = <&tlmm 141 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vreg_bob>; + }; + reserved-memory { cont_splash_mem: cont-splash@e1000000 { reg = <0x0 0xe1000000 0x0 0x2300000>; From c207f5319d17ae2d8447c89ef32e5d297709f222 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Tue, 30 Sep 2025 15:57:03 +0200 Subject: [PATCH 054/138] arm64: dts: qcom: qcm6490-fairphone-fp5: Use correct compatible for audiocc Use the correct compatible for this phone with standard Qualcomm firmware and remove references to power-domains from a 'reserved' node. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250930-sc7280-dts-misc-v1-3-5a45923ef705@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index 2813251a42cd..ea1d3acd975b 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -863,6 +863,11 @@ &ipa { status = "okay"; }; +&lpass_audiocc { + compatible = "qcom,qcm6490-lpassaudiocc"; + /delete-property/ power-domains; +}; + &mdss { status = "okay"; }; From 1a3051614f6d0e0e9f5725032ebbaa434fd1aec3 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Tue, 30 Sep 2025 15:57:04 +0200 Subject: [PATCH 055/138] arm64: dts: qcom: qcm6490-shift-otter: Use correct compatible for audiocc Use the correct compatible for this phone with standard Qualcomm firmware and remove references to power-domains from a 'reserved' node. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250930-sc7280-dts-misc-v1-4-5a45923ef705@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts index eb8efba1b9dd..6be2ebb2958f 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts @@ -568,6 +568,11 @@ &ipa { status = "okay"; }; +&lpass_audiocc { + compatible = "qcom,qcm6490-lpassaudiocc"; + /delete-property/ power-domains; +}; + &pm7250b_adc { channel@4d { reg = ; From 037f0f59bb0f43bda3d3f0892f9bf65a64c173e2 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Tue, 30 Sep 2025 15:57:05 +0200 Subject: [PATCH 056/138] arm64: dts: qcom: sm7325-nothing-spacewar: Use correct compatible for audiocc Use the correct compatible for this phone with standard Qualcomm firmware and remove references to power-domains from a 'reserved' node. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250930-sc7280-dts-misc-v1-5-5a45923ef705@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts b/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts index f16b47b6a74c..cb59c122f6f6 100644 --- a/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts +++ b/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts @@ -978,6 +978,11 @@ &ipa { status = "okay"; }; +&lpass_audiocc { + compatible = "qcom,qcm6490-lpassaudiocc"; + /delete-property/ power-domains; +}; + &mdss { status = "okay"; }; From c2703c90161b45bca5b65f362adbae02ed71fcc1 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 7 Oct 2025 20:53:44 +0200 Subject: [PATCH 057/138] arm64: dts: qcom: sm8650: set ufs as dma coherent The UFS device is ovbiously dma coherent like the other IOMMU devices like usb, mmc, ... let's fix this by adding the flag. To be sure an extensive test has been performed to be sure it's safe, as downstream uses this flag for UFS as well. As an experiment, I checked how the dma-coherent could impact the UFS bandwidth, and it happens the max bandwidth on cached write is slighly highter (up to 10%) while using less cpu time since cache sync/flush is skipped. Fixes: 10e024671295 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes") Signed-off-by: Neil Armstrong Reviewed-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251007-topic-sm8650-upstream-ufs-dma-coherent-v1-1-f3cfeaee04ce@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index ebf1971b1bfb..3b03c1353938 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3988,6 +3988,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, iommus = <&apps_smmu 0x60 0>; + dma-coherent; + lanes-per-direction = <2>; qcom,ice = <&ice>; From cc8056a16472d186140d1a66ed5648cee41f4379 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Wed, 8 Oct 2025 10:08:55 +0530 Subject: [PATCH 058/138] arm64: dts: qcom: sm8750-mtp: move PCIe GPIOs to pcieport0 node Relocate the wake-gpios and perst-gpios properties from the pcie0 controller node to the pcieport0 node. These GPIOs are associated with the PCIe root port and should reside under the pcieport0 node. Also rename perst-gpios to reset-gpios to match the expected property name in the PCIe port node. Fixes: 141714e163bb ("arm64: dts: qcom: sm8750-mtp: Add WiFi and Bluetooth") Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Krzysztof Kozlowski Tested-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251008-sm8750-v1-1-daeadfcae980@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts index 3bbb53b7c71f..45b5f7581567 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts @@ -960,9 +960,6 @@ &pon_resin { }; &pcie0 { - wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>; - perst-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -977,6 +974,9 @@ &pcie0_phy { }; &pcieport0 { + wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; From bfc5cabaa4979f6645c851759b4242f9efe4f106 Mon Sep 17 00:00:00 2001 From: Jingzhou Zhu Date: Wed, 8 Oct 2025 21:00:51 +0800 Subject: [PATCH 059/138] dt-bindings: arm: qcom: Document Huawei MateBook E 2019 Add compatible for the sdm850-based tablet Huawei MateBook E 2019 using its codename "planck". Acked-by: Krzysztof Kozlowski Signed-off-by: Jingzhou Zhu Link: https://lore.kernel.org/r/20251008130052.11427-2-newwheatzjz@zohomail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 850bd9180bab..ae2fab820c79 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -894,6 +894,7 @@ properties: - items: - enum: + - huawei,planck - lenovo,yoga-c630 - lg,judyln - lg,judyp From aab69794b55d7f60d94305961be264cd230112ba Mon Sep 17 00:00:00 2001 From: Jingzhou Zhu Date: Wed, 8 Oct 2025 21:00:52 +0800 Subject: [PATCH 060/138] arm64: dts: qcom: Add support for Huawei MateBook E 2019 Add device tree for Huawei MateBook E 2019, which is a 2-in-1 tablet based on Qualcomm's sdm850 platform. Supported features: - ADSP, CDSP and SLPI - Volume Key - Power Key - Tablet Mode Switching - Display - Touchscreen - Stylus - WiFi [1] - Bluetooth [2] - GPU - USB - Keyboard - Touchpad - UFS - SD Card - Audio (right internal mic and headphone mic not working) - Mobile Network [1] WiFi probing log: ath10k_snoc 18800000.wifi: Adding to iommu group 12 ath10k_snoc 18800000.wifi: qmi chip_id 0x30214 chip_family 0x4001 board_id 0xff soc_id 0x40030001 ath10k_snoc 18800000.wifi: qmi fw_version 0x2009856b fw_build_timestamp 2018-07-19 12:28 fw_build_id QC_IMAGE_VERSION_STRING=WLAN.HL.2.0-01387-QCAHLSWMTPLZ-1 ath10k_snoc 18800000.wifi: wcn3990 hw1.0 target 0x00000008 chip_id 0x00000000 sub 0000:0000 ath10k_snoc 18800000.wifi: kconfig debug 1 debugfs 1 tracing 1 dfs 0 testmode 0 ath10k_snoc 18800000.wifi: firmware ver api 5 features wowlan,mgmt-tx-by-reference,non-bmi crc32 b3d4b790 ath10k_snoc 18800000.wifi: htt-ver 3.53 wmi-op 4 htt-op 3 cal file max-sta 32 raw 0 hwcrypto 1 ath10k_snoc 18800000.wifi: invalid MAC address; choosing random [2] Bluetooth probing log: Bluetooth: hci0: setting up wcn399x Bluetooth: hci0: QCA Product ID :0x0000000a Bluetooth: hci0: QCA SOC Version :0x40010214 Bluetooth: hci0: QCA ROM Version :0x00000201 Bluetooth: hci0: QCA Patch Version:0x00000001 Bluetooth: hci0: QCA controller version 0x02140201 Bluetooth: hci0: QCA Downloading qca/crbtfw21.tlv Bluetooth: hci0: QCA Downloading qca/crnv21.bin Bluetooth: hci0: QCA setup on UART is completed Features not supported yet: - Panel Backlight - Lid Detection - Battery - EFI Variable Access - Cameras 1. Panel backlight, lid detection and battery will be supported with the EC driver upstreamed. 2. EFI variables can only be read with the QSEECOM driver, and will be enabled when the driver is fixed. 3. Cameras are tested to work with modified downstream driver, and once drivers for these camera modules are included in the tree, cameras can be enabled. Features won't be supported: - External Display - Fingerprint 1. To make external display work, more reverse engineering may be required, but it's beyond my ability. 2. Fingerprint is controlled by TrustZone, meaning direct access to it isn't possible. Reviewed-by: Dmitry Baryshkov Signed-off-by: Jingzhou Zhu Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251008130052.11427-3-newwheatzjz@zohomail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../qcom/sdm850-huawei-matebook-e-2019.dts | 972 ++++++++++++++++++ 2 files changed, 973 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 44391fd19939..7f17ddf00935 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -261,6 +261,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium-ebbg.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium-tianma.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-polaris.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm850-huawei-matebook-e-2019.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb dtb-$(CONFIG_ARCH_QCOM) += sdx75-idp.dtb diff --git a/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts b/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts new file mode 100644 index 000000000000..117cc0133363 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts @@ -0,0 +1,972 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Huawei MateBook E 2019 + * + * Copyright (c) 2025, Jingzhou Zhu + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include +#include "sdm850.dtsi" +#include "sdm845-wcd9340.dtsi" +#include "pm8998.dtsi" + +/* + * Update following upstream (sdm845.dtsi) reserved + * memory mappings for firmware loading to succeed + * and enable the IPA device. + */ +/delete-node/ &tz_mem; +/delete-node/ &rmtfs_mem; +/delete-node/ &qseecom_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &ipa_gsi_mem; +/delete-node/ &gpu_mem; +/delete-node/ &adsp_mem; +/delete-node/ &wlan_msa_mem; +/delete-node/ &slpi_mem; + +/ { + model = "Huawei MateBook E 2019"; + compatible = "huawei,planck", "qcom,sdm845"; + chassis-type = "convertible"; + + aliases { + serial0 = &uart9; + serial1 = &uart6; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&volume_up_gpio &mode_pin_active>; + pinctrl-names = "default"; + + key-vol-up { + label = "Volume up"; + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + wakeup-source; + }; + + switch-mode { + label = "Tablet mode switch"; + gpios = <&tlmm 79 GPIO_ACTIVE_HIGH>; + linux,input-type = ; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&cam_indicator_en>; + pinctrl-names = "default"; + + led: led-camera-indicator { + label = "white:camera-indicator"; + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + /* Reuse as a panic indicator until we get a "camera on" trigger */ + panic-indicator; + }; + }; + + sw_edp_1p2: regulator-edp-1p2 { + compatible = "regulator-fixed"; + regulator-name = "sw_edp_1p2"; + + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + pinctrl-0 = <&sw_edp_1p2_en>; + pinctrl-names = "default"; + + gpio = <&pm8998_gpios 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vreg_l2a_1p2>; + }; + + vlcm_3v3: regulator-vlcm-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vlcm_3v3"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 88 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vph_pwr>; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + }; + + reserved-memory { + cont_splash_mem: framebuffer@80100000 { + reg = <0 0x80100000 0 0xd00000>; + no-map; + }; + + tz_mem: tz@86d00000 { + reg = <0 0x86d00000 0 0x4600000>; + no-map; + }; + + qseecom_mem: qseecom@8b500000 { + reg = <0 0x8b500000 0 0xa00000>; + no-map; + }; + + wlan_msa_mem: wlan-msa@8c400000 { + reg = <0 0x8c400000 0 0x100000>; + no-map; + }; + + adsp_mem: adsp@8c500000 { + reg = <0 0x8c500000 0 0x1a00000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@8df00000 { + reg = <0 0x8df00000 0 0x100000>; + no-map; + }; + + slpi_mem: slpi@96700000 { + reg = <0 0x96700000 0 0x1200000>; + }; + + gpu_mem: gpu@97900000 { + reg = <0 0x97900000 0 0x5000>; + no-map; + }; + + rmtfs_mem: rmtfs@97c00000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0x97c00000 0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = ; + + }; + }; + + sn65dsi86_refclk: sn65dsi86-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + + clock-frequency = <19200000>; + }; +}; + +&adsp_pas { + firmware-name = "qcom/sdm850/HUAWEI/AL09/qcadsp850.mbn"; + + status = "okay"; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8998-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + vdd-s13-supply = <&vph_pwr>; + vdd-l1-l27-supply = <&vreg_s7a_1p025>; + vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>; + vdd-l3-l11-supply = <&vreg_s7a_1p025>; + vdd-l4-l5-supply = <&vreg_s7a_1p025>; + vdd-l6-supply = <&vph_pwr>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; + vdd-l26-supply = <&vreg_s3a_1p35>; + vin-lvs-1-2-supply = <&vreg_s4a_1p8>; + + vreg_s2a_1p125: smps2 { + }; + + vreg_s3a_1p35: smps3 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = ; + }; + + vreg_s4a_1p8: smps4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_s5a_2p04: smps5 { + regulator-min-microvolt = <2040000>; + regulator-max-microvolt = <2040000>; + regulator-initial-mode = ; + }; + + vreg_s6a_0p8: smps6 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vreg_s7a_1p025: smps7 { + regulator-min-microvolt = <1028000>; + regulator-max-microvolt = <1028000>; + regulator-initial-mode = ; + }; + + vdd_qusb_hs0: + vdda_hp_pcie_core: + vdda_mipi_csi0_0p9: + vdda_mipi_csi1_0p9: + vdda_mipi_csi2_0p9: + vdda_mipi_dsi0_pll: + vdda_mipi_dsi1_pll: + vdda_qlink_lv: + vdda_qlink_lv_ck: + vdda_qrefs_0p875: + vdda_pcie_core: + vdda_pll_cc_ebi01: + vdda_pll_cc_ebi23: + vdda_sp_sensor: + vdda_ufs1_core: + vdda_ufs2_core: + vdda_usb1_ss_core: + vdda_usb2_ss_core: + vreg_l1a_0p875: ldo1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vddpx_10: + vreg_l2a_1p2: ldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l3a_1p0: ldo3 { + }; + + vdd_wcss_cx: + vdd_wcss_mx: + vdda_wcss_pll: + vreg_l5a_0p8: ldo5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vddpx_13: + vreg_l6a_1p8: ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l8a_1p2: ldo8 { + }; + + vreg_l9a_1p8: ldo9 { + }; + + vreg_l10a_1p8: ldo10 { + }; + + vreg_l11a_1p0: ldo11 { + }; + + vdd_qfprom: + vdd_qfprom_sp: + vdda_apc1_cs_1p8: + vdda_gfx_cs_1p8: + vdda_qrefs_1p8: + vdda_qusb_hs0_1p8: + vddpx_11: + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vddpx_2: + vreg_l13a_2p95: ldo13 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l14a_1p88: ldo14 { + regulator-min-microvolt = <1880000>; + regulator-max-microvolt = <1880000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l15a_1p8: ldo15 { + }; + + vreg_l16a_2p7: ldo16 { + }; + + vreg_l17a_1p3: ldo17 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l18a_2p7: ldo18 { + }; + + vreg_l19a_3p0: ldo19 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l20a_2p95: ldo20 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l21a_2p95: ldo21 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l22a_2p85: ldo22 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + + regulator-always-on; + }; + + vreg_l23a_3p3: ldo23 { + }; + + vdda_qusb_hs0_3p1: + vreg_l24a_3p075: ldo24 { + /* 3075000 uV causes -ENOTRECOVERABLE error */ + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + regulator-initial-mode = ; + }; + + vreg_l25a_3p3: ldo25 { + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + }; + + vdda_hp_pcie_1p2: + vdda_hv_ebi0: + vdda_hv_ebi1: + vdda_hv_ebi2: + vdda_hv_ebi3: + vdda_mipi_csi_1p25: + vdda_mipi_dsi0_1p2: + vdda_mipi_dsi1_1p2: + vdda_pcie_1p2: + vdda_ufs1_1p2: + vdda_ufs2_1p2: + vdda_usb1_ss_1p2: + vdda_usb2_ss_1p2: + vreg_l26a_1p2: ldo26 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l28a_3p0: ldo28 { + /* 3300000 uV causes -ENOTRECOVERABLE error */ + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_lvs1a_1p8: lvs1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_lvs2a_1p8: lvs2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + regulators-1 { + compatible = "qcom,pm8005-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s2c_0p752: smps2 { + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + }; + }; +}; + +&cci_i2c0 { + /* chipnext,cn3927e vcm@0xc */ + /* samsung,s5k3l6 camera@0x10 */ + /* eeprom@0x50 */ +}; + +&cci_i2c1 { + /* galaxycore,gc5025 camera@0x36 */ + /* eeprom@0x50 */ +}; + +&cdsp_pas { + firmware-name = "qcom/sdm850/HUAWEI/AL09/qccdsp850.mbn"; + + status = "okay"; +}; + +&crypto { + /* FIXME: qce_start triggers an SError */ + status = "disabled"; +}; + +&gcc { + protected-clocks = , + , + , + , + ; +}; + +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sdm850/HUAWEI/AL09/qcdxkmsuc850.mbn"; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + touchscreen: hid@5d { + compatible = "hid-over-i2c"; + reg = <0x5d>; + hid-descr-addr = <0x1>; + + interrupts-extended = <&tlmm 125 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&i2c5_hid_active>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c7 { + /* ec@0x76 */ +}; + +&i2c10 { + clock-frequency = <400000>; + + status = "okay"; + + sn65dsi86: bridge@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + + pinctrl-0 = <&sn65dsi86_pin_active>; + pinctrl-names = "default"; + + enable-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + + vcca-supply = <&sw_edp_1p2>; + vcc-supply = <&sw_edp_1p2>; + vpll-supply = <&vreg_l14a_1p88>; + vccio-supply = <&vreg_l14a_1p88>; + + clocks = <&sn65dsi86_refclk>; + clock-names = "refclk"; + + no-hpd; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + sn65dsi86_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + sn65dsi86_out: endpoint { + remote-endpoint = <&panel_in_edp>; + }; + }; + }; + + aux-bus { + panel: panel { + compatible = "innolux,p120zdg-bf1"; + power-supply = <&vlcm_3v3>; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&sn65dsi86_out>; + }; + }; + }; + }; + }; +}; + +&ipa { + qcom,gsi-loader = "self"; + memory-region = <&ipa_fw_mem>; + firmware-name = "qcom/sdm850/HUAWEI/AL09/ipa_fws.elf"; + + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vdda_mipi_dsi0_1p2>; + + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <&sn65dsi86_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vdda_mipi_dsi0_pll>; + + status = "okay"; +}; + +&mss_pil { + firmware-name = "qcom/sdm850/HUAWEI/AL09/qcdsp1v2850.mbn", + "qcom/sdm850/HUAWEI/AL09/qcdsp2850.mbn"; + + status = "okay"; +}; + +&pm8998_gpios { + sw_edp_1p2_en: sw-edp-1p2-en-state { + pins = "gpio9"; + function = "normal"; + bias-disable; + qcom,drive-strength = ; + }; + + volume_up_gpio: volume-up-gpio-state { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,drive-strength = ; + }; +}; + +&pm8998_pwrkey { + status = "okay"; +}; + +&pm8998_resin { + linux,code = ; + + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&q6asmdai { + dai@0 { + reg = ; + }; + + dai@1 { + reg = ; + }; + + dai@2 { + reg = ; + }; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>; + pinctrl-names = "default"; + + vmmc-supply = <&vreg_l21a_2p95>; + vqmmc-supply = <&vddpx_2>; + + bus-width = <4>; + cd-gpios = <&tlmm 126 GPIO_ACTIVE_HIGH>; + + status = "okay"; +}; + +&slpi_pas { + firmware-name = "qcom/sdm850/HUAWEI/AL09/qcslpi850.mbn"; + + status = "okay"; +}; + +&sound { + compatible = "lenovo,yoga-c630-sndcard", "qcom,sdm845-sndcard"; + model = "HUAWEI-PAK_AL09-M1040"; + + audio-routing = "RX_BIAS", "MCLK", + "AMIC2", "MIC BIAS2", + "DMIC0", "MCLK", + "DMIC0", "MIC BIAS1", + "DMIC2", "MCLK", + "DMIC2", "MIC BIAS3", + "SpkrLeft IN", "SPK1 OUT", + "SpkrRight IN", "SPK2 OUT"; + + mm1-dai-link { + link-name = "MultiMedia1"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; + }; + + mm2-dai-link { + link-name = "MultiMedia2"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; + }; + }; + + mm3-dai-link { + link-name = "MultiMedia3"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; + }; + }; + + slim-dai-link { + link-name = "SLIM Playback"; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 AIF1_PB>; + }; + + cpu { + sound-dai = <&q6afedai SLIMBUS_0_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + }; + + slimcap-dai-link { + link-name = "SLIM Capture"; + + codec { + sound-dai = <&wcd9340 AIF1_CAP>; + }; + + cpu { + sound-dai = <&q6afedai SLIMBUS_0_TX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + }; + + slim-wcd-dai-link { + link-name = "SLIM WCD Playback"; + + codec { + sound-dai = <&wcd9340 AIF2_PB>; + }; + + cpu { + sound-dai = <&q6afedai SLIMBUS_1_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + }; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, /* Unused */ + <81 4>; /* SPI (fingerprint reader) */ + + cam_indicator_en: cam-indicator-en-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c5_hid_active: i2c5-hid-active-state { + pins = "gpio125"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + mode_pin_active: mode-pin-state { + pins = "gpio79"; + function = "gpio"; + bias-disable; + }; + + sdc2_default_state: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <16>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + sdc2_card_det_n: sd-card-det-n-state { + pins = "gpio126"; + function = "gpio"; + bias-pull-up; + }; + + sn65dsi86_pin_active: sn65dsi86-enable-state { + pins = "gpio96"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart6 { + pinctrl-0 = <&qup_uart6_4pin>; + pinctrl-names = "default"; + + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3990-bt"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l17a_1p3>; + vddch0-supply = <&vreg_l25a_3p3>; + vddch1-supply = <&vreg_l23a_3p3>; + max-speed = <3200000>; + }; +}; + +&uart9 { + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l20a_2p95>; + vcc-max-microamp = <600000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vdda_ufs1_core>; + vdda-pll-supply = <&vdda_ufs1_1p2>; + + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_hsphy { + vdd-supply = <&vdda_usb1_ss_core>; + vdda-pll-supply = <&vdda_qusb_hs0_1p8>; + vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; + + qcom,imp-res-offset-value = <8>; + qcom,hstx-trim-value = ; + qcom,preemphasis-level = ; + qcom,preemphasis-width = ; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vdda_usb1_ss_1p2>; + vdda-pll-supply = <&vdda_usb1_ss_core>; + + status = "okay"; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + vdd-supply = <&vdda_usb2_ss_core>; + vdda-pll-supply = <&vdda_qusb_hs0_1p8>; + vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; + + qcom,imp-res-offset-value = <8>; + qcom,hstx-trim-value = ; + + status = "okay"; +}; + +&usb_2_qmpphy { + vdda-phy-supply = <&vdda_usb2_ss_1p2>; + vdda-pll-supply = <&vdda_usb2_ss_core>; + + status = "okay"; +}; + +&venus { + firmware-name = "qcom/sdm850/HUAWEI/AL09/qcvss850.mbn"; + + status = "okay"; +}; + +&wcd9340 { + reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; + vdd-buck-supply = <&vreg_s4a_1p8>; + vdd-buck-sido-supply = <&vreg_s4a_1p8>; + vdd-tx-supply = <&vreg_s4a_1p8>; + vdd-rx-supply = <&vreg_s4a_1p8>; + vdd-io-supply = <&vreg_s4a_1p8>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 + 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <2700000>; + qcom,micbias3-microvolt = <1800000>; + + swm: soundwire@c85 { + left_spkr: speaker@0,3 { + compatible = "sdw10217211000"; + reg = <0 3>; + powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_LOW>; + #thermal-sensor-cells = <0>; + sound-name-prefix = "SpkrLeft"; + #sound-dai-cells = <0>; + }; + + right_spkr: speaker@0,4 { + compatible = "sdw10217211000"; + reg = <0 4>; + powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_LOW>; + #thermal-sensor-cells = <0>; + sound-name-prefix = "SpkrRight"; + #sound-dai-cells = <0>; + }; + }; +}; + +&wifi { + vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; + vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; + + qcom,snoc-host-cap-8bit-quirk; + qcom,calibration-variant = "Huawei_Planck"; + + status = "okay"; +}; From bc42d98593535ccca739f67d9b9cb859f4e13304 Mon Sep 17 00:00:00 2001 From: Erikas Bitovtas Date: Wed, 8 Oct 2025 21:20:19 +0300 Subject: [PATCH 061/138] dt-bindings: arm: qcom: Add Asus ZenFone 2 Laser/Selfie Add a compatible for Asus ZenFone 2 Laser/Selfie (1080p) Signed-off-by: Erikas Bitovtas Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20251008182106.217340-2-xerikasxx@gmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index ae2fab820c79..df3dd0798a7d 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -88,6 +88,7 @@ properties: - items: - enum: + - asus,z00t - huawei,kiwi - longcheer,l9100 - samsung,a7 From 42621cbb3afd47e1e3000abe2da8ac33286fff4f Mon Sep 17 00:00:00 2001 From: Erikas Bitovtas Date: Wed, 8 Oct 2025 21:20:20 +0300 Subject: [PATCH 062/138] arm64: dts: qcom: msm8939-asus-z00t: add initial device tree Add an initial device tree for Asus ZenFone 2 Laser/Selfie. This includes support for: - UART - USB - Internal storage - MicroSD - Volume keys - Touchscreen: Focaltech FT5306 - Accelerometer: Invensense MPU6515 - Magnetometer: Asahi Kasei AK09911 - Vibrator - Audio input and output - Modem Signed-off-by: Erikas Bitovtas Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251008182106.217340-3-xerikasxx@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../arm64/boot/dts/qcom/msm8939-asus-z00t.dts | 256 ++++++++++++++++++ 2 files changed, 257 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 7f17ddf00935..4fe7e1843b1a 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -74,6 +74,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-yiming-uz801v3.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8917-xiaomi-riva.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8929-wingtech-wt82918hd.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8939-asus-z00t.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8939-huawei-kiwi.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8939-longcheer-l9100.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8939-samsung-a7.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts b/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts new file mode 100644 index 000000000000..ebb548e62e02 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts @@ -0,0 +1,256 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8939-pm8916.dtsi" +#include "msm8916-modem-qdsp6.dtsi" + +#include +#include +#include + +/ { + model = "Asus ZenFone 2 Laser/Selfie (1080p)"; + compatible = "asus,z00t", "qcom,msm8939"; + chassis-type = "handset"; + + aliases { + mmc0 = &sdhc_1; + mmc1 = &sdhc_2; + serial0 = &blsp_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + button-volume-up { + label = "Volume Up"; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + + button-volume-down { + label = "Volume Down"; + gpios = <&tlmm 117 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + }; + + reg_sd_vmmc: regulator-sdcard-vmmc { + compatible = "regulator-fixed"; + regulator-name = "sdcard-vmmc"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>; + enable-active-high; + + startup-delay-us = <200>; + + pinctrl-0 = <&sd_vmmc_en_default>; + pinctrl-names = "default"; + }; + + usb_id: usb-id { + compatible = "linux,extcon-usb-gpio"; + id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&usb_id_default>; + pinctrl-names = "default"; + }; +}; + +&blsp_i2c2 { + status = "okay"; + + magnetometer@c { + compatible = "asahi-kasei,ak09911"; + reg = <0x0c>; + + vdd-supply = <&pm8916_l8>; + vid-supply = <&pm8916_l6>; + + reset-gpios = <&tlmm 112 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&mag_reset_default>; + pinctrl-names = "default"; + }; + + imu@68 { + compatible = "invensense,mpu6515"; + reg = <0x68>; + + interrupts-extended = <&tlmm 36 IRQ_TYPE_EDGE_RISING>; + + vdd-supply = <&pm8916_l8>; + vddio-supply = <&pm8916_l6>; + + pinctrl-0 = <&imu_default>; + pinctrl-names = "default"; + + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; + }; +}; + +&blsp_i2c5 { + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5306"; + reg = <0x38>; + + interrupts-extended = <&tlmm 13 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>; + + vcc-supply = <&pm8916_l8>; + iovcc-supply = <&pm8916_l6>; + + touchscreen-size-x = <1080>; + touchscreen-size-y = <1920>; + + pinctrl-0 = <&touchscreen_default>; + pinctrl-names = "default"; + }; +}; + +&blsp_uart2 { + pinctrl-0 = <&blsp_uart2_console_default>; + pinctrl-1 = <&blsp_uart2_console_sleep>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&mpss_mem { + reg = <0x0 0x86800000 0x0 0x5500000>; +}; + +&pm8916_codec { + qcom,micbias-lvl = <2800>; + qcom,mbhc-vthreshold-low = <75 150 237 450 500>; + qcom,mbhc-vthreshold-high = <75 150 237 450 500>; + qcom,micbias1-ext-cap; + qcom,hphl-jack-type-normally-open; + + status = "okay"; +}; + +&pm8916_vib { + status = "okay"; +}; + +&sdhc_1 { + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <®_sd_vmmc>; + + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; + pinctrl-names = "default", "sleep"; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&sound { + audio-routing = + "AMIC1", "MIC BIAS External1", + "AMIC2", "MIC BIAS Internal2", + "AMIC3", "MIC BIAS External1"; + + status = "okay"; +}; + +&usb { + extcon = <&usb_id>, <&usb_id>; + + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&usb_id>; +}; + +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3660b"; +}; + +&wcnss_mem { + status = "okay"; +}; + +&tlmm { + touchscreen_default: touchscreen-default-state { + reset-pins { + pins = "gpio12"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + touch-pins { + pins = "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + imu_default: imu-default-state { + pins = "gpio36"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + sd_vmmc_en_default: sd-vmmc-en-default-state { + pins = "gpio87"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + gpio_keys_default: gpio-keys-default-state { + pins = "gpio107", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + usb_id_default: usb-id-default-state { + pins = "gpio110"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + mag_reset_default: mag-reset-default-state { + pins = "gpio112"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; From 03eb18495d2d91214e840064641eade208fcd8c7 Mon Sep 17 00:00:00 2001 From: Alexander Martinz Date: Thu, 9 Oct 2025 11:06:31 +0200 Subject: [PATCH 063/138] arm64: dts: qcom: qcm6490-shift-otter: Fix sorting and indentation Make sure the nodes are sorted correctly, and the indentation is correct. Signed-off-by: Alexander Martinz Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251009-otter-further-bringup-v2-1-5bb2f4a02cea@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts index 6be2ebb2958f..740ade0655fc 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts @@ -862,7 +862,7 @@ &uart5 { &uart7 { /delete-property/interrupts; interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>, - <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; + <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>, <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>; pinctrl-names = "default", "sleep"; @@ -925,10 +925,6 @@ &usb_1_dwc3_hs { remote-endpoint = <&pmic_glink_hs_in>; }; -&usb_dp_qmpphy_out { - remote-endpoint = <&pmic_glink_ss_in>; -}; - &usb_1_hsphy { vdda-pll-supply = <&vreg_l10c>; vdda18-supply = <&vreg_l1c>; @@ -955,6 +951,10 @@ &usb_1_qmpphy { status = "okay"; }; +&usb_dp_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + &wifi { qcom,calibration-variant = "SHIFTphone_8"; From a206ee34db2eff05d3d58214ba2e827824b2bc7b Mon Sep 17 00:00:00 2001 From: Alexander Martinz Date: Thu, 9 Oct 2025 11:06:32 +0200 Subject: [PATCH 064/138] arm64: dts: qcom: qcm6490-shift-otter: Remove thermal zone polling delays As with all other devices in commit 7747a49db7e5 ("arm64: dts: qcom: sc7280-*: Remove thermal zone polling delays"), apply the same change to this device as the delays are assumed to be equal to "0" if not set. Signed-off-by: Alexander Martinz Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251009-otter-further-bringup-v2-2-5bb2f4a02cea@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts index 740ade0655fc..47412d233cc1 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts @@ -130,8 +130,6 @@ rmtfs_mem: rmtfs@f8500000 { thermal-zones { camera-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pmk8350_adc_tm 2>; trips { @@ -144,8 +142,6 @@ active-config0 { }; chg-skin-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm7250b_adc_tm 0>; trips { @@ -158,8 +154,6 @@ active-config0 { }; conn-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm7250b_adc_tm 1>; trips { @@ -172,8 +166,6 @@ active-config0 { }; quiet-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pmk8350_adc_tm 1>; trips { @@ -186,8 +178,6 @@ active-config0 { }; rear-cam-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pmk8350_adc_tm 4>; trips { @@ -200,8 +190,6 @@ active-config0 { }; sdm-skin-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pmk8350_adc_tm 3>; trips { @@ -214,8 +202,6 @@ active-config0 { }; xo-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pmk8350_adc_tm 0>; trips { From f404fdcb50021fdad6bc734d69468cc777901a80 Mon Sep 17 00:00:00 2001 From: Alexander Martinz Date: Thu, 9 Oct 2025 11:06:33 +0200 Subject: [PATCH 065/138] arm64: dts: qcom: qcm6490-shift-otter: Add missing reserved-memory It seems we also need to reserve a region of 81 MiB called "removed_mem" otherwise we can easily hit memory errors with higher RAM usage. Fixes: 249666e34c24 ("arm64: dts: qcom: add QCM6490 SHIFTphone 8") Signed-off-by: Alexander Martinz Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251009-otter-further-bringup-v2-3-5bb2f4a02cea@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts index 47412d233cc1..0ae6acbd60f5 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts @@ -118,6 +118,11 @@ cdsp_mem: cdsp@88f00000 { no-map; }; + removed_mem: removed@c0000000 { + reg = <0x0 0xc0000000 0x0 0x5100000>; + no-map; + }; + rmtfs_mem: rmtfs@f8500000 { compatible = "qcom,rmtfs-mem"; reg = <0x0 0xf8500000 0x0 0x600000>; From 2fd302ea31af00eff7d8e2c9fb13209ea6959195 Mon Sep 17 00:00:00 2001 From: Casey Connolly Date: Thu, 9 Oct 2025 11:06:34 +0200 Subject: [PATCH 066/138] arm64: dts: qcom: qcm6490-shift-otter: Enable flash LED Describe the flash LED on this phone. Signed-off-by: Casey Connolly Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Reviewed-by: Pavel Machek Link: https://lore.kernel.org/r/20251009-otter-further-bringup-v2-4-5bb2f4a02cea@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts index 0ae6acbd60f5..c23dc166d561 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts @@ -610,6 +610,19 @@ volume_down_default: volume-down-default-state { }; }; +&pm8350c_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <1>, <2>; + led-max-microamp = <500000>; + flash-max-microamp = <1500000>; + flash-max-timeout-us = <1280000>; + }; +}; + &pmk8350_adc_tm { status = "okay"; From 66e74839662d06ddd11b310a8465b91802030531 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 9 Oct 2025 11:06:35 +0200 Subject: [PATCH 067/138] arm64: dts: qcom: qcm6490-shift-otter: Enable RGB LED Enable the RGB LED connected to the PM7350C (PM8350C). Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Reviewed-by: Pavel Machek Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251009-otter-further-bringup-v2-5-5bb2f4a02cea@fairphone.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/qcm6490-shift-otter.dts | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts index c23dc166d561..9fcc96fcb60f 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts @@ -623,6 +623,33 @@ led-0 { }; }; +&pm8350c_pwm { + status = "okay"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + + led@3 { + reg = <3>; + color = ; + }; + }; +}; + &pmk8350_adc_tm { status = "okay"; From 6e66efe16bde9c498789d8156da3aeb0b24e9c90 Mon Sep 17 00:00:00 2001 From: Alexander Martinz Date: Thu, 9 Oct 2025 11:06:36 +0200 Subject: [PATCH 068/138] arm64: dts: qcom: qcm6490-shift-otter: Enable venus node Enable the venus node so that the video encoder/decoder will start working. Signed-off-by: Alexander Martinz Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251009-otter-further-bringup-v2-6-5bb2f4a02cea@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts index 9fcc96fcb60f..7a6208bdd645 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts @@ -986,6 +986,12 @@ &usb_dp_qmpphy_out { remote-endpoint = <&pmic_glink_ss_in>; }; +&venus { + firmware-name = "qcom/qcm6490/SHIFT/otter/venus.mbn"; + + status = "okay"; +}; + &wifi { qcom,calibration-variant = "SHIFTphone_8"; From cdf9756037d74dee865570e808e4bded7402c662 Mon Sep 17 00:00:00 2001 From: Wojciech Slenska Date: Thu, 9 Oct 2025 11:07:17 +0200 Subject: [PATCH 069/138] arm64: dts: qcom: qcm2290: Fix uart3 QUP interconnect The config_noc interconnect should use SLAVE_QUP_0. Signed-off-by: Wojciech Slenska Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251009090718.32503-1-wojciech.slenska@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 08141b41de24..746c49d6e0fd 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -1302,7 +1302,7 @@ uart3: serial@4a8c000 { interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG - &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; From 89e4902ac7262f368dfb03afd76d71e6bbb4424d Mon Sep 17 00:00:00 2001 From: Wojciech Slenska Date: Thu, 9 Oct 2025 11:08:58 +0200 Subject: [PATCH 070/138] arm64: dts: qcom: qcm2290: Add uart1 and uart5 nodes Add nodes to support uart1 and uart5. Signed-off-by: Wojciech Slenska Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251009090858.32911-1-wojciech.slenska@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 48 +++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 746c49d6e0fd..ffb194be7b01 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -552,6 +552,13 @@ qup_uart0_default: qup-uart0-default-state { bias-disable; }; + qup_uart1_default: qup-uart1-default-state { + pins = "gpio4", "gpio5", "gpio69", "gpio70"; + function = "qup1"; + drive-strength = <2>; + bias-disable; + }; + qup_uart3_default: qup-uart3-default-state { pins = "gpio8", "gpio9", "gpio10", "gpio11"; function = "qup3"; @@ -566,6 +573,13 @@ qup_uart4_default: qup-uart4-default-state { bias-disable; }; + qup_uart5_default: qup-uart5-default-state { + pins = "gpio14", "gpio15", "gpio16", "gpio17"; + function = "qup5"; + drive-strength = <2>; + bias-disable; + }; + cci0_default: cci0-default-state { pins = "gpio22", "gpio23"; function = "cci_i2c"; @@ -1197,6 +1211,23 @@ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, status = "disabled"; }; + uart1: serial@4a84000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a84000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart1_default>; + pinctrl-names = "default"; + interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + status = "disabled"; + }; + i2c2: i2c@4a88000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x04a88000 0x0 0x4000>; @@ -1418,6 +1449,23 @@ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, #size-cells = <0>; status = "disabled"; }; + + uart5: serial@4a94000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a94000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart5_default>; + pinctrl-names = "default"; + interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + status = "disabled"; + }; }; usb: usb@4ef8800 { From 752c3765a952bab9b20d4fbe75ef855dff546c46 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 9 Oct 2025 14:59:18 +0200 Subject: [PATCH 071/138] arm64: dts: qcom: x1e80100: Describe the full 'link' region of DP hosts The regions are larger than currently described. Rather inconveniently, some control registers, including some related to USB4, are in that left-out chunk. Extend it to cover the entire region, as per the hw specification. Fixes: 1940c25eaa63 ("arm64: dts: qcom: x1e80100: Add display nodes") Signed-off-by: Konrad Dybcio Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20251009-topic-hamoa_dp_reg-v1-1-4c70afa5f029@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 087465f028f5..b4f640c421e2 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -5487,7 +5487,7 @@ mdss_dp0: displayport-controller@ae90000 { compatible = "qcom,x1e80100-dp"; reg = <0 0x0ae90000 0 0x200>, <0 0x0ae90200 0 0x200>, - <0 0x0ae90400 0 0x600>, + <0 0x0ae90400 0 0xc00>, <0 0x0ae91000 0 0x400>, <0 0x0ae91400 0 0x400>; @@ -5575,7 +5575,7 @@ mdss_dp1: displayport-controller@ae98000 { compatible = "qcom,x1e80100-dp"; reg = <0 0x0ae98000 0 0x200>, <0 0x0ae98200 0 0x200>, - <0 0x0ae98400 0 0x600>, + <0 0x0ae98400 0 0xc00>, <0 0x0ae99000 0 0x400>, <0 0x0ae99400 0 0x400>; @@ -5663,7 +5663,7 @@ mdss_dp2: displayport-controller@ae9a000 { compatible = "qcom,x1e80100-dp"; reg = <0 0x0ae9a000 0 0x200>, <0 0x0ae9a200 0 0x200>, - <0 0x0ae9a400 0 0x600>, + <0 0x0ae9a400 0 0xc00>, <0 0x0ae9b000 0 0x400>, <0 0x0ae9b400 0 0x400>; @@ -5750,7 +5750,7 @@ mdss_dp3: displayport-controller@aea0000 { compatible = "qcom,x1e80100-dp"; reg = <0 0x0aea0000 0 0x200>, <0 0x0aea0200 0 0x200>, - <0 0x0aea0400 0 0x600>, + <0 0x0aea0400 0 0xc00>, <0 0x0aea1000 0 0x400>, <0 0x0aea1400 0 0x400>; From 210d525d9c4c321a74828e0e626df2598cc7ed97 Mon Sep 17 00:00:00 2001 From: Le Qi Date: Fri, 10 Oct 2025 11:37:28 +0800 Subject: [PATCH 072/138] arm64: dts: qcom: hamoa-iot-evk: Fix 4-speaker playback support On the HAMOA-IOT-EVK board only 2 out of 4 speakers were functional. Unlike the CRD, which shares a single GPIO reset line for WSA1/2, this board provides a dedicated GPIO reset for each WSA, resulting in 4 separate reset lines. Update the device tree accordingly so that all 4 speakers can playback audio as expected. Signed-off-by: Le Qi Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251010033728.1808133-1-le.qi@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 38 +++++++++++++++++----- 1 file changed, 29 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts index df8d6e5c1f45..36dd6599402b 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -743,20 +743,32 @@ retimer_ss1_con_sbu_out: endpoint { }; &lpass_tlmm { - spkr_01_sd_n_active: spkr-01-sd-n-active-state { + spkr_0_sd_n_active: spkr-0-sd-n-active-state { pins = "gpio12"; function = "gpio"; drive-strength = <16>; bias-disable; - output-low; }; - spkr_23_sd_n_active: spkr-23-sd-n-active-state { + spkr_1_sd_n_active: spkr-1-sd-n-active-state { pins = "gpio13"; function = "gpio"; drive-strength = <16>; bias-disable; - output-low; + }; + + spkr_2_sd_n_active: spkr-2-sd-n-active-state { + pins = "gpio17"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + spkr_3_sd_n_active: spkr-3-sd-n-active-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <16>; + bias-disable; }; }; @@ -908,12 +920,14 @@ &smb2360_2_eusb2_repeater { &swr0 { status = "okay"; - pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-0 = <&wsa_swr_active>; pinctrl-names = "default"; /* WSA8845, Left Woofer */ left_woofer: speaker@0,0 { compatible = "sdw20217020400"; + pinctrl-0 = <&spkr_0_sd_n_active>; + pinctrl-names = "default"; reg = <0 0>; reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; #sound-dai-cells = <0>; @@ -926,8 +940,10 @@ left_woofer: speaker@0,0 { /* WSA8845, Left Tweeter */ left_tweeter: speaker@0,1 { compatible = "sdw20217020400"; + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-names = "default"; reg = <0 1>; - reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; #sound-dai-cells = <0>; sound-name-prefix = "TweeterLeft"; vdd-1p8-supply = <&vreg_l15b_1p8>; @@ -961,14 +977,16 @@ wcd_tx: codec@0,3 { &swr3 { status = "okay"; - pinctrl-0 = <&wsa2_swr_active>, <&spkr_23_sd_n_active>; + pinctrl-0 = <&wsa2_swr_active>; pinctrl-names = "default"; /* WSA8845, Right Woofer */ right_woofer: speaker@0,0 { compatible = "sdw20217020400"; + pinctrl-0 = <&spkr_2_sd_n_active>; + pinctrl-names = "default"; reg = <0 0>; - reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + reset-gpios = <&lpass_tlmm 17 GPIO_ACTIVE_LOW>; #sound-dai-cells = <0>; sound-name-prefix = "WooferRight"; vdd-1p8-supply = <&vreg_l15b_1p8>; @@ -979,8 +997,10 @@ right_woofer: speaker@0,0 { /* WSA8845, Right Tweeter */ right_tweeter: speaker@0,1 { compatible = "sdw20217020400"; + pinctrl-0 = <&spkr_3_sd_n_active>; + pinctrl-names = "default"; reg = <0 1>; - reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + reset-gpios = <&lpass_tlmm 18 GPIO_ACTIVE_LOW>; #sound-dai-cells = <0>; sound-name-prefix = "TweeterRight"; vdd-1p8-supply = <&vreg_l15b_1p8>; From 5b5014f667ddbc590fe2cd3ab5a5d042e01c0e2f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 Oct 2025 22:02:18 +0200 Subject: [PATCH 073/138] arm64: dts: qcom: x1e80100: Move CPU idle states to their respective PSCI PDs To make things uniform with other Qualcomm platforms, move the CPU idle states under their PSCI power domains. No functional change. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251010-topic-x1e_dt_idle-v1-1-b1c8d558e635@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index b4f640c421e2..5f6f04857cc6 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -75,7 +75,6 @@ cpu0: cpu@0 { next-level-cache = <&l2_0>; power-domains = <&cpu_pd0>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; - cpu-idle-states = <&cluster_c4>; l2_0: l2-cache { compatible = "cache"; @@ -92,7 +91,6 @@ cpu1: cpu@100 { next-level-cache = <&l2_0>; power-domains = <&cpu_pd1>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; - cpu-idle-states = <&cluster_c4>; }; cpu2: cpu@200 { @@ -103,7 +101,6 @@ cpu2: cpu@200 { next-level-cache = <&l2_0>; power-domains = <&cpu_pd2>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; - cpu-idle-states = <&cluster_c4>; }; cpu3: cpu@300 { @@ -114,7 +111,6 @@ cpu3: cpu@300 { next-level-cache = <&l2_0>; power-domains = <&cpu_pd3>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; - cpu-idle-states = <&cluster_c4>; }; cpu4: cpu@10000 { @@ -125,7 +121,6 @@ cpu4: cpu@10000 { next-level-cache = <&l2_1>; power-domains = <&cpu_pd4>, <&scmi_dvfs 1>; power-domain-names = "psci", "perf"; - cpu-idle-states = <&cluster_c4>; l2_1: l2-cache { compatible = "cache"; @@ -142,7 +137,6 @@ cpu5: cpu@10100 { next-level-cache = <&l2_1>; power-domains = <&cpu_pd5>, <&scmi_dvfs 1>; power-domain-names = "psci", "perf"; - cpu-idle-states = <&cluster_c4>; }; cpu6: cpu@10200 { @@ -153,7 +147,6 @@ cpu6: cpu@10200 { next-level-cache = <&l2_1>; power-domains = <&cpu_pd6>, <&scmi_dvfs 1>; power-domain-names = "psci", "perf"; - cpu-idle-states = <&cluster_c4>; }; cpu7: cpu@10300 { @@ -164,7 +157,6 @@ cpu7: cpu@10300 { next-level-cache = <&l2_1>; power-domains = <&cpu_pd7>, <&scmi_dvfs 1>; power-domain-names = "psci", "perf"; - cpu-idle-states = <&cluster_c4>; }; cpu8: cpu@20000 { @@ -175,7 +167,6 @@ cpu8: cpu@20000 { next-level-cache = <&l2_2>; power-domains = <&cpu_pd8>, <&scmi_dvfs 2>; power-domain-names = "psci", "perf"; - cpu-idle-states = <&cluster_c4>; l2_2: l2-cache { compatible = "cache"; @@ -192,7 +183,6 @@ cpu9: cpu@20100 { next-level-cache = <&l2_2>; power-domains = <&cpu_pd9>, <&scmi_dvfs 2>; power-domain-names = "psci", "perf"; - cpu-idle-states = <&cluster_c4>; }; cpu10: cpu@20200 { @@ -203,7 +193,6 @@ cpu10: cpu@20200 { next-level-cache = <&l2_2>; power-domains = <&cpu_pd10>, <&scmi_dvfs 2>; power-domain-names = "psci", "perf"; - cpu-idle-states = <&cluster_c4>; }; cpu11: cpu@20300 { @@ -214,7 +203,6 @@ cpu11: cpu@20300 { next-level-cache = <&l2_2>; power-domains = <&cpu_pd11>, <&scmi_dvfs 2>; power-domain-names = "psci", "perf"; - cpu-idle-states = <&cluster_c4>; }; cpu-map { @@ -371,61 +359,73 @@ psci { cpu_pd0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&cluster_pd0>; + domain-idle-states = <&cluster_c4>; }; cpu_pd1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&cluster_pd0>; + domain-idle-states = <&cluster_c4>; }; cpu_pd2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&cluster_pd0>; + domain-idle-states = <&cluster_c4>; }; cpu_pd3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&cluster_pd0>; + domain-idle-states = <&cluster_c4>; }; cpu_pd4: power-domain-cpu4 { #power-domain-cells = <0>; power-domains = <&cluster_pd1>; + domain-idle-states = <&cluster_c4>; }; cpu_pd5: power-domain-cpu5 { #power-domain-cells = <0>; power-domains = <&cluster_pd1>; + domain-idle-states = <&cluster_c4>; }; cpu_pd6: power-domain-cpu6 { #power-domain-cells = <0>; power-domains = <&cluster_pd1>; + domain-idle-states = <&cluster_c4>; }; cpu_pd7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&cluster_pd1>; + domain-idle-states = <&cluster_c4>; }; cpu_pd8: power-domain-cpu8 { #power-domain-cells = <0>; power-domains = <&cluster_pd2>; + domain-idle-states = <&cluster_c4>; }; cpu_pd9: power-domain-cpu9 { #power-domain-cells = <0>; power-domains = <&cluster_pd2>; + domain-idle-states = <&cluster_c4>; }; cpu_pd10: power-domain-cpu10 { #power-domain-cells = <0>; power-domains = <&cluster_pd2>; + domain-idle-states = <&cluster_c4>; }; cpu_pd11: power-domain-cpu11 { #power-domain-cells = <0>; power-domains = <&cluster_pd2>; + domain-idle-states = <&cluster_c4>; }; cluster_pd0: power-domain-cpu-cluster0 { From 1bdfe3edd4c862f97ac65b60da1db999981fc52a Mon Sep 17 00:00:00 2001 From: Val Packett Date: Sun, 12 Oct 2025 19:40:08 -0300 Subject: [PATCH 074/138] arm64: dts: qcom: x1-dell-thena: Add missing pinctrl for eDP HPD The commit a41d23142d87 ("arm64: dts: qcom: x1e80100-dell-xps13-9345: Add missing pinctrl for eDP HPD") has applied this change to a very similar machine, so apply it here too. This allows us not to rely on the boot firmware to set up the pinctrl for the eDP HPD line of the internal display. Fixes: e7733b42111c ("arm64: dts: qcom: Add support for Dell Inspiron 7441 / Latitude 7455") Reviewed-by: Bryan O'Donoghue Signed-off-by: Val Packett Link: https://lore.kernel.org/r/20251012224706.14311-1-val@packett.cool Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi index 10dc191c193a..b759d0ee169d 100644 --- a/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi @@ -1039,6 +1039,9 @@ &mdss_dp1_out { &mdss_dp3 { /delete-property/ #sound-dai-cells; + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + status = "okay"; aux-bus { From 147d5eefab8f0e17e9951fb5e0c4c77bada34558 Mon Sep 17 00:00:00 2001 From: Val Packett Date: Sun, 12 Oct 2025 19:48:07 -0300 Subject: [PATCH 075/138] arm64: dts: qcom: x1-dell-thena: remove dp data-lanes The commit 458de584248a ("arm64: dts: qcom: x1e80100: move dp0/1/2 data-lanes to SoC dtsi") has landed before this file was added, so the data-lanes lines here remained. Remove them to enable 4-lane DP on the X1E Dell Inspiron/Latitude. Fixes: e7733b42111c ("arm64: dts: qcom: Add support for Dell Inspiron 7441 / Latitude 7455") Reviewed-by: Bryan O'Donoghue Signed-off-by: Val Packett Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251012224909.14988-1-val@packett.cool Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi index b759d0ee169d..bf04a12b16bc 100644 --- a/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi @@ -1023,7 +1023,6 @@ &mdss_dp0 { }; &mdss_dp0_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; @@ -1032,7 +1031,6 @@ &mdss_dp1 { }; &mdss_dp1_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; From 367c2f473f5f5a84cdf633df96e0f9b4a16e443d Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Mon, 13 Oct 2025 16:23:28 +0530 Subject: [PATCH 076/138] arm64: dts: qcom: sm8450: Add opp-level to indicate PCIe data rates The existing OPP table for PCIe is shared across different link configurations such as data rates 8GT/s x2 and 16GT/s x1. These configurations often operate at the same frequency, allowing them to reuse the same OPP entries. However, 8GT/s and 16 GT/s may have different RPMh votes which cannot be represented accurately when sharing a single OPP. To address this, introduce an `opp-level` to indicate the PCIe data rate and uniquely differentiate OPP entries even when the frequency is the same. Although this platform does not currently suffer from this issue, the change is introduced to support unification across platforms. Append the opp level to name of the opp node to indicate both frequency and level. Signed-off-by: Krishna Chaitanya Chundru Acked-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20251013-opp_pcie-v5-1-eb64db2b4bd3@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 55 ++++++++++++++++++++-------- 1 file changed, 40 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 23420e692472..2ae56c39f2e6 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2047,25 +2047,28 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, pcie0_opp_table: opp-table { compatible = "operating-points-v2"; - /* GEN 1 x1 */ + /* 2.5 GT/s x1 */ opp-2500000 { opp-hz = /bits/ 64 <2500000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <250000 1>; + opp-level = <1>; }; - /* GEN 2 x1 */ + /* 5 GT/s x1 */ opp-5000000 { opp-hz = /bits/ 64 <5000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <500000 1>; + opp-level = <2>; }; - /* GEN 3 x1 */ + /* 8 GT/s x1 */ opp-8000000 { opp-hz = /bits/ 64 <8000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <984500 1>; + opp-level = <3>; }; }; @@ -2209,46 +2212,68 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, pcie1_opp_table: opp-table { compatible = "operating-points-v2"; - /* GEN 1 x1 */ - opp-2500000 { + /* 2.5 GT/s x1 */ + opp-2500000-1 { opp-hz = /bits/ 64 <2500000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <250000 1>; + opp-level = <1>; }; - /* GEN 1 x2 and GEN 2 x1 */ - opp-5000000 { + /* 2.5 GT/s x2 */ + opp-5000000-1 { opp-hz = /bits/ 64 <5000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <500000 1>; + opp-level = <1>; }; - /* GEN 2 x2 */ - opp-10000000 { + /* 5 GT/s x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* 5 GT/s x2 */ + opp-10000000-2 { opp-hz = /bits/ 64 <10000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <1000000 1>; + opp-level = <2>; }; - /* GEN 3 x1 */ - opp-8000000 { + /* 8 GT/s x1 */ + opp-8000000-3 { opp-hz = /bits/ 64 <8000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <984500 1>; + opp-level = <3>; }; - /* GEN 3 x2 and GEN 4 x1 */ - opp-16000000 { + /* 8 GT/s x2 */ + opp-16000000-3 { opp-hz = /bits/ 64 <16000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <1969000 1>; + opp-level = <3>; }; - /* GEN 4 x2 */ - opp-32000000 { + /* 16 GT/s x1 */ + opp-16000000-4 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <1969000 1>; + opp-level = <4>; + }; + + /* 16 GT/s x2 */ + opp-32000000-4 { opp-hz = /bits/ 64 <32000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <3938000 1>; + opp-level = <4>; }; }; From fc0ed54869be3a40c92879411b6db553d271de4d Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Mon, 13 Oct 2025 16:23:29 +0530 Subject: [PATCH 077/138] arm64: dts: qcom: sm8550: Add opp-level to indicate PCIe data rates The existing OPP table for PCIe is shared across different link configurations such as data rates 8GT/s x2 and 16GT/s x1. These configurations often operate at the same frequency, allowing them to reuse the same OPP entries. However, 8GT/s and 16 GT/s may have different RPMh votes which cannot be represented accurately when sharing a single OPP. To address this, introduce an `opp-level` to indicate the PCIe data rate and uniquely differentiate OPP entries even when the frequency is the same. Although this platform does not currently suffer from this issue, the change is introduced to support unification across platforms. Append the opp level to name of the opp node to indicate both frequency and level. Signed-off-by: Krishna Chaitanya Chundru Acked-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20251013-opp_pcie-v5-2-eb64db2b4bd3@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 79 ++++++++++++++++++++-------- 1 file changed, 57 insertions(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 7724dba75db7..9e726f848d3a 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2027,39 +2027,52 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, pcie0_opp_table: opp-table { compatible = "operating-points-v2"; - /* GEN 1 x1 */ - opp-2500000 { + /* 2.5 GT/s x1 */ + opp-2500000-1 { opp-hz = /bits/ 64 <2500000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <250000 1>; + opp-level = <1>; }; - /* GEN 1 x2 and GEN 2 x1 */ - opp-5000000 { + /* 2.5 GT/s x2 */ + opp-5000000-1 { opp-hz = /bits/ 64 <5000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <500000 1>; + opp-level = <1>; }; - /* GEN 2 x2 */ - opp-10000000 { + /* 5 GT/s x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* 5 GT/s x2 */ + opp-10000000-2 { opp-hz = /bits/ 64 <10000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <1000000 1>; + opp-level = <2>; }; - /* GEN 3 x1 */ - opp-8000000 { + /* 8 GT/s x1 */ + opp-8000000-3 { opp-hz = /bits/ 64 <8000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <984500 1>; + opp-level = <3>; }; - /* GEN 3 x2 */ - opp-16000000 { + /* 8 GT/s x2 */ + opp-16000000-3 { opp-hz = /bits/ 64 <16000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <1969000 1>; + opp-level = <3>; }; }; @@ -2194,46 +2207,68 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, pcie1_opp_table: opp-table { compatible = "operating-points-v2"; - /* GEN 1 x1 */ - opp-2500000 { + /* 2.5 GT/s x1 */ + opp-2500000-1 { opp-hz = /bits/ 64 <2500000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <250000 1>; + opp-level = <1>; }; - /* GEN 1 x2 and GEN 2 x1 */ - opp-5000000 { + /* 2.5 GT/s x2 */ + opp-5000000-1 { opp-hz = /bits/ 64 <5000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <500000 1>; + opp-level = <1>; }; - /* GEN 2 x2 */ - opp-10000000 { + /* 5 GT/s x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* 5 GT/s x2 */ + opp-10000000-2 { opp-hz = /bits/ 64 <10000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <1000000 1>; + opp-level = <2>; }; - /* GEN 3 x1 */ - opp-8000000 { + /* 8 GT/s x1 */ + opp-8000000-3 { opp-hz = /bits/ 64 <8000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <984500 1>; + opp-level = <3>; }; - /* GEN 3 x2 and GEN 4 x1 */ - opp-16000000 { + /* 8 GT/s x2 */ + opp-16000000-3 { opp-hz = /bits/ 64 <16000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <1969000 1>; + opp-level = <3>; }; - /* GEN 4 x2 */ - opp-32000000 { + /* 16 GT/s x1 */ + opp-16000000-4 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <1969000 1>; + opp-level = <4>; + }; + + /* 16 GT/s x2 */ + opp-32000000-4 { opp-hz = /bits/ 64 <32000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <3938000 1>; + opp-level = <4>; }; }; From 860d514f09f0ccecd233808b44918ac5b2c10627 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Mon, 13 Oct 2025 16:23:30 +0530 Subject: [PATCH 078/138] arm64: dts: qcom: sm8650: Add opp-level to indicate PCIe data rates The existing OPP table for PCIe is shared across different link configurations such as data rates 8GT/s x2 and 16GT/s x1. These configurations often operate at the same frequency, allowing them to reuse the same OPP entries. However, 8GT/s and 16 GT/s may have different RPMh votes which cannot be represented accurately when sharing a single OPP. To address this, introduce an `opp-level` to indicate the PCIe data rate and uniquely differentiate OPP entries even when the frequenc is the same. Although this platform does not currently suffer from this issue, the change is introduced to support unification across platforms. Append the opp level to name of the opp node to indicate both frequency and level. Signed-off-by: Krishna Chaitanya Chundru Acked-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20251013-opp_pcie-v5-3-eb64db2b4bd3@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 79 ++++++++++++++++++++-------- 1 file changed, 57 insertions(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 3b03c1353938..1a323f4ebdd3 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3659,39 +3659,52 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, pcie0_opp_table: opp-table { compatible = "operating-points-v2"; - /* GEN 1 x1 */ - opp-2500000 { + /* 2.5 GT/s x1 */ + opp-2500000-1 { opp-hz = /bits/ 64 <2500000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <250000 1>; + opp-level = <1>; }; - /* GEN 1 x2 and GEN 2 x1 */ - opp-5000000 { + /* 2.5 GT/s x2 */ + opp-5000000-1 { opp-hz = /bits/ 64 <5000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <500000 1>; + opp-level = <1>; }; - /* GEN 2 x2 */ - opp-10000000 { + /* 5 GT/s x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* 5 GT/s x2 */ + opp-10000000-2 { opp-hz = /bits/ 64 <10000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <1000000 1>; + opp-level = <2>; }; - /* GEN 3 x1 */ - opp-8000000 { + /* 8 GT/s x1 */ + opp-8000000-3 { opp-hz = /bits/ 64 <8000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <984500 1>; + opp-level = <3>; }; - /* GEN 3 x2 */ - opp-16000000 { + /* 8 GT/s x2 */ + opp-16000000-3 { opp-hz = /bits/ 64 <16000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <1969000 1>; + opp-level = <3>; }; }; @@ -3839,46 +3852,68 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, pcie1_opp_table: opp-table { compatible = "operating-points-v2"; - /* GEN 1 x1 */ - opp-2500000 { + /* 2.5 GT/s x1 */ + opp-2500000-1 { opp-hz = /bits/ 64 <2500000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <250000 1>; + opp-level = <1>; }; - /* GEN 1 x2 and GEN 2 x1 */ - opp-5000000 { + /* 2.5 GT/s x2 */ + opp-5000000-1 { opp-hz = /bits/ 64 <5000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <500000 1>; + opp-level = <1>; }; - /* GEN 2 x2 */ - opp-10000000 { + /* 5 GT/s x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* 5 GT/s x2 */ + opp-10000000-2 { opp-hz = /bits/ 64 <10000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <1000000 1>; + opp-level = <2>; }; - /* GEN 3 x1 */ - opp-8000000 { + /* 8 GT/s x1 */ + opp-8000000-3 { opp-hz = /bits/ 64 <8000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <984500 1>; + opp-level = <3>; }; - /* GEN 3 x2 and GEN 4 x1 */ - opp-16000000 { + /* 8 GT/s x2 */ + opp-16000000-3 { opp-hz = /bits/ 64 <16000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <1969000 1>; + opp-level = <3>; }; - /* GEN 4 x2 */ - opp-32000000 { + /* 16 GT/s x1 */ + opp-16000000-4 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <1969000 1>; + opp-level = <4>; + }; + + /* 16 GT/s x2 */ + opp-32000000-4 { opp-hz = /bits/ 64 <32000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <3938000 1>; + opp-level = <4>; }; }; From cfd8f45ddf8944fa95ae3e8cb5159c62fef95e34 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Mon, 13 Oct 2025 16:23:31 +0530 Subject: [PATCH 079/138] arm64: dts: qcom: x1e80100: Add opp-level to indicate PCIe data rates The existing OPP table for PCIe is shared across different link configurations such as data rates 8GT/s x2 and 16GT/s x1. These configurations often operate at the same frequency, allowing them to reuse the same OPP entries. However, 8GT/s and 16 GT/s may have different RPMh votes which cannot be represented accurately when sharing a single OPP. To address this, introduce an `opp-level` to indicate the PCIe data rate and uniquely differentiate OPP entries even when the frequenc is the same. Although this platform does not currently suffer from this issue, the change is introduced to support unification across platforms. Append the opp level to name of the opp node to indicate both frequency and level. Signed-off-by: Krishna Chaitanya Chundru Acked-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20251013-opp_pcie-v5-4-eb64db2b4bd3@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 98 +++++++++++++++++++++++------ 1 file changed, 78 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 5f6f04857cc6..a17900eacb20 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -3267,74 +3267,132 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, pcie3_opp_table: opp-table { compatible = "operating-points-v2"; - /* GEN 1 x1 */ - opp-2500000 { + /* 2.5GT/s x1 */ + opp-2500000-1 { opp-hz = /bits/ 64 <2500000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <250000 1>; + opp-level = <1>; }; - /* GEN 1 x2 and GEN 2 x1 */ - opp-5000000 { + /* 2.5 GT/s x2 */ + opp-5000000-1 { opp-hz = /bits/ 64 <5000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <500000 1>; + opp-level = <1>; }; - /* GEN 1 x4 and GEN 2 x2 */ - opp-10000000 { + /* 2.5 GT/s x4 */ + opp-10000000-1 { opp-hz = /bits/ 64 <10000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <1000000 1>; + opp-level = <1>; }; - /* GEN 1 x8 and GEN 2 x4 */ - opp-20000000 { + /* 2.5 GT/s x8 */ + opp-20000000-1 { opp-hz = /bits/ 64 <20000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <2000000 1>; + opp-level = <1>; }; - /* GEN 2 x8 */ - opp-40000000 { + /* 5 GT/s x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* 5 GT/s x2 */ + opp-10000000-2 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + opp-level = <2>; + }; + + /* 5 GT/s x4 */ + opp-20000000-2 { + opp-hz = /bits/ 64 <20000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <2000000 1>; + opp-level = <2>; + }; + + /* 5 GT/s x8 */ + opp-40000000-2 { opp-hz = /bits/ 64 <40000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <4000000 1>; + opp-level = <2>; }; - /* GEN 3 x1 */ - opp-8000000 { + /* 8 GT/s x1 */ + opp-8000000-3 { opp-hz = /bits/ 64 <8000000>; required-opps = <&rpmhpd_opp_svs>; opp-peak-kBps = <984500 1>; + opp-level = <3>; }; - /* GEN 3 x2 and GEN 4 x1 */ - opp-16000000 { + /* 8 GT/s x2 */ + opp-16000000-3 { opp-hz = /bits/ 64 <16000000>; required-opps = <&rpmhpd_opp_svs>; opp-peak-kBps = <1969000 1>; + opp-level = <3>; }; - /* GEN 3 x4 and GEN 4 x2 */ - opp-32000000 { + /* 8 GT/s x4 */ + opp-32000000-3 { opp-hz = /bits/ 64 <32000000>; required-opps = <&rpmhpd_opp_svs>; opp-peak-kBps = <3938000 1>; + opp-level = <3>; }; - /* GEN 3 x8 and GEN 4 x4 */ - opp-64000000 { + /* 8 GT/s x8 */ + opp-64000000-3 { opp-hz = /bits/ 64 <64000000>; required-opps = <&rpmhpd_opp_svs>; opp-peak-kBps = <7876000 1>; + opp-level = <3>; }; - /* GEN 4 x8 */ - opp-128000000 { + /* 16 GT/s x1 */ + opp-16000000-4 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <4>; + }; + + /* 16 GT/s x2 */ + opp-32000000-4 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <3938000 1>; + opp-level = <4>; + }; + + /* 16 GT/s x4 */ + opp-64000000-4 { + opp-hz = /bits/ 64 <64000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <7876000 1>; + opp-level = <4>; + }; + + /* 16 GT/s x8 */ + opp-128000000-4 { opp-hz = /bits/ 64 <128000000>; required-opps = <&rpmhpd_opp_svs>; opp-peak-kBps = <15753000 1>; + opp-level = <4>; }; }; From fb48d3f3abba9a7bca2814fa2e9db8ac5b9e16b9 Mon Sep 17 00:00:00 2001 From: Pengyu Luo Date: Mon, 13 Oct 2025 19:55:05 +0800 Subject: [PATCH 080/138] arm64: dts: qcom: sc8280xp: Fix shifted GPI DMA channels The GPI DMA channels in sc8280xp.dtsi are wrong. Let's fix it. Origianl patch was rebased to the linux-next and formated to a new patch again later, then it got the GPI DMA channels in the new patch shifted. Fixes: 71b12166a2be ("arm64: dts: qcom: sc8280xp: Describe GPI DMA controller nodes") Signed-off-by: Pengyu Luo Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251013115506.103649-1-mitltlatltl@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 170 ++++++++++++------------- 1 file changed, 85 insertions(+), 85 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index e48efbd13bfa..7b89d3d422ea 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -967,8 +967,8 @@ i2c16: i2c@880000 { <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, - <&gpi_dma2 1 6 QCOM_GPI_SPI>; + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -989,8 +989,8 @@ spi16: spi@880000 { <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, - <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1011,8 +1011,8 @@ i2c17: i2c@884000 { <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, - <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1033,8 +1033,8 @@ spi17: spi@884000 { <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, - <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1069,8 +1069,8 @@ i2c18: i2c@888000 { <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, - <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1091,8 +1091,8 @@ spi18: spi@888000 { <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, - <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1131,8 +1131,8 @@ i2c19: i2c@88c000 { <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, - <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1153,8 +1153,8 @@ spi19: spi@88c000 { <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, - <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, + <&gpi_dma2 1 3 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1175,8 +1175,8 @@ i2c20: i2c@890000 { <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, - <&gpi_dma2 1 3 QCOM_GPI_SPI>; + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1197,8 +1197,8 @@ spi20: spi@890000 { <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, - <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, + <&gpi_dma2 1 4 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1241,8 +1241,8 @@ spi21: spi@894000 { <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, - <&gpi_dma2 1 4 QCOM_GPI_SPI>; + dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, + <&gpi_dma2 1 5 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1285,8 +1285,8 @@ spi22: spi@898000 { <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, - <&gpi_dma2 1 5 QCOM_GPI_SPI>; + dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, + <&gpi_dma2 1 6 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1338,7 +1338,7 @@ spi23: spi@89c000 { }; }; - gpi_dma0: dma-controller@900000 { + gpi_dma0: dma-controller@900000 { compatible = "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0 0x00900000 0 0x60000>; @@ -1393,8 +1393,8 @@ i2c0: i2c@980000 { <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, - <&gpi_dma0 1 7 QCOM_GPI_I2C>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1415,8 +1415,8 @@ spi0: spi@980000 { <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, - <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1437,8 +1437,8 @@ i2c1: i2c@984000 { <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, - <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1459,8 +1459,8 @@ spi1: spi@984000 { <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, - <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1481,8 +1481,8 @@ i2c2: i2c@988000 { <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, - <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1503,8 +1503,8 @@ spi2: spi@988000 { <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, - <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1539,8 +1539,8 @@ i2c3: i2c@98c000 { <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, - <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1561,8 +1561,8 @@ spi3: spi@98c000 { <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, - <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1583,8 +1583,8 @@ i2c4: i2c@990000 { <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, - <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1605,8 +1605,8 @@ spi4: spi@990000 { <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, - <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1627,8 +1627,8 @@ i2c5: i2c@994000 { <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, - <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1649,8 +1649,8 @@ spi5: spi@994000 { <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, - <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1671,8 +1671,8 @@ i2c6: i2c@998000 { <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, - <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1693,8 +1693,8 @@ spi6: spi@998000 { <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, - <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, + <&gpi_dma0 1 6 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1715,8 +1715,8 @@ i2c7: i2c@99c000 { <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, - <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, + <&gpi_dma0 1 7 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1800,8 +1800,8 @@ i2c8: i2c@a80000 { <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, - <&gpi_dma1 1 7 QCOM_GPI_I2C>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1822,8 +1822,8 @@ spi8: spi@a80000 { <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, - <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1844,8 +1844,8 @@ i2c9: i2c@a84000 { <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, - <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1866,8 +1866,8 @@ spi9: spi@a84000 { <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, - <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1888,8 +1888,8 @@ i2c10: i2c@a88000 { <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, - <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1910,8 +1910,8 @@ spi10: spi@a88000 { <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, - <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1932,8 +1932,8 @@ i2c11: i2c@a8c000 { <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, - <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1954,8 +1954,8 @@ spi11: spi@a8c000 { <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, - <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1976,8 +1976,8 @@ i2c12: i2c@a90000 { <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, - <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1998,8 +1998,8 @@ spi12: spi@a90000 { <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, - <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -2020,8 +2020,8 @@ i2c13: i2c@a94000 { <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, - <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -2042,8 +2042,8 @@ spi13: spi@a94000 { <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, - <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -2064,8 +2064,8 @@ i2c14: i2c@a98000 { <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, - <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -2086,8 +2086,8 @@ spi14: spi@a98000 { <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, - <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, + <&gpi_dma1 1 6 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -2108,8 +2108,8 @@ i2c15: i2c@a9c000 { <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, - <&gpi_dma1 1 6 QCOM_GPI_SPI>; + dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, + <&gpi_dma1 1 7 QCOM_GPI_I2C>; dma-names = "tx", "rx"; From 78db965913f70f72a71dd41992dd7885fca6084c Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Tue, 14 Oct 2025 02:54:58 +0300 Subject: [PATCH 081/138] arm64: dts: qcom: sm8550: Add description of MCLK pins Add MCLK pin descriptions for all pins with such supported function on SM8550 SoC. Signed-off-by: Vladimir Zapolskiy Reviewed-by: Konrad Dybcio Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20251013235500.1883847-2-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 144 +++++++++++++++++++++++++++ 1 file changed, 144 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 9e726f848d3a..aa3167d10a41 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -4312,6 +4312,150 @@ tlmm: pinctrl@f100000 { gpio-ranges = <&tlmm 0 0 211>; wakeup-parent = <&pdc>; + cam0_default: cam0-default-state { + mclk-pins { + pins = "gpio100"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + }; + + cam0_sleep: cam0-sleep-state { + mclk-pins { + pins = "gpio100"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cam1_default: cam1-default-state { + mclk-pins { + pins = "gpio101"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + }; + + cam1_sleep: cam1-sleep-state { + mclk-pins { + pins = "gpio101"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cam2_default: cam2-default-state { + mclk-pins { + pins = "gpio102"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + }; + + cam2_sleep: cam2-sleep-state { + mclk-pins { + pins = "gpio102"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cam3_default: cam3-default-state { + mclk-pins { + pins = "gpio103"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + }; + + cam3_sleep: cam3-sleep-state { + mclk-pins { + pins = "gpio103"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cam4_default: cam4-default-state { + mclk-pins { + pins = "gpio104"; + function = "cam_aon_mclk4"; + drive-strength = <2>; + bias-disable; + }; + }; + + cam4_sleep: cam4-sleep-state { + mclk-pins { + pins = "gpio104"; + function = "cam_aon_mclk4"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cam5_default: cam5-default-state { + mclk-pins { + pins = "gpio105"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + }; + + cam5_sleep: cam5-sleep-state { + mclk-pins { + pins = "gpio105"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cam6_default: cam6-default-state { + mclk-pins { + pins = "gpio106"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + }; + + cam6_sleep: cam6-sleep-state { + mclk-pins { + pins = "gpio106"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cam7_default: cam7-default-state { + mclk-pins { + pins = "gpio107"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + }; + + cam7_sleep: cam7-sleep-state { + mclk-pins { + pins = "gpio107"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + }; + cci0_0_default: cci0-0-default-state { sda-pins { pins = "gpio110"; From 3f857377578740f73fbead7f154a56db20e05f82 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Tue, 14 Oct 2025 02:54:59 +0300 Subject: [PATCH 082/138] arm64: dts: qcom: sm8550-qrd: Enable CAMSS and S5K3M5 camera sensor Enable CAMSS IP and Samsung S5K3M5 camera sensor on SM8550-QRD board. Signed-off-by: Vladimir Zapolskiy Reviewed-by: Konrad Dybcio Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20251013235500.1883847-3-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 46 +++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index a3f4200a1145..9af2a4fd02ea 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -716,6 +716,52 @@ vreg_l7n_2p96: ldo7 { }; }; +&camss { + status = "okay"; + + vdda-phy-supply = <&vreg_l1e_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + ports { + port@3 { + csiphy3_ep: endpoint { + clock-lanes = <4>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&cam_tele>; + }; + }; + }; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c0 { + sensor@10 { + compatible = "samsung,s5k3m5"; + reg = <0x10>; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK3_CLK>; + assigned-clock-rates = <24000000>; + reset-gpios = <&tlmm 119 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&cam3_default>; + pinctrl-names = "default"; + afvdd-supply = <&vreg_l7n_2p96>; + avdd-supply = <&vreg_l4m_2p8>; + dovdd-supply = <&vreg_l5n_1p8>; + dvdd-supply = <&vreg_l2m_1p056>; + + port { + cam_tele: endpoint { + link-frequencies = /bits/ 64 <602500000>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&csiphy3_ep>; + }; + }; + }; +}; + &i2c_master_hub_0 { status = "okay"; }; From 08ce5274038ae7ad2b9e90bbcbeabe7548ec425b Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Tue, 14 Oct 2025 02:55:00 +0300 Subject: [PATCH 083/138] arm64: dts: qcom: sm8550-hdk: Add SM8550-HDK Rear Camera Card overlay Lantronix SM8550-HDK board may be equipped with a Rear Camera Card PCB which contains: * Samsung S3K33D time-of-fligt image sensor connected to CSIPHY0 (TOF), * Omnivision OV64B40 image sensor connected to CSIPHY1 (uWide), * Sony IMX766 image sensor connected to CSIPHY2 (Wide), * Samsung S5K3M5 image sensor connected to CSIPHY3 (Tele), * two flash leds. The change adds support of a Samsung S5K3M5 camera image sensor and two flash leds on the external camera card module. Signed-off-by: Vladimir Zapolskiy Reviewed-by: Konrad Dybcio Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20251013235500.1883847-4-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 4 + .../dts/qcom/sm8550-hdk-rear-camera-card.dtso | 91 +++++++++++++++++++ 2 files changed, 95 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8550-hdk-rear-camera-card.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 4fe7e1843b1a..fc1db74f65b0 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -303,6 +303,10 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-samsung-r0q.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx223.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb + +sm8550-hdk-rear-camera-card-dtbs := sm8550-hdk.dtb sm8550-hdk-rear-camera-card.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk-rear-camera-card.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk-rear-camera-card.dtso b/arch/arm64/boot/dts/qcom/sm8550-hdk-rear-camera-card.dtso new file mode 100644 index 000000000000..66bec0fef766 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk-rear-camera-card.dtso @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * SM8550-HDK Rear Camera Card overlay + * + * Copyright (c) 2025, Linaro Limited + */ + +#include +#include +#include + +/dts-v1/; +/plugin/; + +&camss { + status = "okay"; + + vdda-phy-supply = <&vreg_l1e_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@3 { + reg = <3>; + + csiphy3_ep: endpoint { + clock-lanes = <4>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&cam_tele>; + }; + }; + }; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + sensor@10 { + compatible = "samsung,s5k3m5"; + reg = <0x10>; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK3_CLK>; + assigned-clock-rates = <24000000>; + reset-gpios = <&tlmm 119 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&cam3_default>; + pinctrl-names = "default"; + afvdd-supply = <&vreg_l7n_2p96>; + avdd-supply = <&vreg_l4m_2p8>; + dovdd-supply = <&vreg_l5n_1p8>; + dvdd-supply = <&vreg_l2m_1p056>; + + port { + cam_tele: endpoint { + link-frequencies = /bits/ 64 <602500000>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&csiphy3_ep>; + }; + }; + }; +}; + +&pm8550_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <1>, <4>; + led-max-microamp = <500000>; + flash-max-microamp = <2000000>; + flash-max-timeout-us = <1280000>; + function-enumerator = <0>; + }; + + led-1 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <2>, <3>; + led-max-microamp = <500000>; + flash-max-microamp = <2000000>; + flash-max-timeout-us = <1280000>; + function-enumerator = <1>; + }; +}; From a829f6f2e8a727409d2b896bff244d33ef21fe29 Mon Sep 17 00:00:00 2001 From: Dang Huynh Date: Tue, 14 Oct 2025 16:04:24 +0200 Subject: [PATCH 084/138] arm64: dts: qcom: Add initial support for MSM8937 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add initial support for MSM8937 SoC. Signed-off-by: Dang Huynh Reviewed-by: Dmitry Baryshkov Co-developed-by: Barnabás Czémán Reviewed-by: Konrad Dybcio Signed-off-by: Barnabás Czémán Link: https://lore.kernel.org/r/20251014-msm8937-v10-1-b3e8da82e968@mainlining.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8937.dtsi | 2133 +++++++++++++++++++++++++ 1 file changed, 2133 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8937.dtsi diff --git a/arch/arm64/boot/dts/qcom/msm8937.dtsi b/arch/arm64/boot/dts/qcom/msm8937.dtsi new file mode 100644 index 000000000000..b93621080989 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8937.dtsi @@ -0,0 +1,2133 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Dang Huynh + */ + +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0x0>; + device_type = "cpu"; + enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table_c0>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + + l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-unified; + }; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + reg = <0x1>; + device_type = "cpu"; + enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table_c0>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53"; + reg = <0x2>; + device_type = "cpu"; + enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table_c0>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53"; + reg = <0x3>; + device_type = "cpu"; + enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table_c0>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu4: cpu@100 { + compatible = "arm,cortex-a53"; + reg = <0x100>; + device_type = "cpu"; + next-level-cache = <&l2_1>; + enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table_c1>; + #cooling-cells = <2>; + + l2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x100000>; + cache-unified; + }; + }; + + cpu5: cpu@101 { + compatible = "arm,cortex-a53"; + reg = <0x101>; + device_type = "cpu"; + next-level-cache = <&l2_1>; + enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table_c1>; + #cooling-cells = <2>; + }; + + cpu6: cpu@102 { + compatible = "arm,cortex-a53"; + reg = <0x102>; + device_type = "cpu"; + next-level-cache = <&l2_1>; + enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table_c1>; + #cooling-cells = <2>; + }; + + cpu7: cpu@103 { + compatible = "arm,cortex-a53"; + reg = <0x103>; + device_type = "cpu"; + next-level-cache = <&l2_1>; + enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table_c1>; + #cooling-cells = <2>; + }; + + cpu-map { + /* Little Cores */ + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + + /* Big Cores */ + cluster1 { + core0 { + cpu = <&cpu4>; + }; + + core1 { + cpu = <&cpu5>; + }; + + core2 { + cpu = <&cpu6>; + }; + + core3 { + cpu = <&cpu7>; + }; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-msm8937", "qcom,scm"; + clocks = <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names = "core", + "bus", + "iface"; + #reset-cells = <1>; + + qcom,dload-mode = <&tcsr 0x6100>; + }; + }; + + memory@80000000 { + /* We expect the bootloader to fill in the reg */ + reg = <0 0x80000000 0 0>; + device_type = "memory"; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + qseecom_mem: reserved@85b00000 { + reg = <0x0 0x85b00000 0x0 0x800000>; + no-map; + }; + + smem@86300000 { + compatible = "qcom,smem"; + reg = <0x0 0x86300000 0x0 0x100000>; + no-map; + + hwlocks = <&tcsr_mutex 3>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + }; + + reserved@86400000 { + reg = <0x0 0x86400000 0x0 0x400000>; + no-map; + }; + + rmtfs@92100000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0x92100000 0x0 0x180000>; + no-map; + + qcom,client-id = <1>; + }; + + adsp_mem: adsp { + size = <0x0 0x1100000>; + alignment = <0x0 0x100000>; + alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; + no-map; + status = "disabled"; + }; + + mba_mem: mba { + size = <0x0 0x100000>; + alignment = <0x0 0x100000>; + alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; + no-map; + status = "disabled"; + }; + + wcnss_mem: wcnss { + size = <0x0 0x700000>; + alignment = <0x0 0x100000>; + alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; + no-map; + status = "disabled"; + }; + + venus_mem: venus { + size = <0x0 0x400000>; + alignment = <0x0 0x100000>; + alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; + no-map; + status = "disabled"; + }; + }; + + cpu_opp_table_c0: opp-table-c0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-768000000 { + opp-hz = /bits/ 64 <768000000>; + }; + + opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + }; + + opp-998400000 { + opp-hz = /bits/ 64 <998400000>; + }; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + }; + }; + + cpu_opp_table_c1: opp-table-c1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-960000000 { + opp-hz = /bits/ 64 <960000000>; + }; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + }; + + opp-1209600000 { + opp-hz = /bits/ 64 <1209600000>; + }; + + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + }; + + opp-1344000000 { + opp-hz = /bits/ 64 <1344000000>; + }; + + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + }; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + rpm: remoteproc { + compatible = "qcom,msm8937-rpm-proc", "qcom,rpm-proc"; + + smd-edge { + interrupts = ; + qcom,ipc = <&apcs1 8 0>; + qcom,smd-edge = <15>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-msm8937", "qcom,smd-rpm"; + qcom,smd-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8937", "qcom,rpmcc"; + #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; + }; + + rpmpd: power-controller { + compatible = "qcom,msm8937-rpmpd", "qcom,msm8917-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level = ; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level = ; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level = ; + }; + + rpmpd_opp_svs: opp5 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level = ; + }; + + rpmpd_opp_nom: opp7 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp9 { + opp-level = ; + }; + }; + }; + }; + }; + }; + + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + + interrupts = ; + + mboxes = <&apcs1 10>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupts = ; + + mboxes = <&apcs1 14>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-wcnss { + compatible = "qcom,smp2p"; + qcom,smem = <451>, <431>; + + interrupts = ; + + mboxes = <&apcs1 18>; + + qcom,local-pid = <0>; + qcom,remote-pid = <4>; + + wcnss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + + wcnss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smsm { + compatible = "qcom,smsm"; + + #address-cells = <1>; + #size-cells = <0>; + + mboxes = <0>, <&apcs1 13>, <0>, <&apcs1 19>; + + apps_smsm: apps@0 { + reg = <0>; + + #qcom,smem-state-cells = <1>; + }; + + hexagon_smsm: hexagon@1 { + reg = <1>; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + wcnss_smsm: wcnss@6 { + reg = <6>; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + ranges = <0 0 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + + qfprom: qfprom@a4000 { + compatible = "qcom,msm8937-qfprom", "qcom,qfprom"; + reg = <0x000a4000 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + + tsens_base1: base1@1d8 { + reg = <0x1d8 0x1>; + bits = <0 8>; + }; + + tsens_s5_p1: s5-p1@1d9 { + reg = <0x1d9 0x1>; + bits = <0 6>; + }; + + tsens_s5_p2: s5-p2@1d9 { + reg = <0x1d9 0x2>; + bits = <6 6>; + }; + + tsens_s6_p1: s6-p1@1da { + reg = <0x1da 0x2>; + bits = <4 6>; + }; + + tsens_s6_p2: s6-p2@1db { + reg = <0x1db 0x1>; + bits = <2 6>; + }; + + tsens_s7_p1: s7-p1@1dc { + reg = <0x1dc 0x1>; + bits = <0 6>; + }; + + tsens_s7_p2: s7-p2@1dc { + reg = <0x1dc 0x2>; + bits = <6 6>; + }; + + tsens_s8_p1: s8-p1@1dd { + reg = <0x1dd 0x2>; + bits = <4 6>; + }; + + tsens_s8_p2: s8-p2@1de { + reg = <0x1de 0x1>; + bits = <2 6>; + }; + + tsens_base2: base2@1df { + reg = <0x1df 0x1>; + bits = <0 8>; + }; + + tsens_mode: mode@210 { + reg = <0x210 0x1>; + bits = <0 3>; + }; + + tsens_s0_p1: s0-p1@210 { + reg = <0x210 0x2>; + bits = <3 6>; + }; + + tsens_s0_p2: s0-p2@211 { + reg = <0x211 0x1>; + bits = <1 6>; + }; + + tsens_s1_p1: s1-p1@211 { + reg = <0x211 0x2>; + bits = <7 6>; + }; + + tsens_s1_p2: s1-p2@212 { + reg = <0x212 0x2>; + bits = <5 6>; + }; + + tsens_s2_p1: s2-p1@213 { + reg = <0x213 0x2>; + bits = <3 6>; + }; + + tsens_s2_p2: s2-p2@214 { + reg = <0x214 0x1>; + bits = <1 6>; + }; + + tsens_s3_p1: s3-p1@214 { + reg = <0x214 0x2>; + bits = <7 6>; + }; + + tsens_s3_p2: s3-p2@215 { + reg = <0x215 0x2>; + bits = <5 6>; + }; + + tsens_s4_p1: s4-p1@216 { + reg = <0x216 0x2>; + bits = <3 6>; + }; + + tsens_s4_p2: s4-p2@217 { + reg = <0x217 0x1>; + bits = <1 6>; + }; + + tsens_s9_p1: s9-p1@230 { + reg = <0x230 0x1>; + bits = <0 6>; + }; + + tsens_s9_p2: s9-p2@230 { + reg = <0x230 0x2>; + bits = <6 6>; + }; + + tsens_s10_p1: s10-p1@231 { + reg = <0x231 0x2>; + bits = <4 6>; + }; + + tsens_s10_p2: s10-p2@232 { + reg = <0x232 0x1>; + bits = <2 6>; + }; + + gpu_speed_bin: gpu-speed-bin@201b { + reg = <0x201b 0x1>; + bits = <7 1>; + }; + }; + + rpm_msg_ram: sram@60000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x00060000 0x8000>; + }; + + usb_hs_phy: phy@6c000 { + compatible = "qcom,usb-hs-28nm-femtophy"; + reg = <0x0006c000 0x200>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", + "ahb", + "sleep"; + resets = <&gcc GCC_QUSB2_PHY_BCR>, + <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; + reset-names = "phy", + "por"; + status = "disabled"; + }; + + rng@e3000 { + compatible = "qcom,prng"; + reg = <0x000e3000 0x1000>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + + tsens: thermal-sensor@4a9000 { + compatible = "qcom,msm8937-tsens", "qcom,tsens-v1"; + reg = <0x004a9000 0x1000>, + <0x004a8000 0x1000>; + interrupts = ; + interrupt-names = "uplow"; + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>, + <&tsens_s10_p1>, <&tsens_s10_p2>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2", + "s10_p1", "s10_p2"; + #qcom,sensors = <11>; + #thermal-sensor-cells = <1>; + }; + + restart@4ab000 { + compatible = "qcom,pshold"; + reg = <0x004ab000 0x4>; + }; + + tlmm: pinctrl@1000000 { + compatible = "qcom,msm8917-pinctrl"; + reg = <0x01000000 0x300000>; + interrupts = ; + gpio-controller; + gpio-ranges = <&tlmm 0 0 134>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + blsp1_i2c2_default: blsp1-i2c2-default-state { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { + pins = "gpio6", "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c3_default: blsp1-i2c3-default-state { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { + pins = "gpio10", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c4_default: blsp1-i2c4-default-state { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { + pins = "gpio14", "gpio15"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c1_default: blsp2-i2c1-default-state { + pins = "gpio18", "gpio19"; + function = "blsp_i2c5"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { + pins = "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_spi3_default: blsp1-spi3-default-state { + cs-pins { + pins = "gpio10"; + function = "blsp_spi3"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio8", "gpio9", "gpio11"; + function = "blsp_spi3"; + drive-strength = <12>; + bias-disable; + }; + }; + + blsp1_spi3_sleep: blsp1-spi3-sleep-state { + cs-pins { + pins = "gpio10"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio8", "gpio9", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + blsp2_spi2_default: blsp2-spi2-default-state { + cs0-pins { + pins = "gpio47"; + function = "blsp_spi6"; + drive-strength = <16>; + bias-disable; + }; + + cs1-pins { + pins = "gpio22"; + function = "blsp_spi6"; + drive-strength = <16>; + bias-disable; + }; + + spi-pins { + pins = "gpio20", "gpio21", "gpio23"; + function = "blsp_spi6"; + drive-strength = <16>; + bias-disable; + }; + }; + + blsp2_spi2_sleep: blsp2-spi2-sleep-state { + cs0-pins { + pins = "gpio47"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + cs1-pins { + pins = "gpio22"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio20", "gpio21", "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + blsp1_uart1_default: blsp1-uart1-default-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "blsp_uart1"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_uart1_sleep: blsp1-uart1-sleep-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_uart2_default: blsp1-uart2-default-state { + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_uart2_sleep: blsp1-uart2-sleep-state { + pins = "gpio4", "gpio5"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + sdc1_default: sdc1-default-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_sleep: sdc1-sleep-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <2>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + sdc2_cmd_default: cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <16>; + bias-pull-up; + }; + + sdc2_data_default: data-pins { + pins = "sdc2_data"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + wcnss_pin_a: wcnss-active-state { + wcss-wlan-pins { + pins = "gpio79", "gpio80"; + function = "wcss_wlan"; + drive-strength = <6>; + bias-pull-up; + + }; + + wcss-wlan0-pins { + pins = "gpio78"; + function = "wcss_wlan0"; + drive-strength = <6>; + bias-pull-up; + + }; + + wcss-wlan1-pins { + pins = "gpio77"; + function = "wcss_wlan1"; + drive-strength = <6>; + bias-pull-up; + + }; + + wcss-wlan2-pins { + pins = "gpio76"; + function = "wcss_wlan2"; + drive-strength = <6>; + bias-pull-up; + + }; + }; + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,gcc-msm8937"; + reg = <0x01800000 0x80000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>; + clock-names = "xo", + "sleep", + "dsi0pll", + "dsi0pllbyte", + "dsi1pll", + "dsi1pllbyte"; + }; + + tcsr_mutex: hwlock@1905000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01905000 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr: syscon@1937000 { + compatible = "qcom,tcsr-msm8937", "syscon"; + reg = <0x01937000 0x30000>; + }; + + mdss: display-subsystem@1a00000 { + compatible = "qcom,mdss"; + reg = <0x01a00000 0x1000>, + <0x01ab0000 0x3000>; + reg-names = "mdss_phys", + "vbif_phys"; + ranges; + + power-domains = <&gcc MDSS_GDSC>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "vsync"; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + + mdp: display-controller@1a01000 { + compatible = "qcom,msm8937-mdp5", "qcom,mdp5"; + reg = <0x01a01000 0x89000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync"; + + iommus = <&apps_iommu 0x15>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdp5_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + mdp5_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + }; + + mdss_dsi0: dsi@1a94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0x01a94000 0x300>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + assigned-clocks = <&gcc BYTE0_CLK_SRC>, + <&gcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; + + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + phys = <&mdss_dsi0_phy>; + + operating-points-v2 = <&mdss_dsi0_opp_table>; + power-domains = <&rpmpd MSM8937_VDDCX>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&mdp5_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + }; + + mdss_dsi0_phy: phy@1a94400 { + compatible = "qcom,dsi-phy-28nm-8937"; + reg = <0x01a94a00 0xd4>, + <0x01a94400 0x280>, + <0x01a94b80 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", + "ref"; + + status = "disabled"; + }; + + mdss_dsi1: dsi@1a96000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0x01a96000 0x300>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + assigned-clocks = <&gcc MSM8937_BYTE1_CLK_SRC>, + <&gcc MSM8937_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; + + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc MSM8937_GCC_MDSS_BYTE1_CLK>, + <&gcc MSM8937_GCC_MDSS_PCLK1_CLK>, + <&gcc MSM8937_GCC_MDSS_ESC1_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + phys = <&mdss_dsi1_phy>; + + operating-points-v2 = <&mdss_dsi1_opp_table>; + power-domains = <&rpmpd MSM8937_VDDCX>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&mdp5_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + + mdss_dsi1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + }; + + mdss_dsi1_phy: phy@1a96a00 { + compatible = "qcom,dsi-phy-28nm-8937"; + reg = <0x01a96a00 0xd4>, + <0x01a96400 0x280>, + <0x01a94b80 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", + "ref"; + + status = "disabled"; + }; + }; + + gpu: gpu@1c00000 { + compatible = "qcom,adreno-505.0", "qcom,adreno"; + reg = <0x01c00000 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = ; + interrupt-names = "kgsl_3d0_irq"; + #cooling-cells = <2>; + clocks = <&gcc GCC_OXILI_GFX3D_CLK>, + <&gcc GCC_OXILI_AHB_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_BIMC_GPU_CLK>, + <&gcc MSM8937_GCC_OXILI_TIMER_CLK>, + <&gcc MSM8937_GCC_OXILI_AON_CLK>; + clock-names = "core", + "iface", + "mem_iface", + "alt_mem_iface", + "rbbmtimer", + "alwayson"; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&gcc OXILI_GX_GDSC>; + + iommus = <&adreno_smmu 0>; + + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + + status = "disabled"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_min_svs>; + }; + + opp-216000000 { + opp-hz = /bits/ 64 <216000000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_nom>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_nom_plus>; + }; + + opp-450000000 { + opp-hz = /bits/ 64 <450000000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_turbo>; + }; + }; + }; + + adreno_smmu: iommu@1c40000 { + compatible = "qcom,msm8996-smmu-v2", + "qcom,adreno-smmu", + "qcom,smmu-v2"; + reg = <0x01c40000 0x10000>; + + #global-interrupts = <1>; + interrupts = , + , + , + , + ; + #iommu-cells = <1>; + + clocks = <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_OXILI_AHB_CLK>; + clock-names = "bus", + "iface"; + + power-domains = <&gcc MSM8937_OXILI_CX_GDSC>; + }; + + apps_iommu: iommu@1e20000 { + compatible = "qcom,msm8937-iommu", "qcom,msm-iommu-v1"; + ranges = <0 0x01e20000 0x20000>; + + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names = "iface", + "bus"; + + qcom,iommu-secure-id = <17>; + + #address-cells = <1>; + #iommu-cells = <1>; + #size-cells = <1>; + + /* VFE */ + iommu-ctx@14000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x14000 0x1000>; + interrupts = ; + }; + + /* MDP_0 */ + iommu-ctx@15000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x15000 0x1000>; + interrupts = ; + }; + + /* VENUS_NS */ + iommu-ctx@16000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x16000 0x1000>; + interrupts = ; + }; + }; + + spmi_bus: spmi@200f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0200f000 0x001000>, + <0x02400000 0x800000>, + <0x02c00000 0x800000>, + <0x03800000 0x200000>, + <0x0200a000 0x002100>; + reg-names = "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + bam_dmux_dma: dma-controller@4044000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x04044000 0x19000>; + interrupts = ; + #dma-cells = <1>; + qcom,ee = <0>; + + num-channels = <6>; + qcom,num-ees = <1>; + qcom,powered-remotely; + + status = "disabled"; + }; + + sdhc_1: mmc@7824900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0x07824900 0x500>, + <0x07824000 0x800>; + reg-names = "hc", + "core"; + + interrupts = , + ; + interrupt-names = "hc_irq", + "pwr_irq"; + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", + "core", + "xo"; + pinctrl-0 = <&sdc1_default>; + pinctrl-1 = <&sdc1_sleep>; + pinctrl-names = "default", + "sleep"; + power-domains = <&rpmpd MSM8937_VDDCX>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-ddr-1_8v; + bus-width = <8>; + non-removable; + status = "disabled"; + }; + + sdhc_2: mmc@7864900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0x07864900 0x500>, + <0x07864000 0x800>; + reg-names = "hc", + "core"; + + interrupts = , + ; + interrupt-names = "hc_irq", + "pwr_irq"; + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", + "core", + "xo"; + pinctrl-0 = <&sdc2_default>; + pinctrl-1 = <&sdc2_sleep>; + pinctrl-names = "default", + "sleep"; + power-domains = <&rpmpd MSM8937_VDDCX>; + bus-width = <4>; + status = "disabled"; + }; + + blsp1_dma: dma-controller@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07884000 0x1f000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "bam_clk"; + qcom,controlled-remotely; + #dma-cells = <1>; + num-channels = <12>; + qcom,num-ees = <4>; + qcom,ee = <0>; + }; + + blsp1_uart2: serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b0000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", + "iface"; + dmas = <&blsp1_dma 2>, + <&blsp1_dma 3>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&blsp1_uart2_default>; + pinctrl-1 = <&blsp1_uart2_sleep>; + pinctrl-names = "default", + "sleep"; + status = "disabled"; + }; + + blsp1_i2c2: i2c@78b6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b6000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 6>, + <&blsp1_dma 7>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&blsp1_i2c2_default>; + pinctrl-1 = <&blsp1_i2c2_sleep>; + pinctrl-names = "default", + "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_i2c3: i2c@78b7000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b7000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", + "iface"; + dmas = <&blsp1_dma 8>, + <&blsp1_dma 9>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&blsp1_i2c3_default>; + pinctrl-1 = <&blsp1_i2c3_sleep>; + pinctrl-names = "default", + "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_spi3: spi@78b7000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b7000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", + "iface"; + dmas = <&blsp1_dma 8>, + <&blsp1_dma 9>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&blsp1_spi3_default>; + pinctrl-1 = <&blsp1_spi3_sleep>; + pinctrl-names = "default", + "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_i2c4: i2c@78b8000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b8000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", + "iface"; + dmas = <&blsp1_dma 10>, + <&blsp1_dma 11>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&blsp1_i2c4_default>; + pinctrl-1 = <&blsp1_i2c4_sleep>; + pinctrl-names = "default", + "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp2_dma: dma-controller@7ac4000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07ac4000 0x1d000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "bam_clk"; + qcom,controlled-remotely; + #dma-cells = <1>; + num-channels = <10>; + qcom,num-ees = <4>; + qcom,ee = <0>; + }; + + blsp2_i2c1: i2c@7af5000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x07af5000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", + "iface"; + dmas = <&blsp2_dma 4>, + <&blsp2_dma 5>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&blsp2_i2c1_default>; + pinctrl-1 = <&blsp2_i2c1_sleep>; + pinctrl-names = "default", + "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp2_spi2: spi@7af6000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x07af6000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", + "iface"; + dmas = <&blsp2_dma 6>, + <&blsp2_dma 7>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&blsp2_spi2_default>; + pinctrl-1 = <&blsp2_spi2_sleep>; + pinctrl-names = "default", + "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + usb: usb@78db000 { + compatible = "qcom,ci-hdrc"; + reg = <0x078db000 0x200>, + <0x078db200 0x200>; + interrupts = , + ; + clocks = <&gcc GCC_USB_HS_AHB_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + clock-names = "iface", + "core"; + assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates = <80000000>; + resets = <&gcc GCC_USB_HS_BCR>; + reset-names = "core"; + phy_type = "ulpi"; + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + ahb-burst-config = <0>; + phy-names = "usb-phy"; + phys = <&usb_hs_phy>; + status = "disabled"; + #reset-cells = <1>; + }; + + wcnss: remoteproc@a204000 { + compatible = "qcom,pronto-v3-pil", "qcom,pronto"; + reg = <0x0a204000 0x2000>, + <0x0a202000 0x1000>, + <0x0a21b000 0x3000>; + reg-names = "ccu", + "dxe", + "pmu"; + + memory-region = <&wcnss_mem>; + + interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + power-domains = <&rpmpd MSM8937_VDDCX>, + <&rpmpd MSM8937_VDDMX>; + power-domain-names = "cx", + "mx"; + + qcom,smem-states = <&wcnss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + pinctrl-0 = <&wcnss_pin_a>; + pinctrl-names = "default"; + + status = "disabled"; + + wcnss_iris: iris { + clocks = <&rpmcc RPM_SMD_RF_CLK2>; + clock-names = "xo"; + }; + + smd-edge { + interrupts = ; + + mboxes = <&apcs1 17>; + qcom,smd-edge = <6>; + qcom,remote-pid = <4>; + + label = "pronto"; + + wcnss_ctrl: wcnss { + compatible = "qcom,wcnss"; + qcom,smd-channels = "WCNSS_CTRL"; + + qcom,mmio = <&wcnss>; + + wcnss_bt: bluetooth { + compatible = "qcom,wcnss-bt"; + }; + + wcnss_wifi: wifi { + compatible = "qcom,wcnss-wlan"; + + interrupts = , + ; + interrupt-names = "tx", + "rx"; + + qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; + qcom,smem-state-names = "tx-enable", + "tx-rings-empty"; + }; + }; + }; + }; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0b000000 0x1000>, + <0x0b002000 0x1000>; + }; + + apcs1: mailbox@b011000 { + compatible = "qcom,msm8939-apcs-kpss-global", "syscon"; + reg = <0x0b011000 0x1000>; + #mbox-cells = <1>; + }; + + watchdog@b017000 { + compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; + reg = <0x0b017000 0x1000>; + clocks = <&sleep_clk>; + }; + + timer@b120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0b120000 0x1000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + frame@b121000 { + reg = <0x0b121000 0x1000>, + <0x0b122000 0x1000>; + frame-number = <0>; + interrupts = , + ; + }; + + frame@b123000 { + reg = <0x0b123000 0x1000>; + frame-number = <1>; + interrupts = ; + status = "disabled"; + }; + + frame@b124000 { + reg = <0x0b124000 0x1000>; + frame-number = <2>; + interrupts = ; + status = "disabled"; + }; + + frame@b125000 { + reg = <0x0b125000 0x1000>; + frame-number = <3>; + interrupts = ; + status = "disabled"; + }; + + frame@b126000 { + reg = <0x0b126000 0x1000>; + frame-number = <4>; + interrupts = ; + status = "disabled"; + }; + + frame@b127000 { + reg = <0x0b127000 0x1000>; + frame-number = <5>; + interrupts = ; + status = "disabled"; + }; + + frame@b128000 { + reg = <0x0b128000 0x1000>; + frame-number = <6>; + interrupts = ; + status = "disabled"; + }; + }; + }; + + thermal_zones: thermal-zones { + aoss-thermal { + thermal-sensors = <&tsens 0>; + + trips { + aoss_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + mdm-core-thermal { + thermal-sensors = <&tsens 1>; + + trips { + mdm_core_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + q6-thermal { + thermal-sensors = <&tsens 2>; + + trips { + q6_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + camera-thermal { + thermal-sensors = <&tsens 3>; + + trips { + camera_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpuss1-thermal { + thermal-sensors = <&tsens 4>; + + cooling-maps { + map0 { + trip = <&cpuss1_alert0>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpuss1_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpuss1_alert1: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpuss1_crit: cpuss1-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu4-thermal { + thermal-sensors = <&tsens 5>; + + cooling-maps { + map0 { + trip = <&cpu4_alert1>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu4_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_alert1: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu4_crit: cpu-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu5-thermal { + thermal-sensors = <&tsens 6>; + + cooling-maps { + map0 { + trip = <&cpu5_alert1>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu5_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu5_alert1: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_crit: cpu-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu6-thermal { + thermal-sensors = <&tsens 7>; + + cooling-maps { + map0 { + trip = <&cpu6_alert1>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu6_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu6_alert1: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_crit: cpu-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu7-thermal { + thermal-sensors = <&tsens 8>; + + cooling-maps { + map0 { + trip = <&cpu7_alert1>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu7_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu7_alert1: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_crit: cpu-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpuss0-thermal { + thermal-sensors = <&tsens 9>; + + cooling-maps { + map0 { + trip = <&cpuss0_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpuss0_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpuss0_alert1: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpuss0_crit: cpuss0-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens 10>; + + cooling-maps { + map0 { + trip = <&gpu_alert>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + gpu_alert: trip-point0 { + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_crit: gpu-crit { + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; + From 1a614267281fa477b7d1eeb7b225f106161eb739 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Barnab=C3=A1s=20Cz=C3=A9m=C3=A1n?= Date: Tue, 14 Oct 2025 16:04:25 +0200 Subject: [PATCH 085/138] dt-bindings: arm: qcom: Add Xiaomi Redmi 3S MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Document Xiaomi Redmi 3S (land). Add qcom,msm8937 for msm-id, board-id allow-list. Acked-by: Krzysztof Kozlowski Signed-off-by: Barnabás Czémán Link: https://lore.kernel.org/r/20251014-msm8937-v10-2-b3e8da82e968@mainlining.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index df3dd0798a7d..d84bd3bca201 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -192,6 +192,11 @@ properties: - xiaomi,riva - const: qcom,msm8917 + - items: + - enum: + - xiaomi,land + - const: qcom,msm8937 + - items: - enum: - flipkart,rimob @@ -1176,6 +1181,7 @@ allOf: - qcom,apq8094 - qcom,apq8096 - qcom,msm8917 + - qcom,msm8937 - qcom,msm8939 - qcom,msm8953 - qcom,msm8956 From 2144f6d57d8ef8b0c73bd97d8e5f2783e67afc35 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Barnab=C3=A1s=20Cz=C3=A9m=C3=A1n?= Date: Tue, 14 Oct 2025 16:04:26 +0200 Subject: [PATCH 086/138] arm64: dts: qcom: Add Xiaomi Redmi 3S MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add initial support for Xiaomi Redmi 3S (land). Reviewed-by: Konrad Dybcio Signed-off-by: Barnabás Czémán Link: https://lore.kernel.org/r/20251014-msm8937-v10-3-b3e8da82e968@mainlining.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/msm8937-xiaomi-land.dts | 381 ++++++++++++++++++ 2 files changed, 382 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8937-xiaomi-land.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index fc1db74f65b0..6f34d5ed331c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -74,6 +74,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-yiming-uz801v3.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8917-xiaomi-riva.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8929-wingtech-wt82918hd.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8937-xiaomi-land.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8939-asus-z00t.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8939-huawei-kiwi.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8939-longcheer-l9100.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8937-xiaomi-land.dts b/arch/arm64/boot/dts/qcom/msm8937-xiaomi-land.dts new file mode 100644 index 000000000000..91837ff940f1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8937-xiaomi-land.dts @@ -0,0 +1,381 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Barnabas Czeman + */ +/dts-v1/; + +#include +#include +#include + +#include "msm8937.dtsi" +#include "pm8937.dtsi" +#include "pmi8950.dtsi" + +/delete-node/ &qseecom_mem; + +/ { + model = "Xiaomi Redmi 3S (land)"; + compatible = "xiaomi,land", "qcom,msm8937"; + chassis-type = "handset"; + + qcom,msm-id = ; + qcom,board-id = <0x1000b 1>, <0x2000b 1>; + + aliases { + mmc0 = &sdhc_1; + mmc1 = &sdhc_2; + }; + + battery: battery { + compatible = "simple-battery"; + + charge-full-design-microamp-hours = <4100000>; + constant-charge-current-max-microamp = <1000000>; + voltage-min-design-microvolt = <3400000>; + voltage-max-design-microvolt = <4400000>; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "framebuffer0"; + + framebuffer0: framebuffer@8dd01000 { + compatible = "simple-framebuffer"; + reg = <0x0 0x8dd01000 0x0 (720 * 1280 * 3)>; + width = <720>; + height = <1280>; + stride = <(720 * 3)>; + format = "r8g8b8"; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + power-domains = <&gcc MDSS_GDSC>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + key-volup { + label = "Volume Up"; + linux,code = ; + gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + }; + }; + + irled { + compatible = "gpio-ir-tx"; + gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>; + }; + + reserved-memory { + reserved@84a00000 { + reg = <0x0 0x84a00000 0x0 0x1900000>; + no-map; + }; + + framebuffer: memory@8dd01000 { + reg = <0x0 0x8dd01000 0x0 (720 * 1280 * 3)>; + no-map; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&blsp1_i2c2 { + status = "okay"; + + led-controller@45 { + compatible = "awinic,aw2013"; + reg = <0x45>; + #address-cells = <1>; + #size-cells = <0>; + + vcc-supply = <&pm8937_l10>; + vio-supply = <&pm8937_l5>; + + led@0 { + reg = <0>; + function = LED_FUNCTION_STATUS; + led-max-microamp = <5000>; + color = ; + }; + + led@1 { + reg = <1>; + function = LED_FUNCTION_STATUS; + led-max-microamp = <5000>; + color = ; + }; + + led@2 { + reg = <2>; + function = LED_FUNCTION_STATUS; + led-max-microamp = <5000>; + color = ; + }; + }; +}; + +&blsp1_i2c3 { + status = "okay"; + + touchscreen@3e { + compatible = "edt,edt-ft5306"; + reg = <0x3e>; + + interrupts-extended = <&tlmm 65 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; + vcc-supply = <&pm8937_l10>; + iovcc-supply = <&pm8937_l5>; + + pinctrl-0 = <&tsp_int_rst_default>; + pinctrl-names = "default"; + + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; + }; +}; + +&pm8937_resin { + linux,code = ; + + status = "okay"; +}; + +&pm8937_spmi_regulators { + /* APC */ + pm8937_s5: s5 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&pmi8950_wled { + qcom,num-strings = <2>; + qcom,external-pfet; + qcom,current-limit-microamp = <20000>; + qcom,ovp-millivolt = <29600>; + + status = "okay"; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm8937-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + + vdd_l1_l19-supply = <&pm8937_s3>; + vdd_l2_l23-supply = <&pm8937_s3>; + vdd_l3-supply = <&pm8937_s3>; + vdd_l4_l5_l6_l7_l16-supply = <&pm8937_s4>; + vdd_l8_l11_l12_l17_l22-supply = <&vph_pwr>; + vdd_l9_l10_l13_l14_l15_l18-supply = <&vph_pwr>; + + pm8937_s1: s1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1225000>; + }; + + pm8937_s3: s3 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + pm8937_s4: s4 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8937_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8937_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8937_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8937_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8937_l8: l8 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2900000>; + }; + + pm8937_l9: l9 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pm8937_l10: l10 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + }; + + pm8937_l11: l11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + regulator-system-load = <200000>; + }; + + pm8937_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8937_l13: l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + pm8937_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8937_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8937_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8937_l17: l17 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2900000>; + }; + + pm8937_l19: l19 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1350000>; + }; + + pm8937_l22: l22 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + pm8937_l23: l23 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + }; +}; + +&sdc2_cmd_default { + drive-strength = <12>; +}; + +&sdc2_data_default { + drive-strength = <12>; +}; + +&sdhc_1 { + vmmc-supply = <&pm8937_l8>; + vqmmc-supply = <&pm8937_l5>; + + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 67 GPIO_ACTIVE_LOW>; + vmmc-supply = <&pm8937_l11>; + vqmmc-supply = <&pm8937_l12>; + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32768>; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <20 4>; + + gpio_keys_default: gpio-keys-default-state { + pins = "gpio91"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio67"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tsp_int_rst_default: tsp-int-rst-default-state { + pins = "gpio64", "gpio65"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; +}; + +&wcnss { + vddpx-supply = <&pm8937_l5>; + + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; + vddxo-supply = <&pm8937_l7>; + vddrfa-supply = <&pm8937_l19>; + vddpa-supply = <&pm8937_l9>; + vdddig-supply = <&pm8937_l5>; +}; + +&wcnss_mem { + status = "okay"; +}; + +&xo_board { + clock-frequency = <19200000>; +}; From bc303efddf8b2b781d7c002a31bb89bc6579df2c Mon Sep 17 00:00:00 2001 From: Rakesh Kota Date: Wed, 15 Oct 2025 18:04:55 +0530 Subject: [PATCH 087/138] arm64: dts: qcom: lemans-evk: Add resin key code for PMM8654AU Update the PMM8654AU resin input code to KEY_VOLUMEDOWN and enable it. Signed-off-by: Rakesh Kota Link: https://lore.kernel.org/r/20251015-add_pon_resin-v2-1-44e2e45de5f1@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index b21fa6bc36cf..c4faa16e8377 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -587,6 +587,11 @@ &pcie1_phy { status = "okay"; }; +&pmm8654au_0_pon_resin { + linux,code = ; + status = "okay"; +}; + &qupv3_id_0 { firmware-name = "qcom/sa8775p/qupv3fw.elf"; status = "okay"; From 6030fa06360b8b8d898b66ac156adaaf990b83cb Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 15 Oct 2025 18:32:16 +0200 Subject: [PATCH 088/138] arm64: dts: qcom: sdm845-starqltechn: Fix i2c-gpio node name Fix the following DT checker warning: $nodename:0: 'i2c21' does not match '^i2c(@.+|-[a-z0-9]+)?$' Fixes: 3a4600448bef ("arm64: dts: qcom: sdm845-starqltechn: add display PMIC") Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251015-topic-starltechn_i2c_gpio-v1-1-6d303184ee87@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts index 215e1491f3e9..493c69e99174 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts @@ -158,7 +158,7 @@ rmtfs_mem: rmtfs-mem@fde00000 { }; }; - i2c21 { + i2c-21 { compatible = "i2c-gpio"; sda-gpios = <&tlmm 127 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; scl-gpios = <&tlmm 128 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; From 42e56b53a1919dbbd78e140a9f8223f8136ac360 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eric=20Gon=C3=A7alves?= Date: Thu, 16 Oct 2025 16:21:29 -0400 Subject: [PATCH 089/138] arm64: dts: qcom: sm8250-samsung-common: correct reserved pins MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The S20 series has additional reserved pins for the fingerprint sensor, GPIO 20-23. Correct it by adding them into gpio-reserved-ranges. Fixes: 6657fe9e9f23 ("arm64: dts: qcom: add initial support for Samsung Galaxy S20 FE") Signed-off-by: Eric Gonçalves Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251016202129.226449-1-ghatto404@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250-samsung-common.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-samsung-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-samsung-common.dtsi index cf3d917addd8..ef7ea4f72bf9 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-samsung-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-samsung-common.dtsi @@ -159,7 +159,8 @@ &pon_resin { }; &tlmm { - gpio-reserved-ranges = <40 4>; /* I2C (Unused) */ + gpio-reserved-ranges = <20 4>, /* SPI (fingerprint scanner) */ + <40 4>; /* Unused */ }; &usb_1 { From 84ff999ae402b977c5518d0471fe9c4db453d6a7 Mon Sep 17 00:00:00 2001 From: Tingguo Cheng Date: Fri, 17 Oct 2025 10:56:55 +0800 Subject: [PATCH 090/138] arm64: dts: qcom: lemans-pmics: enable rtc Add RTC node, the RTC is controlled by PMIC device via spmi bus. Signed-off-by: Tingguo Cheng Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251017-add-rtc-for-lemans-v2-1-0aaf174b25b9@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans-pmics.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi b/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi index 1369c3d43f86..341119fc8244 100644 --- a/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi @@ -132,6 +132,15 @@ pmm8654au_0_pon_resin: resin { }; }; + pmm8654au_0_rtc: rtc@6100 { + compatible = "qcom,pmk8350-rtc"; + reg = <0x6100>, + <0x6200>; + reg-names = "rtc", + "alarm"; + interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + }; + pmm8654au_0_gpios: gpio@8800 { compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; reg = <0x8800>; From 8053174aac836f192e5738b2886fd4da35a25cd5 Mon Sep 17 00:00:00 2001 From: Gaurav Kohli Date: Fri, 17 Oct 2025 10:32:56 +0530 Subject: [PATCH 091/138] arm64: dts: qcom: lemans-evk: Enable AMC6821 fan controller Enable AMC6821 fan controller for lemans-evk platform and configure pwm polarity as inverted. Signed-off-by: Gaurav Kohli Link: https://lore.kernel.org/r/20251017050256.987660-1-gaurav.kohli@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index c4faa16e8377..b40fa203e4a2 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include #include @@ -501,6 +502,20 @@ mac_addr0: mac-addr@0 { }; }; +&i2c19 { + status = "okay"; + + fan_controller: fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + #pwm-cells = <2>; + + fan { + pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>; + }; + }; +}; + &iris { firmware-name = "qcom/vpu/vpu30_p4_s6_16mb.mbn"; @@ -592,6 +607,11 @@ &pmm8654au_0_pon_resin { status = "okay"; }; +&qup_i2c19_default { + drive-strength = <2>; + bias-pull-up; +}; + &qupv3_id_0 { firmware-name = "qcom/sa8775p/qupv3fw.elf"; status = "okay"; From 4b6e99e4889bee6e34b9bad16d225fa66a8c453f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 20 Oct 2025 10:31:22 +0200 Subject: [PATCH 092/138] arm64: dts: qcom: lemans: Align ethernet interconnect-names with schema Reshuffle the entries to match the expected order. Fixes the following warnings: (qcom,sa8775p-ethqos): interconnect-names:0: 'cpu-mac' was expected (qcom,sa8775p-ethqos): interconnect-names:1: 'mac-mem' was expected Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251020-topic-lemans_eth_dt-v1-1-25f4532addb2@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index ae8cf9203ace..0b154d57ba24 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -6823,11 +6823,12 @@ ethernet1: ethernet@23000000 { "ptp_ref", "phyaux"; - interconnects = <&aggre1_noc MASTER_EMAC_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_EMAC1_CFG QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "mac-mem", "cpu-mac"; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_EMAC1_CFG QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_EMAC_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cpu-mac", + "mac-mem"; power-domains = <&gcc EMAC1_GDSC>; @@ -6864,11 +6865,12 @@ ethernet0: ethernet@23040000 { "ptp_ref", "phyaux"; - interconnects = <&aggre1_noc MASTER_EMAC QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_EMAC_CFG QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "mac-mem", "cpu-mac"; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_EMAC_CFG QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_EMAC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cpu-mac", + "mac-mem"; power-domains = <&gcc EMAC0_GDSC>; From 222c975e06af18af0c9ab5d0b23811bed9c882e2 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 20 Oct 2025 12:13:38 +0200 Subject: [PATCH 093/138] arm64: dts: qcom: sdx75: Fix the USB interrupt entry order The DP and DM interrupts are expected to come in a different order. Reorder them to align with bindings. Signed-off-by: Konrad Dybcio Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20251020-topic-sdx75_usb-v1-1-1a96d5de19c9@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index 75bfc19f412c..f26ba90ba66d 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -1043,13 +1043,13 @@ usb: usb@a6f8800 { interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 9 IRQ_TYPE_EDGE_RISING>, <&pdc 10 IRQ_TYPE_EDGE_RISING>, + <&pdc 9 IRQ_TYPE_EDGE_RISING>, <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pwr_event", "hs_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq", + "dm_hs_phy_irq", "ss_phy_irq"; power-domains = <&gcc GCC_USB30_GDSC>; From 720ebcc3e6b46fe4e01f4ecf1a8a899af213e433 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Guido=20G=C3=BCnther?= Date: Mon, 20 Oct 2025 13:58:24 +0200 Subject: [PATCH 094/138] arm64: dts: qcom: sdm845-shift-axolotl: Drop address and size cells from panel MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit They're set in the parent to describe the panel's reg property already. Fixes the linux/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dtb: panel@0 (visionox,rm69299-shift): '#address-cells', '#size-cells' do not match any of the regexes: '^pinctrl-[0-9]+$' warning. Signed-off-by: Guido Günther Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251020-shift6mq-dt-v2-1-d8fc3ec71281@sigxcpu.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index 89260fce6513..46ca4a38a9a8 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -479,9 +479,6 @@ panel@0 { vdda-supply = <&vreg_l14a_1p88>; vdd3p3-supply = <&vreg_l28a_3p0>; - #address-cells = <1>; - #size-cells = <0>; - reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; pinctrl-names = "default", "sleep"; From ab9a2c821ad229c4e8dd48b0126e40cc85a8cd51 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Mon, 20 Oct 2025 23:12:56 +0200 Subject: [PATCH 095/138] arm64: dts: qcom: sdm845: Define guard pages within the rmtfs region Use qcom,use-guard-pages property instead of polluting device-tree with lower and upper rmtfs guard nodes. No functional change intended. cosmetic: set name the node rmtfs-region. Signed-off-by: David Heidelberg Reviewed-by: Konrad Dybcio Tested-By: Paul Sajna Link: https://lore.kernel.org/r/20251020-sdm845-use-guard-pages-v1-1-64d714f8bd73@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi | 17 +++-------------- .../boot/dts/qcom/sdm845-oneplus-common.dtsi | 18 +++--------------- 2 files changed, 6 insertions(+), 29 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi index 99dafc6716e7..83b98bad19dd 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi @@ -99,26 +99,15 @@ memory@9d400000 { no-map; }; - /* rmtfs lower guard */ - memory@f0800000 { - reg = <0 0xf0800000 0 0x1000>; - no-map; - }; - - rmtfs_mem: memory@f0801000 { + rmtfs_mem: rmtfs-region@f0800000 { compatible = "qcom,rmtfs-mem"; - reg = <0 0xf0801000 0 0x200000>; + reg = <0 0xf0800000 0 0x202000>; + qcom,use-guard-pages; no-map; qcom,client-id = <1>; qcom,vmid = ; }; - - /* rmtfs upper guard */ - memory@f0a01000 { - reg = <0 0xf0a01000 0 0x1000>; - no-map; - }; }; gpio-keys { diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 51a9a276399a..eb708ebdb020 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -75,32 +75,20 @@ key-vol-up { }; reserved-memory { - /* - * The rmtfs_mem needs to be guarded due to "XPU limitations" - * it is otherwise possible for an allocation adjacent to the - * rmtfs_mem region to trigger an XPU violation, causing a crash. - */ - rmtfs_lower_guard: rmtfs-lower-guard@f5b00000 { - no-map; - reg = <0 0xf5b00000 0 0x1000>; - }; /* * The rmtfs memory region in downstream is 'dynamically allocated' * but given the same address every time. Hard code it as this address is * where the modem firmware expects it to be. */ - rmtfs_mem: rmtfs-mem@f5b01000 { + rmtfs_mem: rmtfs-region@f5b00000 { compatible = "qcom,rmtfs-mem"; - reg = <0 0xf5b01000 0 0x200000>; + reg = <0 0xf5b00000 0 0x202000>; + qcom,use-guard-pages; no-map; qcom,client-id = <1>; qcom,vmid = ; }; - rmtfs_upper_guard: rmtfs-upper-guard@f5d01000 { - no-map; - reg = <0 0xf5d01000 0 0x1000>; - }; /* * It seems like reserving the old rmtfs_mem region is also needed to prevent From e19dc81263853d7fb41944db9fe7a54400c0b1b0 Mon Sep 17 00:00:00 2001 From: Joel Selvaraj Date: Tue, 21 Oct 2025 01:20:49 -0500 Subject: [PATCH 096/138] arm64: dts: qcom: sdm845-shift-axolotl: fix touchscreen properties The touchscreen properties previously upstreamed was based on downstream touchscreen driver. We ended up adapting upstream edt_ft5x06 driver to support the touchscreen controller used in this device. Update the touchscreen properties to match with the upstream edt_ft5x06 driver. Also, the touchscreen controller used in this device is ft5452 and not fts8719. Fix the compatible string accordingly. The wakeup-source property was removed as it prevents the touchscreen's regulators and irq from being disabled when the device is suspended and could lead to unexpected battery drain. Once low power mode and tap-to-wake functionality is properly implemented and tested to be working, we can add it back, if needed. Signed-off-by: Joel Selvaraj Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251021-shift-axolotl-fix-touchscreen-dts-v2-1-e94727f0aa7e@joelselvaraj.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm845-shift-axolotl.dts | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index 46ca4a38a9a8..f0ae0159f32a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -434,20 +434,19 @@ &i2c5 { status = "okay"; touchscreen@38 { - compatible = "focaltech,fts8719"; + compatible = "focaltech,ft5452"; reg = <0x38>; - wakeup-source; - interrupt-parent = <&tlmm>; - interrupts = <125 IRQ_TYPE_EDGE_FALLING>; - vdd-supply = <&vreg_l28a_3p0>; - vcc-i2c-supply = <&vreg_l14a_1p88>; - pinctrl-names = "default", "suspend"; + interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l28a_3p0>; + iovcc-supply = <&vreg_l14a_1p88>; + pinctrl-0 = <&ts_int_active &ts_reset_active>; pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-names = "default", "suspend"; - reset-gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>; - irq-gpio = <&tlmm 125 GPIO_TRANSITORY>; touchscreen-size-x = <1080>; touchscreen-size-y = <2160>; }; From f8d21b5e4caa7a8e06cf6c08d85f6e992562a667 Mon Sep 17 00:00:00 2001 From: Alexey Klimov Date: Wed, 22 Oct 2025 07:06:41 +0100 Subject: [PATCH 097/138] arm64: dts: qcom: qcm2290: add APR and its services Add APR (asynchronous packet router) node and its associated services required to enable audio on QRB2210 RB1 board. Cc: Srinivas Kandagatla Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Alexey Klimov Link: https://lore.kernel.org/r/20251022-rb1_hdmi_audio-v3-1-0d38f777a547@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 72 +++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index ffb194be7b01..5131388f1502 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -17,6 +17,8 @@ #include #include #include +#include +#include / { interrupt-parent = <&intc>; @@ -2125,6 +2127,76 @@ glink-edge { label = "lpass"; qcom,remote-pid = <2>; mboxes = <&apcs_glb 8>; + + apr { + compatible = "qcom,apr-v2"; + qcom,glink-channels = "apr_audio_svc"; + qcom,domain = ; + #address-cells = <1>; + #size-cells = <0>; + + service@3 { + reg = ; + compatible = "qcom,q6core"; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + }; + + q6afe: service@4 { + compatible = "qcom,q6afe"; + reg = ; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + q6afedai: dais { + compatible = "qcom,q6afe-dais"; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + }; + + q6afecc: clock-controller { + compatible = "qcom,q6afe-clocks"; + #clock-cells = <2>; + }; + }; + + q6asm: service@7 { + compatible = "qcom,q6asm"; + reg = ; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + q6asmdai: dais { + compatible = "qcom,q6asm-dais"; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + iommus = <&apps_smmu 0x1c1 0x0>; + + dai@0 { + reg = ; + }; + + dai@1 { + reg = ; + }; + + dai@2 { + reg = ; + }; + }; + }; + + q6adm: service@8 { + compatible = "qcom,q6adm"; + reg = ; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + q6routing: routing { + compatible = "qcom,q6adm-routing"; + #sound-dai-cells = <0>; + }; + }; + }; }; }; From 1fc30731562bb45e53e09d40fc69bc4364310b6e Mon Sep 17 00:00:00 2001 From: Alexey Klimov Date: Wed, 22 Oct 2025 07:06:42 +0100 Subject: [PATCH 098/138] arm64: dts: qcom: qcm2290: add LPASS LPI pin controller Add the Low Power Audio SubSystem Low Power Island (LPASS LPI) pin controller device node required for audio subsystem on Qualcomm QRB2210 RB1. QRB2210 is based on qcm2290 which is based on sm6115. While at this, also add description of lpi_i2s2 pins (active state) required for audio playback via HDMI/I2S. Cc: Srinivas Kandagatla Signed-off-by: Alexey Klimov Link: https://lore.kernel.org/r/20251022-rb1_hdmi_audio-v3-2-0d38f777a547@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 38 +++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 5131388f1502..c6544ffa6f32 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -19,6 +19,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -687,6 +688,43 @@ data-pins { }; }; + lpass_tlmm: pinctrl@a7c0000 { + compatible = "qcom,qcm2290-lpass-lpi-pinctrl", + "qcom,sm6115-lpass-lpi-pinctrl"; + reg = <0x0 0x0a7c0000 0x0 0x20000>, + <0x0 0x0a950000 0x0 0x10000>; + + clocks = <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "audio"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 19>; + + lpi_i2s2_active: lpi-i2s2-active-state { + sck-pins { + pins = "gpio10"; + function = "i2s2_clk"; + bias-disable; + drive-strength = <8>; + }; + + ws-pins { + pins = "gpio11"; + function = "i2s2_ws"; + bias-disable; + drive-strength = <8>; + }; + + data-pins { + pins = "gpio12"; + function = "i2s2_data"; + bias-disable; + drive-strength = <8>; + }; + }; + }; + gcc: clock-controller@1400000 { compatible = "qcom,gcc-qcm2290"; reg = <0x0 0x01400000 0x0 0x1f0000>; From acb854eba80dceb12329cbe162122491f13a8a2a Mon Sep 17 00:00:00 2001 From: Alexey Klimov Date: Wed, 22 Oct 2025 07:06:43 +0100 Subject: [PATCH 099/138] arm64: dts: qcom: qrb2210-rb1: add HDMI/I2S audio playback support Add sound node and aDSP-related pieces to enable HDMI+I2S audio playback support on Qualcomm QR2210 RB1 board. That is the only sound output supported for now. The audio playback is verified using the following commands: amixer -c0 cset iface=MIXER,name='SEC_MI2S_RX Audio Mixer MultiMedia1' 1 aplay -D hw:0,0 /usr/share/sounds/alsa/Front_Center.wav Cc: Srinivas Kandagatla Reviewed-by: Konrad Dybcio Signed-off-by: Alexey Klimov Link: https://lore.kernel.org/r/20251022-rb1_hdmi_audio-v3-3-0d38f777a547@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 55 ++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts index 67ba508e92ba..43af25d17aa8 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -188,6 +188,53 @@ vph_pwr: regulator-vph-pwr { regulator-always-on; regulator-boot-on; }; + + sound { + compatible = "qcom,qrb2210-sndcard"; + pinctrl-0 = <&lpi_i2s2_active>; + pinctrl-names = "default"; + model = "Qualcomm-RB1-WSA8815-Speaker-DMIC0"; + + mm1-dai-link { + link-name = "MultiMedia1"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; + }; + + mm2-dai-link { + link-name = "MultiMedia2"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; + }; + }; + + mm3-dai-link { + link-name = "MultiMedia3"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; + }; + }; + + hdmi-i2s-dai-link { + link-name = "HDMI/I2S Playback"; + + codec { + sound-dai = <<9611_codec 0>; + }; + + cpu { + sound-dai = <&q6afedai SECONDARY_MI2S_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + }; + }; }; &cpu_pd0 { @@ -323,6 +370,14 @@ &pm4125_vbus { status = "okay"; }; +/* SECONDARY I2S uses 1 I2S SD Line for audio on LT9611UXC HDMI Bridge */ +&q6afedai { + dai@18 { + reg = ; + qcom,sd-lines = <0>; + }; +}; + &qupv3_id_0 { status = "okay"; }; From ec9d588391761a08aab5eb4523a48ef3df2c910f Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 23 Oct 2025 13:39:26 +0200 Subject: [PATCH 100/138] arm64: dts: qcom: sm6350: Fix wrong order of freq-table-hz for UFS During upstreaming the order of clocks was adjusted to match the upstream sort order, but mistakently freq-table-hz wasn't re-ordered with the new order. Fix that by moving the entry for the ICE clk to the last place. Fixes: 5a814af5fc22 ("arm64: dts: qcom: sm6350: Add UFS nodes") Cc: stable@vger.kernel.org Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20251023-sm6350-ufs-things-v3-1-b68b74e29d35@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 14788d60faf0..0d2eb51ecc50 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1180,11 +1180,11 @@ ufs_mem_hc: ufshc@1d84000 { <0 0>, <0 0>, <37500000 150000000>, - <75000000 300000000>, <0 0>, <0 0>, <0 0>, - <0 0>; + <0 0>, + <75000000 300000000>; status = "disabled"; }; From 06d262bcdb3bc86805739de1c484761f0a59a453 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 23 Oct 2025 13:39:27 +0200 Subject: [PATCH 101/138] arm64: dts: qcom: sm6350: Add OPP table support to UFSHC UFS host controller, when scaling gears, should choose appropriate performance state of RPMh power domain controller along with clock frequency. So let's add the OPP table support to specify both clock frequency and RPMh performance states replacing the old "freq-table-hz" property. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20251023-sm6350-ufs-things-v3-2-b68b74e29d35@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 42 +++++++++++++++++++++------- 1 file changed, 32 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 0d2eb51ecc50..c00ba5bb8c51 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1175,18 +1175,40 @@ ufs_mem_hc: ufshc@1d84000 { <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; - freq-table-hz = - <50000000 200000000>, - <0 0>, - <0 0>, - <37500000 150000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>, - <75000000 300000000>; + + operating-points-v2 = <&ufs_opp_table>; status = "disabled"; + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <37500000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <150000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; ufs_mem_phy: phy@1d87000 { From c1a45887a36ef7ded3fb4bac59d4a3445098b04b Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 23 Oct 2025 13:39:28 +0200 Subject: [PATCH 102/138] arm64: dts: qcom: sm6350: Add interconnect support to UFS Define the two NoC paths used by UFS: ufs-ddr and cpu-ufs. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20251023-sm6350-ufs-things-v3-3-b68b74e29d35@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index c00ba5bb8c51..f34dc6e278b8 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1178,6 +1178,13 @@ ufs_mem_hc: ufshc@1d84000 { operating-points-v2 = <&ufs_opp_table>; + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "ufs-ddr", + "cpu-ufs"; + status = "disabled"; ufs_opp_table: opp-table { From d5e86096feb689c9f5d9aa07c913747ba430a600 Mon Sep 17 00:00:00 2001 From: Manikanta Mylavarapu Date: Thu, 23 Oct 2025 10:08:38 +0530 Subject: [PATCH 103/138] arm64: dts: qcom: ipq5424: add cooling maps for CPU thermal zones Add cooling-maps to the cpu1, cpu2, and cpu3 thermal zones to associate passive trip points with CPU cooling devices. This enables proper thermal mitigation by allowing the thermal framework to throttle CPUs based on temperature thresholds. Also, label the trip points to allow referencing them in the cooling maps. Signed-off-by: Manikanta Mylavarapu Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251023043838.1603673-1-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5424.dtsi | 61 +++++++++++++++++++++++---- 1 file changed, 53 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index ef2b52f3597d..e4a51eeefeac 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -13,6 +13,7 @@ #include #include #include +#include / { #address-cells = <2>; @@ -57,6 +58,7 @@ cpu0: cpu@0 { clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; + #cooling-cells = <2>; l2_0: l2-cache { compatible = "cache"; @@ -82,6 +84,7 @@ cpu1: cpu@100 { clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; + #cooling-cells = <2>; l2_100: l2-cache { compatible = "cache"; @@ -101,6 +104,7 @@ cpu2: cpu@200 { clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; + #cooling-cells = <2>; l2_200: l2-cache { compatible = "cache"; @@ -120,6 +124,7 @@ cpu3: cpu@300 { clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; + #cooling-cells = <2>; l2_300: l2-cache { compatible = "cache"; @@ -1235,18 +1240,28 @@ cpu0-thermal { thermal-sensors = <&tsens 14>; trips { - cpu-critical { + cpu0_crit: cpu-critical { temperature = <120000>; hysteresis = <9000>; type = "critical"; }; - cpu-passive { + cpu0_alert: cpu-passive { temperature = <110000>; hysteresis = <9000>; type = "passive"; }; }; + + cooling-maps { + map0 { + trip = <&cpu0_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu1-thermal { @@ -1254,18 +1269,28 @@ cpu1-thermal { thermal-sensors = <&tsens 12>; trips { - cpu-critical { + cpu1_crit: cpu-critical { temperature = <120000>; hysteresis = <9000>; type = "critical"; }; - cpu-passive { + cpu1_alert: cpu-passive { temperature = <110000>; hysteresis = <9000>; type = "passive"; }; }; + + cooling-maps { + map0 { + trip = <&cpu1_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu2-thermal { @@ -1273,18 +1298,28 @@ cpu2-thermal { thermal-sensors = <&tsens 11>; trips { - cpu-critical { + cpu2_crit: cpu-critical { temperature = <120000>; hysteresis = <9000>; type = "critical"; }; - cpu-passive { + cpu2_alert: cpu-passive { temperature = <110000>; hysteresis = <9000>; type = "passive"; }; }; + + cooling-maps { + map0 { + trip = <&cpu2_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu3-thermal { @@ -1292,18 +1327,28 @@ cpu3-thermal { thermal-sensors = <&tsens 13>; trips { - cpu-critical { + cpu3_crit: cpu-critical { temperature = <120000>; hysteresis = <9000>; type = "critical"; }; - cpu-passive { + cpu3_alert: cpu-passive { temperature = <110000>; hysteresis = <9000>; type = "passive"; }; }; + + cooling-maps { + map0 { + trip = <&cpu3_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; wcss-tile2-thermal { From b54c412b511c8bc8e71fd09a766bd95528d94840 Mon Sep 17 00:00:00 2001 From: Aleksandrs Vinarskis Date: Wed, 10 Sep 2025 14:01:11 +0200 Subject: [PATCH 104/138] arm64: dts: qcom: sc8280xp-x13s: enable camera privacy indicator Leverage newly introduced 'leds' and 'led-names' properties to pass indicator's phandle and function to v4l2 subnode. The latter supports privacy led since couple of years ago under 'privacy-led' designation. Unlike initially proposed trigger-source based approach, this solution cannot be easily bypassed from userspace, thus reducing privacy concerns. Signed-off-by: Aleksandrs Vinarskis Tested-by: Steev Klimaszewski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250910-leds-v5-4-bb90a0f897d5@vinarskis.com Signed-off-by: Bjorn Andersson --- .../arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 637430719e6d..3b3f7137689a 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -83,14 +83,11 @@ leds { pinctrl-names = "default"; pinctrl-0 = <&cam_indicator_en>; - led-camera-indicator { - label = "white:camera-indicator"; + privacy_led: privacy-led { function = LED_FUNCTION_INDICATOR; color = ; gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; default-state = "off"; - /* Reuse as a panic indicator until we get a "camera on" trigger */ panic-indicator; }; }; @@ -685,6 +682,9 @@ camera@10 { pinctrl-names = "default"; pinctrl-0 = <&cam_rgb_default>; + leds = <&privacy_led>; + led-names = "privacy"; + clocks = <&camcc CAMCC_MCLK3_CLK>; orientation = <0>; /* Front facing */ From 7cb69f89700d031f6984b787a918bc5825c067cd Mon Sep 17 00:00:00 2001 From: "Yu Zhang(Yuriy)" Date: Thu, 18 Sep 2025 19:27:29 +0800 Subject: [PATCH 105/138] arm64: dts: qcom: qcs615-ride: Set drive strength for wlan-en-state pin Set the drive-strength to 16mA for gpio98 used as wlan-en-state in the QCS615 ride platform device tree. This ensures sufficient output strength for controlling the WLAN enable signal reliably. Signed-off-by: Yu Zhang (Yuriy) Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250918112729.3512516-1-yu.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index e8faa25da79f..1e79ab70967f 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -398,6 +398,7 @@ wlan_en_state: wlan-en-state { pins = "gpio98"; function = "gpio"; bias-pull-down; + drive-strength = <16>; output-low; }; }; From 67445dc8a8060309eeb7aebbc41fa0e58302fc09 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Thu, 18 Sep 2025 17:54:56 +0200 Subject: [PATCH 106/138] arm64: dts: qcom: qcm2290: Fix camss register prop ordering The qcm2290 CAMSS node has been applied from the V4 series, but a later version changed the order of the register property, fix it to prevent dtb check error. Fixes: 2b3aef30dd9d ("arm64: dts: qcom: qcm2290: Add CAMSS node") Signed-off-by: Loic Poulain Link: https://lore.kernel.org/r/20250918155456.1158691-1-loic.poulain@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 08141b41de24..3b0ba590ee82 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -1685,25 +1685,25 @@ cci_i2c1: i2c-bus@1 { }; }; - camss: camss@5c6e000 { + camss: camss@5c11000 { compatible = "qcom,qcm2290-camss"; - reg = <0x0 0x5c6e000 0x0 0x1000>, + reg = <0x0 0x5c11000 0x0 0x1000>, + <0x0 0x5c6e000 0x0 0x1000>, <0x0 0x5c75000 0x0 0x1000>, <0x0 0x5c52000 0x0 0x1000>, <0x0 0x5c53000 0x0 0x1000>, <0x0 0x5c66000 0x0 0x400>, <0x0 0x5c68000 0x0 0x400>, - <0x0 0x5c11000 0x0 0x1000>, <0x0 0x5c6f000 0x0 0x4000>, <0x0 0x5c76000 0x0 0x4000>; - reg-names = "csid0", + reg-names = "top", + "csid0", "csid1", "csiphy0", "csiphy1", "csitpg0", "csitpg1", - "top", "vfe0", "vfe1"; From 74c2c1e0d0784a13d0709e6ec4dbac3ab1f29f97 Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Fri, 19 Sep 2025 11:18:50 +0800 Subject: [PATCH 107/138] arm64: dts: qcom: x1e80100-crd: Add charge limit nvmem Add nvmem cells for getting charge control thresholds if they have been set previously. Tested-by: Neil Armstrong # on Thinkpad T14S OLED Reviewed-by: Konrad Dybcio Signed-off-by: Fenglin Wu Link: https://lore.kernel.org/r/20250919-qcom_battmgr_update_new-v6-1-ed5c38867614@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi | 20 ++++++++++++++++++++ arch/arm64/boot/dts/qcom/x1-crd.dtsi | 7 +++++++ 2 files changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi b/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi index 621890ada153..6a31a0adf8be 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi @@ -240,6 +240,26 @@ reboot_reason: reboot-reason@48 { }; }; + pmk8550_sdam_15: nvram@7e00 { + compatible = "qcom,spmi-sdam"; + reg = <0x7e00>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x7e00 0x100>; + + charge_limit_en: charge-limit-en@73 { + reg = <0x73 0x1>; + }; + + charge_limit_end: charge-limit-end@75 { + reg = <0x75 0x1>; + }; + + charge_limit_delta: charge-limit-delta@76 { + reg = <0x76 0x1>; + }; + }; + pmk8550_gpios: gpio@8800 { compatible = "qcom,pmk8550-gpio", "qcom,spmi-gpio"; reg = <0xb800>; diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi index 5e324f35547a..ded96fb43489 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -82,6 +82,13 @@ pmic-glink { <&tlmm 123 GPIO_ACTIVE_HIGH>, <&tlmm 125 GPIO_ACTIVE_HIGH>; + nvmem-cells = <&charge_limit_en>, + <&charge_limit_end>, + <&charge_limit_delta>; + nvmem-cell-names = "charge_limit_en", + "charge_limit_end", + "charge_limit_delta"; + /* Left-side rear port */ connector@0 { compatible = "usb-c-connector"; From e7a1bf542c3b254e4f3e8981e2b769f5c7424960 Mon Sep 17 00:00:00 2001 From: Luo Jie Date: Tue, 14 Oct 2025 22:35:34 +0800 Subject: [PATCH 108/138] arm64: dts: qcom: ipq5424: Add NSS clock controller node NSS clock controller provides the clocks and resets to the networking hardware blocks on the IPQ5424, such as PPE (Packet Process Engine) and UNIPHY (PCS) blocks. Reviewed-by: Konrad Dybcio Signed-off-by: Luo Jie Link: https://lore.kernel.org/r/20251014-qcom_ipq5424_nsscc-v7-9-081f4956be02@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5424.dtsi | 32 ++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index e4a51eeefeac..58e6852bebbc 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -3,7 +3,7 @@ * IPQ5424 device tree source * * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include @@ -820,6 +820,36 @@ apss_clk: clock-controller@fa80000 { #interconnect-cells = <1>; }; + clock-controller@39b00000 { + compatible = "qcom,ipq5424-nsscc"; + reg = <0 0x39b00000 0 0x100000>; + clocks = <&cmn_pll IPQ5424_XO_24MHZ_CLK>, + <&cmn_pll IPQ5424_NSS_300MHZ_CLK>, + <&cmn_pll IPQ5424_PPE_375MHZ_CLK>, + <&gcc GPLL0_OUT_AUX>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&gcc GCC_NSSCC_CLK>; + clock-names = "xo", + "nss", + "ppe", + "gpll0_out", + "uniphy0_rx", + "uniphy0_tx", + "uniphy1_rx", + "uniphy1_tx", + "uniphy2_rx", + "uniphy2_tx", + "bus"; + #clock-cells = <1>; + #reset-cells = <1>; + #interconnect-cells = <1>; + }; + pcie3: pcie@40000000 { compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574"; reg = <0x0 0x40000000 0x0 0xf1c>, From 500d3d0e88362eaee5e655bcd3ab2e9c808bec66 Mon Sep 17 00:00:00 2001 From: Xin Liu Date: Tue, 28 Oct 2025 19:31:35 -0700 Subject: [PATCH 109/138] arm64: dts: qcom: qcs615-ride: Update 'model' string for qcs615 ride Update the 'model' property in the QCS615-ride device tree to include the public board name "IQ-615 Beta EVK". This ensures consistency with official documentation and release notes. Signed-off-by: Xin Liu Link: https://lore.kernel.org/r/20251029023137.381386-1-xin.liu@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index 1e79ab70967f..7a0a0cb29fef 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -10,7 +10,7 @@ #include "talos.dtsi" #include "pm8150.dtsi" / { - model = "Qualcomm Technologies, Inc. QCS615 Ride"; + model = "Qualcomm Technologies, Inc. QCS615 Ride (IQ-615 Beta EVK)"; compatible = "qcom,qcs615-ride", "qcom,qcs615", "qcom,sm6150"; chassis-type = "embedded"; From c3398456f6f6121e79f6c3d9bff00076cf7a3521 Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Mon, 8 Sep 2025 16:11:22 +0530 Subject: [PATCH 110/138] arm64: dts: qcom: sm8550: Limit max SD HS mode frequency by default Due to an implementation detail in this SoC, additional passive electrical components are required to achieve the maximum rated speed of the SD controller when paired with a High-Speed SD Card. Without them, the clock frequency must be limited to 37.5 MHz for link stability. Because the reference design does not contain these components, most (derivative) boards do not have them either. To accommodate for that, apply the frequency limit by default and delegate lifting it to the odd boards that do contain the necessary onboard hardware. Signed-off-by: Sarthak Garg Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250908104122.2062653-5-quic_sartgarg@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index aa3167d10a41..04e6db8f1030 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3224,6 +3224,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "sdhc-ddr", "cpu-sdhc"; bus-width = <4>; + max-sd-hs-hz = <37500000>; dma-coherent; /* Forbid SDR104/SDR50 - broken hw! */ From bf9f0bb2ec478926c50769ad0df363719d5d2302 Mon Sep 17 00:00:00 2001 From: Li Liu Date: Wed, 3 Sep 2025 18:49:28 +0800 Subject: [PATCH 111/138] arm64: dts: qcom: Add display support for QCS615 Add display MDSS and DSI configuration for QCS615 platform. QCS615 has a DP port, and DP support will be added in a later patch. Reviewed-by: Dmitry Baryshkov Signed-off-by: Li Liu Signed-off-by: Fange Zhang Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250903-add-display-support-for-qcs615-platform-v8-1-7971c05d1262@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/talos.dtsi | 182 +++++++++++++++++++++++++++- 1 file changed, 180 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index eb6f69be4a82..d1dbfa3bd81c 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. */ +#include #include #include #include @@ -3795,14 +3796,191 @@ camcc: clock-controller@ad00000 { #power-domain-cells = <1>; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,sm6150-mdss"; + reg = <0x0 0x0ae00000 0x0 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; + + power-domains = <&dispcc MDSS_CORE_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x800 0x0>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sm6150-dpu"; + reg = <0x0 0x0ae01000 0x0 0x8f000>, + <0x0 0x0aeb0000 0x0 0x2008>; + reg-names = "mdp", + "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd RPMHPD_CX>; + + interrupts-extended = <&mdss 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf0_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-256000000 { + opp-hz = /bits/ 64 <256000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-307200000 { + opp-hz = /bits/ 64 <307200000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,sm6150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0 0x0ae94000 0x0 0x400>; + reg-names = "dsi_ctrl"; + + interrupts-extended = <&mdss 4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 = <&dsi0_opp_table>; + power-domains = <&rpmhpd RPMHPD_CX>; + + phys = <&mdss_dsi0_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + dsi0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-164000000 { + opp-hz = /bits/ 64 <164000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,sm6150-dsi-phy-14nm"; + reg = <0x0 0x0ae94400 0x0 0x100>, + <0x0 0x0ae94500 0x0 0x300>, + <0x0 0x0ae94800 0x0 0x124>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "ref"; + + status = "disabled"; + }; + }; + dispcc: clock-controller@af00000 { compatible = "qcom,qcs615-dispcc"; reg = <0 0x0af00000 0 0x20000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, - <0>, - <0>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, <0>, <0>, <0>; From 0b4bbf0514fce4acf34676dd107c01dba7f96c33 Mon Sep 17 00:00:00 2001 From: Li Liu Date: Wed, 3 Sep 2025 18:49:29 +0800 Subject: [PATCH 112/138] arm64: dts: qcom: Add display support for QCS615 RIDE board Add display MDSS and DSI configuration for QCS615 RIDE board. QCS615 has a DP port, and DP support will be added in a later patch. Reviewed-by: Dmitry Baryshkov Signed-off-by: Li Liu Signed-off-by: Fange Zhang Link: https://lore.kernel.org/r/20250903-add-display-support-for-qcs615-platform-v8-2-7971c05d1262@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 150 +++++++++++++++++++++++ 1 file changed, 150 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index 7a0a0cb29fef..be67eb173046 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -39,6 +39,18 @@ xo_board_clk: xo-board-clk { }; }; + dp-dsi0-connector { + compatible = "dp-connector"; + label = "DSI0"; + type = "mini"; + + port { + dp_dsi0_connector_in: endpoint { + remote-endpoint = <&dsi2dp_bridge_out>; + }; + }; + }; + vreg_conn_1p8: regulator-conn-1p8 { compatible = "regulator-fixed"; regulator-name = "vreg_conn_1p8"; @@ -65,6 +77,64 @@ regulator-usb2-vbus { regulator-always-on; }; + vreg_12p0: regulator-vreg-12p0 { + compatible = "regulator-fixed"; + regulator-name = "VREG_12P0"; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vreg_1p0: regulator-vreg-1p0 { + compatible = "regulator-fixed"; + regulator-name = "VREG_1P0"; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + vin-supply = <&vreg_1p8>; + }; + + vreg_1p8: regulator-vreg-1p8 { + compatible = "regulator-fixed"; + regulator-name = "VREG_1P8"; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + vin-supply = <&vreg_5p0>; + }; + + vreg_3p0: regulator-vreg-3p0 { + compatible = "regulator-fixed"; + regulator-name = "VREG_3P0"; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + vin-supply = <&vreg_12p0>; + }; + + vreg_5p0: regulator-vreg-5p0 { + compatible = "regulator-fixed"; + regulator-name = "VREG_5P0"; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + vin-supply = <&vreg_12p0>; + }; + wcn6855-pmu { compatible = "qcom,wcn6855-pmu"; @@ -288,6 +358,86 @@ vreg_l17a: ldo17 { }; }; +&i2c2 { + clock-frequency = <400000>; + status = "okay"; + + io_expander: pinctrl@3e { + compatible = "semtech,sx1509q"; + reg = <0x3e>; + interrupts-extended = <&tlmm 58 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + semtech,probe-reset; + }; + + i2c-mux@77 { + compatible = "nxp,pca9542"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + bridge@58 { + compatible = "analogix,anx7625"; + reg = <0x58>; + interrupts-extended = <&io_expander 0 IRQ_TYPE_EDGE_FALLING>; + enable-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>; + vdd10-supply = <&vreg_1p0>; + vdd18-supply = <&vreg_1p8>; + vdd33-supply = <&vreg_3p0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi2dp_bridge_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + dsi2dp_bridge_out: endpoint { + remote-endpoint = <&dp_dsi0_connector_in>; + }; + }; + }; + }; + }; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l11a>; + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <&dsi2dp_bridge_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vcca-supply = <&vreg_l5a>; + status = "okay"; +}; + &pcie { perst-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; From f85592223d5bf983b6c495f33cfa0344a9930d5b Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 28 Oct 2025 23:00:00 +0200 Subject: [PATCH 113/138] arm64: dts: qcom: sdm670: create common zap-shader node In order to reduce duplication, move common GPU memory configuration from individual board files to sdm670.dtsi. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: David Heidelberg Link: https://lore.kernel.org/r/20251028-dt-zap-shader-v1-1-7eccb823b986@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts | 1 - arch/arm64/boot/dts/qcom/sdm670.dtsi | 4 ++++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts index d01422844fbf..760f21f19ca4 100644 --- a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts +++ b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts @@ -406,7 +406,6 @@ &gpu { status = "okay"; zap-shader { - memory-region = <&gpu_mem>; firmware-name = "qcom/sdm670/sargo/a615_zap.mbn"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index c3264a31bccf..57a3ffedc432 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -1382,6 +1382,10 @@ gpu: gpu@5000000 { status = "disabled"; + zap-shader { + memory-region = <&gpu_mem>; + }; + gpu_opp_table: opp-table { compatible = "operating-points-v2"; From 8464b804bd35cf4068e3a7cd19163c0f8a063852 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 28 Oct 2025 23:00:01 +0200 Subject: [PATCH 114/138] arm64: dts: qcom: sdm845: create common zap-shader node In order to reduce duplication, move common GPU memory configuration from individual board files to sdm845.dtsi. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: David Heidelberg Link: https://lore.kernel.org/r/20251028-dt-zap-shader-v1-2-7eccb823b986@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 1 - arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi | 4 ---- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 1 - arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 1 - arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts | 1 - arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts | 1 - arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi | 1 - arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi | 1 - arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts | 1 - arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++++ arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts | 1 - arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 1 - 12 files changed, 4 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 8abf3e909502..662722adf20b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -456,7 +456,6 @@ &gpi_dma1 { &gpu { status = "okay"; zap-shader { - memory-region = <&gpu_mem>; firmware-name = "qcom/sdm845/a630_zap.mbn"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi index 83b98bad19dd..0ee2f4b99fbd 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi @@ -456,10 +456,6 @@ &gcc { &gpu { status = "okay"; - - zap-shader { - memory-region = <&gpu_mem>; - }; }; &ipa { diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index 63d2993536ad..971bdb9c3693 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -418,7 +418,6 @@ &gpu { status = "okay"; zap-shader { - memory-region = <&gpu_mem>; firmware-name = "qcom/sdm845/a630_zap.mbn"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index eb708ebdb020..3fe71adf1dbb 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -341,7 +341,6 @@ &gpu { status = "okay"; zap-shader { - memory-region = <&gpu_mem>; firmware-name = "qcom/sdm845/oneplus6/a630_zap.mbn"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts index 493c69e99174..45e9dda007ce 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts @@ -253,7 +253,6 @@ &gpu { status = "okay"; zap-shader { - memory-region = <&gpu_mem>; firmware-name = "qcom/sdm845/starqltechn/a630_zap.mbn"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index f0ae0159f32a..238471267e1f 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -425,7 +425,6 @@ &gpu { status = "okay"; zap-shader { - memory-region = <&gpu_mem>; firmware-name = "qcom/sdm845/axolotl/a630_zap.mbn"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi index f3f4c0900572..f3ff0b3352bc 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -428,7 +428,6 @@ &gpu { status = "okay"; zap-shader { - memory-region = <&gpu_mem>; firmware-name = "qcom/sdm845/Sony/tama/a630_zap.mbn"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index 7480c8d7ac5b..5b30ace99579 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -248,7 +248,6 @@ &gpu { status = "okay"; zap-shader { - memory-region = <&gpu_mem>; firmware-name = "qcom/sdm845/beryllium/a630_zap.mbn"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts index 1c50a0563bc4..26f090051316 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts @@ -394,7 +394,6 @@ &gpu { status = "okay"; zap-shader { - memory-region = <&gpu_mem>; firmware-name = "qcom/sdm845/polaris/a630_zap.mbn"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 1c3a7371a2d3..8c90f652afff 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4902,6 +4902,10 @@ gpu: gpu@5000000 { status = "disabled"; + zap-shader { + memory-region = <&gpu_mem>; + }; + gpu_opp_table: opp-table { compatible = "operating-points-v2"; diff --git a/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts b/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts index 117cc0133363..57afb3577005 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts @@ -490,7 +490,6 @@ &gpu { status = "okay"; zap-shader { - memory-region = <&gpu_mem>; firmware-name = "qcom/sdm850/HUAWEI/AL09/qcdxkmsuc850.mbn"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 90efbb7e3799..35121cbcd37b 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -358,7 +358,6 @@ &gcc { &gpu { status = "okay"; zap-shader { - memory-region = <&gpu_mem>; firmware-name = "qcom/sdm850/LENOVO/81JL/qcdxkmsuc850.mbn"; }; }; From e3f81bdd46dc4120e9ee373aa8794b84c7dfd2f1 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 28 Oct 2025 23:00:02 +0200 Subject: [PATCH 115/138] arm64: dts: qcom: sc8180x: create common zap-shader node In order to reduce duplication, move common GPU memory configuration from individual board files to sc8180x.dtsi. Signed-off-by: Dmitry Baryshkov Reviewed-by: David Heidelberg Link: https://lore.kernel.org/r/20251028-dt-zap-shader-v1-3-7eccb823b986@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 6 ------ arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 3 ++- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 9 +++++++++ 3 files changed, 11 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index 08d0784d0cbb..625a155a584a 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -151,11 +151,6 @@ adsp_mem: adsp-region@90800000 { no-map; }; - gpu_mem: gpu-region@98715000 { - reg = <0x0 0x98715000 0x0 0x2000>; - no-map; - }; - cdsp_mem: cdsp-region@98900000 { reg = <0x0 0x98900000 0x0 0x1400000>; no-map; @@ -357,7 +352,6 @@ &gpu { status = "okay"; zap-shader { - memory-region = <&gpu_mem>; firmware-name = "qcom/sc8180x/LENOVO/82AK/qcdxkmsuc8180.mbn"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts index 93de9fe918eb..069953dcad37 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts @@ -14,6 +14,8 @@ #include "sc8180x.dtsi" #include "sc8180x-pmics.dtsi" +/delete-node/ &gpu_mem; + / { model = "Qualcomm SC8180x Primus"; compatible = "qcom,sc8180x-primus", "qcom,sc8180x"; @@ -444,7 +446,6 @@ &gpu { status = "okay"; zap-shader { - memory-region = <&gpu_mem>; firmware-name = "qcom/sc8180x/qcdxkmsuc8180.mbn"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index e3143a4a41c9..42ab76d52ae2 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -646,6 +646,11 @@ reserved@89b00000 { no-map; }; + gpu_mem: memory@98715000 { + reg = <0x0 0x98715000 0x0 0x2000>; + no-map; + }; + reserved@9d400000 { reg = <0x0 0x9d400000 0x0 0x1000000>; no-map; @@ -2274,6 +2279,10 @@ gpu: gpu@2c00000 { status = "disabled"; + zap-shader { + memory-region = <&gpu_mem>; + }; + gpu_opp_table: opp-table { compatible = "operating-points-v2"; From 6e9612ced0c90fc19d9b27508f84ebcf5718b8a2 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 28 Oct 2025 23:00:03 +0200 Subject: [PATCH 116/138] arm64: dts: qcom: sc8280xp: create common zap-shader node In order to reduce duplication, mMove common GPU memory configuration from individual board files to sc8280xp.dtsi. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: David Heidelberg Link: https://lore.kernel.org/r/20251028-dt-zap-shader-v1-4-7eccb823b986@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 8 -------- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 6 ------ arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts | 6 ------ .../boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 6 ------ arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts | 6 ------ .../arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts | 6 ------ arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 9 +++++++++ 7 files changed, 9 insertions(+), 38 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index 64e59299672c..524d44cbae74 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -149,13 +149,6 @@ regulator-usb5-vbus { enable-active-high; regulator-always-on; }; - - reserved-memory { - gpu_mem: gpu-mem@8bf00000 { - reg = <0 0x8bf00000 0 0x2000>; - no-map; - }; - }; }; &apps_rsc { @@ -347,7 +340,6 @@ &gpu { status = "okay"; zap-shader { - memory-region = <&gpu_mem>; firmware-name = "qcom/sa8295p/a690_zap.mbn"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index 490e970c54a2..858f71737d93 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -225,11 +225,6 @@ vreg_wwan: regulator-wwan { }; reserved-memory { - gpu_mem: gpu-mem@8bf00000 { - reg = <0 0x8bf00000 0 0x2000>; - no-map; - }; - linux,cma { compatible = "shared-dma-pool"; size = <0x0 0x8000000>; @@ -511,7 +506,6 @@ &gpu { status = "okay"; zap-shader { - memory-region = <&gpu_mem>; firmware-name = "qcom/sc8280xp/qcdxkmsuc8280.mbn"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts index 0374251d3329..69d0d6c12e58 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts @@ -158,11 +158,6 @@ vreg_wlan: regulator-wlan { }; reserved-memory { - gpu_mem: gpu-mem@8bf00000 { - reg = <0 0x8bf00000 0 0x2000>; - no-map; - }; - linux,cma { compatible = "shared-dma-pool"; size = <0x0 0x8000000>; @@ -602,7 +597,6 @@ &gpu { status = "okay"; zap-shader { - memory-region = <&gpu_mem>; firmware-name = "qcom/sc8280xp/HUAWEI/gaokun3/qcdxkmsuc8280.mbn"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 3b3f7137689a..197ac4f4f0b6 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -280,11 +280,6 @@ vreg_wwan: regulator-wwan { }; reserved-memory { - gpu_mem: gpu-mem@8bf00000 { - reg = <0 0x8bf00000 0 0x2000>; - no-map; - }; - linux,cma { compatible = "shared-dma-pool"; size = <0x0 0x8000000>; @@ -724,7 +719,6 @@ &gpu { status = "okay"; zap-shader { - memory-region = <&gpu_mem>; firmware-name = "qcom/sc8280xp/LENOVO/21BX/qcdxkmsuc8280.mbn"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts index aeed3ef152eb..ea50e370f698 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts @@ -186,11 +186,6 @@ vreg_wwan: regulator-wwan { }; reserved-memory { - gpu_mem: gpu-mem@8bf00000 { - reg = <0 0x8bf00000 0 0x2000>; - no-map; - }; - linux,cma { compatible = "shared-dma-pool"; size = <0x0 0x8000000>; @@ -464,7 +459,6 @@ &gpu { status = "okay"; zap-shader { - memory-region = <&gpu_mem>; firmware-name = "qcom/sc8280xp/MICROSOFT/SurfacePro9/qcdxkmsuc8280.mbn"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts index a40dccd70dfd..48b60f6186fc 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts @@ -227,11 +227,6 @@ vreg_wwan: regulator-wwan { }; reserved-memory { - gpu_mem: gpu-mem@8bf00000 { - reg = <0 0x8bf00000 0 0x2000>; - no-map; - }; - linux,cma { compatible = "shared-dma-pool"; size = <0x0 0x8000000>; @@ -581,7 +576,6 @@ &gpu { status = "okay"; zap-shader { - memory-region = <&gpu_mem>; firmware-name = "qcom/sc8280xp/microsoft/blackrock/qcdxkmsuc8280.mbn"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 7b89d3d422ea..b7044b9d656e 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -691,6 +691,11 @@ reserved-region@85b00000 { no-map; }; + pil_gpu_mem: gpu-mem@8bf00000 { + reg = <0 0x8bf00000 0 0x2000>; + no-map; + }; + pil_adsp_mem: adsp-region@86c00000 { reg = <0 0x86c00000 0 0x2000000>; no-map; @@ -3366,6 +3371,10 @@ gpu: gpu@3d00000 { status = "disabled"; + zap-shader { + memory-region = <&pil_gpu_mem>; + }; + gpu_opp_table: opp-table { compatible = "operating-points-v2"; From 00d3f7b0536dec3b5660e25d0767f61ee38941a7 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 28 Oct 2025 23:00:04 +0200 Subject: [PATCH 117/138] arm64: dts: qcom: sm8250: drop duplicate memory-region defs The base file, sm8250.dtsi, alread includes memory-region under the GPU's zap-shader node. Drop duplicates from the individual board files. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: David Heidelberg Link: https://lore.kernel.org/r/20251028-dt-zap-shader-v1-5-7eccb823b986@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 1 - arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 1 - arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi | 1 - arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts | 1 - 4 files changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index d99448a0732d..964e33b6e74a 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -596,7 +596,6 @@ &gpu { status = "okay"; zap-shader { - memory-region = <&gpu_mem>; firmware-name = "qcom/sm8250/a650_zap.mbn"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index 7f592bd30248..5c40d4e869d3 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -486,7 +486,6 @@ &gpu { status = "okay"; zap-shader { - memory-region = <&gpu_mem>; firmware-name = "qcom/sm8250/a650_zap.mbn"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi index 465fd6e954a3..6c9bb993dc2a 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi @@ -556,7 +556,6 @@ &gpu { status = "okay"; zap-shader { - memory-region = <&gpu_mem>; firmware-name = "qcom/sm8250/xiaomi/elish/a650_zap.mbn"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts index 4ad24974c09f..12565ad87890 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts @@ -426,7 +426,6 @@ &gpu { status = "okay"; zap-shader { - memory-region = <&gpu_mem>; firmware-name = "qcom/sm8250/xiaomi/pipa/a650_zap.mbn"; }; }; From d994ae0427a83087bedcfbb8afabe620529ef594 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 28 Oct 2025 23:00:05 +0200 Subject: [PATCH 118/138] arm64: dts: qcom: sc7180: add gpu_zap_shader label Patching existing DT nodes based on full path is error prone and generally not recommended. Add a generic zap-shader subnode to the GPU node on SC7180, delete it on trogdor and IDP, two platforms which don't use ZAP and patch it with the firmware-name on all other platforms by using the label. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: David Heidelberg Link: https://lore.kernel.org/r/20251028-dt-zap-shader-v1-6-7eccb823b986@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts | 9 ++++----- arch/arm64/boot/dts/qcom/sc7180-el2.dtso | 6 ++---- arch/arm64/boot/dts/qcom/sc7180-idp.dts | 1 + arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 1 + arch/arm64/boot/dts/qcom/sc7180.dtsi | 4 ++++ 5 files changed, 12 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts index ad342d8b7508..1514da636269 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts @@ -31,7 +31,7 @@ chosen { }; reserved-memory { - zap_mem: zap-shader@80840000 { + gpu_mem: zap-shader@80840000 { reg = <0x0 0x80840000 0 0x2000>; no-map; }; @@ -426,11 +426,10 @@ panel_in_edp: endpoint { &gpu { status = "okay"; +}; - zap-shader { - memory-region = <&zap_mem>; - firmware-name = "qcom/sc7180/acer/aspire1/qcdxkmsuc7180.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sc7180/acer/aspire1/qcdxkmsuc7180.mbn"; }; &mdss { diff --git a/arch/arm64/boot/dts/qcom/sc7180-el2.dtso b/arch/arm64/boot/dts/qcom/sc7180-el2.dtso index 49a98676ca4d..6e8da59597b6 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-el2.dtso +++ b/arch/arm64/boot/dts/qcom/sc7180-el2.dtso @@ -8,10 +8,8 @@ /plugin/; /* We can't and don't need to use zap shader in EL2 as linux can zap the gpu on it's own. */ -&gpu { - zap-shader { - status = "disabled"; - }; +&gpu_zap_shader { + status = "disabled"; }; /* Venus can be used in EL2 if booted similarly to ChromeOS devices. */ diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index 19cf419cf531..0bce3eefca2e 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -39,6 +39,7 @@ chosen { * */ +/delete-node/ &gpu_zap_shader; /delete-node/ &hyp_mem; /delete-node/ &xbl_mem; /delete-node/ &aop_mem; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 74ab321d3333..b398f69917f0 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -41,6 +41,7 @@ charger-crit { * required by the board dts. */ +/delete-node/ &gpu_zap_shader; /delete-node/ &hyp_mem; /delete-node/ &ipa_fw_mem; /delete-node/ &xbl_mem; diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index a47182994c56..45b9864e3304 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2185,6 +2185,10 @@ gpu: gpu@5000000 { interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "gfx-mem"; + gpu_zap_shader: zap-shader { + memory-region = <&gpu_mem>; + }; + gpu_opp_table: opp-table { compatible = "operating-points-v2"; From 2377626fd216ebdf17294ac0cabc27614fff07d1 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 28 Oct 2025 23:00:06 +0200 Subject: [PATCH 119/138] arm64: dts: qcom: add gpu_zap_shader label Patching existing DT nodes based on full path is error prone and generally not recommended. Follow the pattern introduced in the last platforms, add gpu_zap_shader label to the ZAP node and use it in the board files. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: David Heidelberg Link: https://lore.kernel.org/r/20251028-dt-zap-shader-v1-7-7eccb823b986@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 6 +++--- arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts | 6 +++--- arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts | 6 +++--- arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts | 6 ++---- arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts | 6 ++---- arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-scorpio.dts | 6 ++---- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 2 +- arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 6 +++--- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 6 +++--- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 6 +++--- arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 6 +++--- arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 6 +++--- arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 6 +++--- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 6 +++--- arch/arm64/boot/dts/qcom/sc8280xp-el2.dtso | 6 ++---- arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts | 6 +++--- .../arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 6 +++--- arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts | 6 +++--- arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts | 6 +++--- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts | 6 +++--- arch/arm64/boot/dts/qcom/sdm670.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 7 ++++--- arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts | 6 ++---- arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts | 6 ++---- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 6 +++--- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts | 6 +++--- arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts | 6 +++--- arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi | 6 +++--- .../boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts | 6 +++--- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- .../arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts | 6 +++--- arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts | 6 +++--- arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts | 6 +++--- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 6 +++--- arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts | 6 +++--- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 6 +++--- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 6 +++--- arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 6 +++--- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 6 +++--- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 6 +++--- arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 6 +++--- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 6 +++--- arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +- arch/arm64/boot/dts/qcom/x1e001de-devkit.dts | 6 +++--- .../boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts | 6 +++--- arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts | 6 +++--- .../boot/dts/qcom/x1e80100-hp-elitebook-ultra-g1q.dts | 6 ++---- arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts | 6 +++--- arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 6 +++--- 64 files changed, 162 insertions(+), 175 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index 99658b0bca84..9fa70ff6887b 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -201,10 +201,10 @@ &camss { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/apq8096/a530_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/apq8096/a530_zap.mbn"; }; &hsusb_phy1 { diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts b/arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts index 220eeb31fdc7..0bb9e3d8f714 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts @@ -27,10 +27,10 @@ &battery { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/msm8996/oneplus3/a530_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/msm8996/oneplus3/a530_zap.mbn"; }; &mss_pil { diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts b/arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts index f772618e80c7..1d7b27c5aff6 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts @@ -28,10 +28,10 @@ &battery { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/msm8996/oneplus3t/a530_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/msm8996/oneplus3t/a530_zap.mbn"; }; &mss_pil { diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts index bd3f39e1b98f..3c6a40212a8d 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts @@ -91,10 +91,8 @@ synaptics@20 { }; -&gpu { - zap-shader { - firmware-name = "qcom/msm8996/gemini/a530_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/msm8996/gemini/a530_zap.mbn"; }; &mdss_dsi0 { diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index c75b522f6eba..b341dec27193 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1333,7 +1333,7 @@ opp-133000000 { }; }; - zap-shader { + gpu_zap_shader: zap-shader { memory-region = <&gpu_mem>; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts index 443599a5a5dd..f8ab03f106a1 100644 --- a/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts +++ b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts @@ -39,10 +39,8 @@ touchscreen@20 { }; }; -&gpu { - zap-shader { - firmware-name = "qcom/msm8996/natrium/a530_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/msm8996/natrium/a530_zap.mbn"; }; &mdss_dsi0 { diff --git a/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-scorpio.dts b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-scorpio.dts index 33d84ac541e1..1cc33c3123a4 100644 --- a/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-scorpio.dts +++ b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-scorpio.dts @@ -91,10 +91,8 @@ touchscreen: atmel-mxt-ts@4a { }; }; -&gpu { - zap-shader { - firmware-name = "qcom/msm8996/scorpio/a530_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/msm8996/scorpio/a530_zap.mbn"; }; &mdp_smmu { diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index c6544ffa6f32..b909306b3f12 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -1625,7 +1625,7 @@ gpu: gpu@5900000 { status = "disabled"; - zap-shader { + gpu_zap_shader: zap-shader { memory-region = <&pil_gpu_mem>; }; diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts index 43af25d17aa8..5cbbdae497d8 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -261,10 +261,10 @@ &gpi_dma0 { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/qcm2290/a702_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/qcm2290/a702_zap.mbn"; }; &i2c2_gpio { diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index bdf2d66e40c6..0cd36c54632f 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -245,10 +245,10 @@ &gpi_dma0 { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/qrb4210/a610_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/qrb4210/a610_zap.mbn"; }; &i2c2_gpio { diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 964e33b6e74a..71b42e76f03d 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -594,10 +594,10 @@ &gmu { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sm8250/a650_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sm8250/a650_zap.mbn"; }; /* LS-I2C0 */ diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index 524d44cbae74..d28d69162427 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -338,10 +338,10 @@ &gmu { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sa8295p/a690_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sa8295p/a690_zap.mbn"; }; &gpu_smmu { diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index 625a155a584a..d86a31ddede2 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -350,10 +350,10 @@ vreg_l16e_3p0: ldo16 { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sc8180x/LENOVO/82AK/qcdxkmsuc8180.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sc8180x/LENOVO/82AK/qcdxkmsuc8180.mbn"; }; &i2c1 { diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts index 069953dcad37..aff398390eba 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts @@ -444,10 +444,10 @@ vreg_l16e_3p0: ldo16 { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sc8180x/qcdxkmsuc8180.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sc8180x/qcdxkmsuc8180.mbn"; }; &i2c1 { diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 42ab76d52ae2..8319d892c6e4 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -2279,7 +2279,7 @@ gpu: gpu@2c00000 { status = "disabled"; - zap-shader { + gpu_zap_shader: zap-shader { memory-region = <&gpu_mem>; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index 858f71737d93..c53e00cae465 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -504,10 +504,10 @@ &gpi_dma2 { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sc8280xp/qcdxkmsuc8280.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sc8280xp/qcdxkmsuc8280.mbn"; }; &mdss0 { diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-el2.dtso b/arch/arm64/boot/dts/qcom/sc8280xp-el2.dtso index 25d1fa4bc205..cff3735a12dd 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-el2.dtso +++ b/arch/arm64/boot/dts/qcom/sc8280xp-el2.dtso @@ -8,10 +8,8 @@ /plugin/; /* We can't and don't need to use zap shader in EL2 as linux can zap the gpu on it's own. */ -&gpu { - zap-shader { - status = "disabled"; - }; +&gpu_zap_shader { + status = "disabled"; }; /* diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts index 69d0d6c12e58..9819454abe13 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts @@ -595,10 +595,10 @@ &gpi_dma2 { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sc8280xp/HUAWEI/gaokun3/qcdxkmsuc8280.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sc8280xp/HUAWEI/gaokun3/qcdxkmsuc8280.mbn"; }; &i2c4 { diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 197ac4f4f0b6..d84ca010ab9d 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -717,10 +717,10 @@ &gpi_dma2 { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sc8280xp/LENOVO/21BX/qcdxkmsuc8280.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sc8280xp/LENOVO/21BX/qcdxkmsuc8280.mbn"; }; &mdss0 { diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts index ea50e370f698..f2b4470d4407 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts @@ -457,10 +457,10 @@ &gpi_dma2 { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sc8280xp/MICROSOFT/SurfacePro9/qcdxkmsuc8280.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sc8280xp/MICROSOFT/SurfacePro9/qcdxkmsuc8280.mbn"; }; &mdss0 { diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts index 48b60f6186fc..00bbeeef6f14 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts @@ -574,10 +574,10 @@ &gpi_dma2 { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sc8280xp/microsoft/blackrock/qcdxkmsuc8280.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sc8280xp/microsoft/blackrock/qcdxkmsuc8280.mbn"; }; &mdss0 { diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index b7044b9d656e..5334adebf278 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -3371,7 +3371,7 @@ gpu: gpu@3d00000 { status = "disabled"; - zap-shader { + gpu_zap_shader: zap-shader { memory-region = <&pil_gpu_mem>; }; diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts index 760f21f19ca4..ed55646ca419 100644 --- a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts +++ b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts @@ -404,10 +404,10 @@ &gpi_dma1 { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sdm670/sargo/a615_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sdm670/sargo/a615_zap.mbn"; }; &i2c9 { diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index 57a3ffedc432..b8a8dcbdfbe3 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -1382,7 +1382,7 @@ gpu: gpu@5000000 { status = "disabled"; - zap-shader { + gpu_zap_shader: zap-shader { memory-region = <&gpu_mem>; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 662722adf20b..ce23f87e0316 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -455,9 +455,10 @@ &gpi_dma1 { &gpu { status = "okay"; - zap-shader { - firmware-name = "qcom/sdm845/a630_zap.mbn"; - }; +}; + +&gpu_zap_shader { + firmware-name = "qcom/sdm845/a630_zap.mbn"; }; &i2c10 { diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts b/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts index a12723310c8b..09bfcef42402 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts @@ -47,10 +47,8 @@ &cdsp_pas { firmware-name = "qcom/sdm845/judyln/cdsp.mbn"; }; -&gpu { - zap-shader { - firmware-name = "qcom/sdm845/judyln/a630_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sdm845/judyln/a630_zap.mbn"; }; &mss_pil { diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts b/arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts index d17d4d4d5609..ffe1da2227f0 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts @@ -33,10 +33,8 @@ &cdsp_pas { firmware-name = "qcom/sdm845/judyp/cdsp.mbn"; }; -&gpu { - zap-shader { - firmware-name = "qcom/sdm845/judyp/a630_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sdm845/judyp/a630_zap.mbn"; }; &mss_pil { diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index 971bdb9c3693..091568642faa 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -416,10 +416,10 @@ &gcc { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sdm845/a630_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sdm845/a630_zap.mbn"; }; &i2c10 { diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 3fe71adf1dbb..fd7fdc1f0749 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -339,10 +339,10 @@ &gcc { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sdm845/oneplus6/a630_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sdm845/oneplus6/a630_zap.mbn"; }; &i2c10 { diff --git a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts index 45e9dda007ce..5d41a92cfebf 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts @@ -251,10 +251,10 @@ vib_pwm: pwm { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sdm845/starqltechn/a630_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sdm845/starqltechn/a630_zap.mbn"; }; &mdss { diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index 238471267e1f..ddc2b3ca3bc5 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -423,10 +423,10 @@ &gcc { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sdm845/axolotl/a630_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sdm845/axolotl/a630_zap.mbn"; }; &i2c5 { diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi index f3ff0b3352bc..7dc9349eedfd 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -426,10 +426,10 @@ &gpi_dma1 { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sdm845/Sony/tama/a630_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sdm845/Sony/tama/a630_zap.mbn"; }; &i2c5 { diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index 5b30ace99579..785006a15e97 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -246,10 +246,10 @@ &gpi_dma1 { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sdm845/beryllium/a630_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sdm845/beryllium/a630_zap.mbn"; }; &ibb { diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts index 26f090051316..30e88ff010a3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts @@ -392,10 +392,10 @@ &gpi_dma1 { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sdm845/polaris/a630_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sdm845/polaris/a630_zap.mbn"; }; &ibb { diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 8c90f652afff..bf2f9c04adba 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4902,7 +4902,7 @@ gpu: gpu@5000000 { status = "disabled"; - zap-shader { + gpu_zap_shader: zap-shader { memory-region = <&gpu_mem>; }; diff --git a/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts b/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts index 57afb3577005..0ef9ea38a424 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts @@ -488,10 +488,10 @@ &gcc { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sdm850/HUAWEI/AL09/qcdxkmsuc850.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sdm850/HUAWEI/AL09/qcdxkmsuc850.mbn"; }; &i2c5 { diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 35121cbcd37b..e41200839dbe 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -356,10 +356,10 @@ &gcc { }; &gpu { - status = "okay"; - zap-shader { - firmware-name = "qcom/sdm850/LENOVO/81JL/qcdxkmsuc850.mbn"; - }; + status = "okay";}; + +&gpu_zap_shader { + firmware-name = "qcom/sdm850/LENOVO/81JL/qcdxkmsuc850.mbn"; }; &i2c1 { diff --git a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts index ad347ccd1975..466ad409e924 100644 --- a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts +++ b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts @@ -121,10 +121,10 @@ &gpi_dma0 { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sm6115/Fxtec/QX1050/a610_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sm6115/Fxtec/QX1050/a610_zap.mbn"; }; &i2c1 { diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 91fc36b59abf..5e2032c26ea3 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -1745,7 +1745,7 @@ gpu: gpu@5900000 { status = "disabled"; - zap-shader { + gpu_zap_shader: zap-shader { memory-region = <&pil_gpu_mem>; }; diff --git a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts index c17545111f49..be1f550fd7b5 100644 --- a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts +++ b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts @@ -67,10 +67,10 @@ ramoops@ffc00000 { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sm6115/LENOVO/J606F/a610_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sm6115/LENOVO/J606F/a610_zap.mbn"; }; &mdss { diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 1ea2beb9e2ea..e3ec99972a28 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -2255,7 +2255,7 @@ gpu: gpu@2c00000 { status = "disabled"; - zap-shader { + gpu_zap_shader: zap-shader { memory-region = <&gpu_mem>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index 5c40d4e869d3..51779b99176d 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -484,10 +484,10 @@ &gmu { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sm8250/a650_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sm8250/a650_zap.mbn"; }; &i2c1 { diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi index 6c9bb993dc2a..c017399297b9 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi @@ -554,10 +554,10 @@ &gpi_dma2 { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sm8250/xiaomi/elish/a650_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sm8250/xiaomi/elish/a650_zap.mbn"; }; &i2c0 { diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts index 12565ad87890..078ba13f8762 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts @@ -424,10 +424,10 @@ &gpi_dma2 { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sm8250/xiaomi/pipa/a650_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sm8250/xiaomi/pipa/a650_zap.mbn"; }; &i2c11 { diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index d30b3bc2db9e..c7dffa440074 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2944,7 +2944,7 @@ gpu: gpu@3d00000 { status = "disabled"; - zap-shader { + gpu_zap_shader: zap-shader { memory-region = <&gpu_mem>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 24a8c91e9f70..5f975d009465 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -403,10 +403,10 @@ &gpi_dma1 { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sm8350/a660_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sm8350/a660_zap.mbn"; }; &i2c13 { diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index fc4ce9d4977e..5c8fe213f5e4 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2051,7 +2051,7 @@ gpu: gpu@3d00000 { status = "disabled"; - zap-shader { + gpu_zap_shader: zap-shader { memory-region = <&pil_gpu_mem>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 0c6aa7ddf432..268ae0cd642a 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -643,10 +643,10 @@ vreg_l7e_2p8: ldo7 { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sm8450/a730_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sm8450/a730_zap.mbn"; }; &i2c9 { diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 2ae56c39f2e6..920a2d1c04d0 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2459,7 +2459,7 @@ gpu: gpu@3d00000 { status = "disabled"; - zap-shader { + gpu_zap_shader: zap-shader { memory-region = <&gpu_micro_code_mem>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts index b5d7f0cd443a..599850c48494 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -955,10 +955,10 @@ &gpi_dma1 { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sm8550/a740_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sm8550/a740_zap.mbn"; }; &lpass_tlmm { diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 38f2928f23cc..f430038bd402 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -642,10 +642,10 @@ vreg_l7n_2p96: ldo7 { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sm8550/a740_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sm8550/a740_zap.mbn"; }; &i2c_master_hub_0 { diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index 9af2a4fd02ea..05c98fe2c25b 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -835,10 +835,10 @@ &gpi_dma1 { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sm8550/a740_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sm8550/a740_zap.mbn"; }; &lpass_tlmm { diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 04e6db8f1030..2ca9e50ef599 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2491,7 +2491,7 @@ gpu: gpu@3d00000 { status = "disabled"; - zap-shader { + gpu_zap_shader: zap-shader { memory-region = <&gpu_micro_code_mem>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts index 87d7190dc991..5bf1af3308ce 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -900,10 +900,10 @@ &iris { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sm8650/gen70900_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sm8650/gen70900_zap.mbn"; }; &lpass_tlmm { diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index 9e790cf44804..b2feac61a89f 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -830,10 +830,10 @@ &iris { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sm8650/gen70900_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sm8650/gen70900_zap.mbn"; }; &lpass_tlmm { diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 1a323f4ebdd3..07ae74851621 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -4158,7 +4158,7 @@ gpu: gpu@3d00000 { status = "disabled"; - zap-shader { + gpu_zap_shader: zap-shader { memory-region = <&gpu_micro_code_mem>; }; diff --git a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts index 701f35af7d5c..a9643cd746d5 100644 --- a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts +++ b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts @@ -763,10 +763,10 @@ vreg_l3j_0p8: ldo3 { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/x1e80100/Thundercomm/DEVKIT/qcdxkmsuc8380.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/x1e80100/Thundercomm/DEVKIT/qcdxkmsuc8380.mbn"; }; &i2c1 { diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi index 169726984d3b..80ece9db875a 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi @@ -722,10 +722,10 @@ vreg_l3j_0p8: ldo3 { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/x1e80100/LENOVO/21N1/qcdxkmsuc8380.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/x1e80100/LENOVO/21N1/qcdxkmsuc8380.mbn"; }; &i2c0 { diff --git a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts index f2960953e608..d4df21de0d95 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts @@ -479,10 +479,10 @@ vreg_l3j_0p8: ldo3 { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/x1e80100/ASUSTeK/vivobook-s15/qcdxkmsuc8380.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/x1e80100/ASUSTeK/vivobook-s15/qcdxkmsuc8380.mbn"; }; &i2c0 { diff --git a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts index c1f49cba61fc..2f533e56c8c8 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts @@ -676,10 +676,10 @@ vreg_l3j_0p8: ldo3 { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/x1e80100/dell/xps13-9345/qcdxkmsuc8380.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/x1e80100/dell/xps13-9345/qcdxkmsuc8380.mbn"; }; &i2c0 { diff --git a/arch/arm64/boot/dts/qcom/x1e80100-hp-elitebook-ultra-g1q.dts b/arch/arm64/boot/dts/qcom/x1e80100-hp-elitebook-ultra-g1q.dts index 4ea00d823693..0b3b6cb23e1a 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-hp-elitebook-ultra-g1q.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-hp-elitebook-ultra-g1q.dts @@ -9,10 +9,8 @@ / { compatible = "hp,elitebook-ultra-g1q", "qcom,x1e80100"; }; -&gpu { - zap-shader { - firmware-name = "qcom/x1e80100/hp/elitebook-ultra-g1q/qcdxkmsuc8380.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/x1e80100/hp/elitebook-ultra-g1q/qcdxkmsuc8380.mbn"; }; &remoteproc_adsp { diff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts index 56e4d13cca11..4c31d14a07bc 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts @@ -799,10 +799,10 @@ vreg_l3j_0p8: ldo3 { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/x1e80100/LENOVO/83ED/qcdxkmsuc8380.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/x1e80100/LENOVO/83ED/qcdxkmsuc8380.mbn"; }; &i2c0 { diff --git a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi index 3b319f65dde1..7e1e808ea983 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi @@ -861,11 +861,11 @@ vreg_l3j: ldo3 { &gpu { status = "okay"; +}; - zap-shader { - memory-region = <&gpu_microcode_mem>; - firmware-name = "qcom/x1e80100/microsoft/qcdxkmsuc8380.mbn"; - }; +&gpu_zap_shader { + memory-region = <&gpu_microcode_mem>; + firmware-name = "qcom/x1e80100/microsoft/qcdxkmsuc8380.mbn"; }; &i2c0 { diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index 5a121fc44940..b742aabd9c04 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -831,10 +831,10 @@ vreg_l3j_0p8: ldo3 { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/x1e80100/gen70500_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/x1e80100/gen70500_zap.mbn"; }; &i2c5 { From 021df9dee9cd63eee1cfae1bb2381db11a1a45d7 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 30 Oct 2025 20:20:13 +0200 Subject: [PATCH 120/138] arm64: dts: qcom: rename qcm2290 to agatti QCM2290 and QRB2210 are two names for the same die, collectively known as 'agatti'. Follow the example of other platforms and rename QCM2290 to agatti.dtsi. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251030-rename-dts-2-v1-1-80c0b81c4d77@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/{qcm2290.dtsi => agatti.dtsi} | 0 arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 2 +- 2 files changed, 1 insertion(+), 1 deletion(-) rename arch/arm64/boot/dts/qcom/{qcm2290.dtsi => agatti.dtsi} (100%) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/agatti.dtsi similarity index 100% rename from arch/arm64/boot/dts/qcom/qcm2290.dtsi rename to arch/arm64/boot/dts/qcom/agatti.dtsi diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts index 5cbbdae497d8..e0e362b140ad 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -7,7 +7,7 @@ #include #include -#include "qcm2290.dtsi" +#include "agatti.dtsi" #include "pm4125.dtsi" / { From dd6edcd7d3e42b143a2f86e8d30ded62106a8972 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 30 Oct 2025 20:20:14 +0200 Subject: [PATCH 121/138] arm64: dts: qcom: rename sc7280 to kodiak SC7280, QCM6490 and QCS6490 are three names for the same die, collectively known as 'kodiak'. Follow the example of other platforms and rename SC7280 to kodiak.dtsi. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251030-rename-dts-2-v1-2-80c0b81c4d77@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/{sc7280.dtsi => kodiak.dtsi} | 0 arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 2 +- arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 2 +- arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts | 2 +- arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts | 2 +- arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 2 +- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 2 +- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm7325.dtsi | 2 +- 10 files changed, 10 insertions(+), 10 deletions(-) rename arch/arm64/boot/dts/qcom/{sc7280.dtsi => kodiak.dtsi} (100%) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi similarity index 100% rename from arch/arm64/boot/dts/qcom/sc7280.dtsi rename to arch/arm64/boot/dts/qcom/kodiak.dtsi diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index ea1d3acd975b..69726ab90f16 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -16,7 +16,7 @@ #include #include #include -#include "sc7280.dtsi" +#include "kodiak.dtsi" #include "pm7250b.dtsi" #include "pm7325.dtsi" #include "pm8350c.dtsi" /* PM7350C */ diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index 73fce639370c..089a027c57d5 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -13,7 +13,7 @@ #include #include #include -#include "sc7280.dtsi" +#include "kodiak.dtsi" #include "pm7250b.dtsi" #include "pm7325.dtsi" #include "pm8350c.dtsi" diff --git a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts index 251e72f11428..bf18c4852081 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts @@ -11,7 +11,7 @@ #include #include #include -#include "sc7280.dtsi" +#include "kodiak.dtsi" #include "pm8350c.dtsi" #include "pmk8350.dtsi" diff --git a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts index 7a6208bdd645..797f37596bf1 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts @@ -14,7 +14,7 @@ #include #include #include -#include "sc7280.dtsi" +#include "kodiak.dtsi" #include "pm7250b.dtsi" #include "pm7325.dtsi" #include "pm8350c.dtsi" /* PM7350C */ diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts index a63f79b0844c..bb5a42b038f1 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts @@ -14,7 +14,7 @@ #include #include #include -#include "sc7280.dtsi" +#include "kodiak.dtsi" #include "pm7250b.dtsi" #include "pm7325.dtsi" #include "pm8350c.dtsi" /* PM7350C */ diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 721a26d49cca..a36961d55e41 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -14,7 +14,7 @@ #include #include #include -#include "sc7280.dtsi" +#include "kodiak.dtsi" #include "pm7250b.dtsi" #include "pm7325.dtsi" #include "pm8350c.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index ccd39a1baeda..8cac4ce9c851 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -7,7 +7,7 @@ #include #include -#include "sc7280.dtsi" +#include "kodiak.dtsi" #include "pm7325.dtsi" #include "pm8350c.dtsi" #include "pmk8350.dtsi" @@ -573,7 +573,7 @@ bluetooth: bluetooth { }; }; -/* PINCTRL - additions to nodes defined in sc7280.dtsi */ +/* PINCTRL - additions to nodes defined in kodiak.dtsi */ &dp_hot_plug_det { bias-disable; diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi index 7d1d5bbbbbd9..469a5d103e3d 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -16,7 +16,7 @@ #include #include -#include "sc7280.dtsi" +#include "kodiak.dtsi" /* PMICs depend on spmi_bus label and so must come after SoC */ #include "pm7325.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sm7325.dtsi b/arch/arm64/boot/dts/qcom/sm7325.dtsi index 85d34b53e5e9..beb279956df6 100644 --- a/arch/arm64/boot/dts/qcom/sm7325.dtsi +++ b/arch/arm64/boot/dts/qcom/sm7325.dtsi @@ -4,7 +4,7 @@ * Copyright (c) 2024, Danila Tikhonov */ -#include "sc7280.dtsi" +#include "kodiak.dtsi" /* SM7325 uses Kryo 670 */ &cpu0 { compatible = "qcom,kryo670"; }; From ef659a5bd91bed7fae2c2a150f8ecca06599ac03 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 30 Oct 2025 20:20:15 +0200 Subject: [PATCH 122/138] arm64: dts: qcom: rename x1p42100 to purwa Follow the example of other platforms and rename X1P42100 to purwa.dtsi. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251030-rename-dts-2-v1-3-80c0b81c4d77@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/{x1p42100.dtsi => purwa.dtsi} | 0 arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi | 2 +- arch/arm64/boot/dts/qcom/x1p42100-crd.dts | 2 +- arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts | 2 +- arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts | 2 +- 5 files changed, 4 insertions(+), 4 deletions(-) rename arch/arm64/boot/dts/qcom/{x1p42100.dtsi => purwa.dtsi} (100%) diff --git a/arch/arm64/boot/dts/qcom/x1p42100.dtsi b/arch/arm64/boot/dts/qcom/purwa.dtsi similarity index 100% rename from arch/arm64/boot/dts/qcom/x1p42100.dtsi rename to arch/arm64/boot/dts/qcom/purwa.dtsi diff --git a/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi b/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi index 7ccb2076bab6..22470a97e1e3 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi +++ b/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi @@ -6,7 +6,7 @@ /dts-v1/; -#include "x1p42100.dtsi" +#include "purwa.dtsi" #include "x1-asus-zenbook-a14.dtsi" /delete-node/ &pmc8380_6; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts index cf999c2cf8d4..7ed4116b9590 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts @@ -5,7 +5,7 @@ /dts-v1/; -#include "x1p42100.dtsi" +#include "purwa.dtsi" #include "x1-crd.dtsi" /delete-node/ &pmc8380_6; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts b/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts index 47ab0c5b3034..0f338e457abd 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts +++ b/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts @@ -2,7 +2,7 @@ /dts-v1/; -#include "x1p42100.dtsi" +#include "purwa.dtsi" #include "hamoa-pmics.dtsi" #include "x1-hp-omnibook-x14.dtsi" /delete-node/ &pmc8380_6; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts index f7d372d2e961..3186e79e862d 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts +++ b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts @@ -13,7 +13,7 @@ #include #include -#include "x1p42100.dtsi" +#include "purwa.dtsi" #include "hamoa-pmics.dtsi" /delete-node/ &pmc8380_6; From 7a5bb9f60527fdc469e8fc53c537664fe0d481b0 Mon Sep 17 00:00:00 2001 From: Wesley Cheng Date: Sat, 1 Nov 2025 23:14:35 +0530 Subject: [PATCH 123/138] arm64: dts: qcom: sm8750: Add USB support to SM8750 SoCs SM8750 chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY (rev. v8) and M31 eUSB2 PHY. The major difference for SM8750 is the transition to using the M31 eUSB2 PHY compared to previous SoCs. Enable USB support on SM8750 MTP and QRD variants. SM8750 has a QMP combo PHY for the SSUSB path, and a M31 eUSB2 PHY for the HSUSB path. Signed-off-by: Wesley Cheng [Konrad: Provided diff to flattened USB node] Signed-off-by: Konrad Dybcio Signed-off-by: Krishna Kurapati Link: https://lore.kernel.org/r/20251101174437.1267998-2-krishna.kurapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 161 ++++++++++++++++++++++++++- 1 file changed, 160 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index a82d9867c7cb..3f0b57f428bb 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -635,7 +636,7 @@ gcc: clock-controller@100000 { <0>, <0>, <0>, - <0>; + <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; #clock-cells = <1>; #reset-cells = <1>; @@ -2581,6 +2582,164 @@ data-pins { }; }; + usb_hsphy: phy@88e3000 { + compatible = "qcom,sm8750-m31-eusb2-phy"; + reg = <0x0 0x88e3000 0x0 0x29c>; + + clocks = <&tcsrcc TCSR_USB2_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_dp_qmpphy: phy@88e8000 { + compatible = "qcom,sm8750-qmp-usb3-dp-phy"; + reg = <0x0 0x088e8000 0x0 0x4000>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&tcsrcc TCSR_USB3_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe"; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; + reset-names = "phy", + "common"; + + power-domains = <&gcc GCC_USB3_PHY_GDSC>; + + #clock-cells = <1>; + #phy-cells = <1>; + + orientation-switch; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dp_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_dp_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_dp_qmpphy_dp_in: endpoint { + }; + }; + }; + }; + + usb: usb@a600000 { + compatible = "qcom,sm8750-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a600000 0x0 0xfc100>; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, + <200000000>; + + interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dwc_usb3", + "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "usb-ddr", "apps-usb"; + + iommus = <&apps_smmu 0x40 0x0>; + + phys = <&usb_hsphy>, + <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + snps,hird-threshold = /bits/ 8 <0x0>; + snps,usb2-gadget-lpm-disable; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,usb2-lpm-disable; + snps,has-lpm-erratum; + tx-fifo-resize; + + dma-coherent; + usb-role-switch; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_dwc3_ss: endpoint { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; + }; + }; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8750-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; From 2340f29e2b06e24b44f5e8a4220d61605b3ea533 Mon Sep 17 00:00:00 2001 From: Wesley Cheng Date: Sat, 1 Nov 2025 23:14:36 +0530 Subject: [PATCH 124/138] arm64: dts: qcom: sm8750: Add USB support for SM8750 MTP platform Enable USB support on SM8750 MTP variant. Add the PMIC glink node with connector to enable role switch support. Signed-off-by: Wesley Cheng [Konrad: Provided diff to flatten USB node on MTP] Signed-off-by: Konrad Dybcio Co-developed-by: Jishnu Prakash Signed-off-by: Jishnu Prakash Signed-off-by: Krishna Kurapati Link: https://lore.kernel.org/r/20251101174437.1267998-3-krishna.kurapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 73 +++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts index 45b5f7581567..c8cb521b4c26 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts @@ -191,6 +191,51 @@ platform { }; }; + pmic-glink { + compatible = "qcom,sm8750-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 61 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + }; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; @@ -1200,3 +1245,31 @@ &ufs_mem_hc { status = "okay"; }; + +&usb { + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l3g_1p2>; + vdda-pll-supply = <&vreg_l2d_0p88>; + + status = "okay"; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_hsphy { + vdd-supply = <&vreg_l2d_0p88>; + vdda12-supply = <&vreg_l3g_1p2>; + + phys = <&pmih0108_eusb2_repeater>; + + status = "okay"; +}; From 530f824a4e1878c3d80dee070b831daa80a48634 Mon Sep 17 00:00:00 2001 From: Wesley Cheng Date: Sat, 1 Nov 2025 23:14:37 +0530 Subject: [PATCH 125/138] arm64: dts: qcom: sm8750: Add USB support for SM8750 QRD platform Enable USB support on SM8750 QRD variant. Add the PMIC glink node with connector to enable role switch support. Signed-off-by: Wesley Cheng [Konrad: Provided diff to flatten USB node on MTP] Signed-off-by: Konrad Dybcio Co-developed-by: Jishnu Prakash Signed-off-by: Jishnu Prakash Signed-off-by: Krishna Kurapati Link: https://lore.kernel.org/r/20251101174437.1267998-4-krishna.kurapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750-qrd.dts | 73 +++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts index 13c7b9664c89..b0cb61c5a603 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts @@ -193,6 +193,51 @@ platform { }; }; + pmic-glink { + compatible = "qcom,sm8750-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 61 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + }; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; @@ -1054,3 +1099,31 @@ &ufs_mem_hc { status = "okay"; }; + +&usb { + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l3g_1p2>; + vdda-pll-supply = <&vreg_l2d_0p88>; + + status = "okay"; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_hsphy { + vdd-supply = <&vreg_l2d_0p88>; + vdda12-supply = <&vreg_l3g_1p2>; + + phys = <&pmih0108_eusb2_repeater>; + + status = "okay"; +}; From 6678d5cf48deee17b903aed72f2e20924fe016d9 Mon Sep 17 00:00:00 2001 From: Griffin Kroah-Hartman Date: Thu, 16 Oct 2025 13:35:24 +0200 Subject: [PATCH 126/138] arm64: dts: qcom: qcm6490-fairphone-fp5: Enable CCI pull-up Enable vreg_l6p, which is the voltage source for the pull-up resistor of the CCI busses. This ensures that I2C communication works as expected. Reviewed-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Signed-off-by: Griffin Kroah-Hartman Link: https://lore.kernel.org/r/20251016-dw9800-driver-v3-3-d7058f72ead4@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index 69726ab90f16..c4efe35e393a 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -764,6 +764,8 @@ vreg_l6p: ldo6 { regulator-name = "vreg_l6p"; regulator-min-microvolt = <1700000>; regulator-max-microvolt = <1904000>; + /* Pull-up for CCI I2C busses */ + regulator-always-on; }; vreg_l7p: ldo7 { From 1cf6be79a865a15ac34c6dacc16205304bccfab1 Mon Sep 17 00:00:00 2001 From: Griffin Kroah-Hartman Date: Thu, 16 Oct 2025 13:35:25 +0200 Subject: [PATCH 127/138] arm64: dts: qcom: qcm6490-fairphone-fp5: Add UW cam actuator Add a node for the Dongwoon DW9800K actuator, used for focus of the ultra-wide camera sensor. Tested-by: Luca Weiss Reviewed-by: Konrad Dybcio Signed-off-by: Griffin Kroah-Hartman Link: https://lore.kernel.org/r/20251016-dw9800-driver-v3-4-d7058f72ead4@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index c4efe35e393a..455e5c9bb072 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -642,6 +642,15 @@ eeprom@50 { }; &cci0_i2c1 { + camera_imx858_dw9800k: actuator@e { + compatible = "dongwoon,dw9800k"; + reg = <0x0e>; + vdd-supply = <&vreg_afvdd_2p8>; + + dongwoon,sac-mode = <1>; + dongwoon,vcm-prescale = <16>; + }; + /* IMX858 @ 29 */ eeprom@54 { From 72a63169bf1100a64affde275ba90d7607f872c6 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Sun, 2 Nov 2025 11:22:20 -0600 Subject: [PATCH 128/138] arm64: dts: qcom: qcs6490-rb3gen2: Rename vph-pwr regulator node When fixed regulators are not named with "regulator-" prefix, they can not be neatly grouped and sorted together. Rename the vph-pwr-regulator, to facilitate the incoming addition of additional fixed regulators. Signed-off-by: Bjorn Andersson Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251102-rb3gen2-regulator-sort-v1-1-908879d240be@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index a36961d55e41..f29a352b0288 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -217,6 +217,13 @@ pmic_glink_sbu_in: endpoint { }; }; + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + thermal-zones { sdm-skin-thermal { thermal-sensors = <&pmk8350_adc_tm 3>; @@ -255,13 +262,6 @@ active-config0 { }; }; - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - }; - wcn6750-pmu { compatible = "qcom,wcn6750-pmu"; pinctrl-0 = <&bt_en>; From 69b8bbde238a1503ac45998a911ea56ddb7610cf Mon Sep 17 00:00:00 2001 From: Casey Connolly Date: Mon, 3 Nov 2025 12:45:50 +0100 Subject: [PATCH 129/138] arm64: dts: qcom: sdm845-oneplus: Update compatbible and add DDIC supplies Update the compatible to reflect combination of DDIC and panel. Original compatible describing only the DDIC used, but omit describing the panel used (Samsung AMS641RW), which we have no way to detect. There are two additional supplies used by the panel, both are GPIO controlled and are left enabled by the bootloader for continuous splash. Previously these were (incorrectly) modelled as pinctrl. Describe them properly so that the panel can control them. Fixes: 288ef8a42612 ("arm64: dts: sdm845: add oneplus6/6t devices") Signed-off-by: Casey Connolly Reviewed-by: Dmitry Baryshkov Co-developed-by: David Heidelberg Signed-off-by: David Heidelberg Link: https://lore.kernel.org/r/20251103-s6e3fc2x01-v6-1-d4eb4abaefa4@ixit.cz Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm845-oneplus-common.dtsi | 46 ++++++++++++++++++- .../boot/dts/qcom/sdm845-oneplus-fajita.dts | 2 +- 2 files changed, 46 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index fd7fdc1f0749..d619b710c63f 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -150,6 +150,34 @@ ts_1p8_supply: ts-1p8-regulator { enable-active-high; regulator-boot-on; }; + + panel_vci_3v3: panel-vci-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "LCD_VCI_3V"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 26 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-0 = <&panel_vci_default>; + pinctrl-names = "default"; + regulator-boot-on; + }; + + panel_vddi_poc_1p8: panel-vddi-poc-regulator { + compatible = "regulator-fixed"; + regulator-name = "VDDI_POC"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 25 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-0 = <&panel_poc_default>; + pinctrl-names = "default"; + regulator-boot-on; + }; }; &adsp_pas { @@ -416,6 +444,8 @@ display_panel: panel@0 { reg = <0>; vddio-supply = <&vreg_l14a_1p88>; + vci-supply = <&panel_vci_3v3>; + poc-supply = <&panel_vddi_poc_1p8>; reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; @@ -790,6 +820,20 @@ hall_sensor_default: hall-sensor-default-state { bias-disable; }; + panel_vci_default: vci-state { + pins = "gpio26"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + panel_poc_default: poc-state { + pins = "gpio25"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + alert_slider_default: alert-slider-default-state { pins = "gpio126", "gpio52", "gpio24"; function = "gpio"; @@ -805,7 +849,7 @@ ts_default_pins: ts-int-state { }; panel_reset_pins: panel-reset-state { - pins = "gpio6", "gpio25", "gpio26"; + pins = "gpio6"; function = "gpio"; drive-strength = <8>; bias-disable; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts index 7e75decfda05..d6cd873aef0d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts @@ -32,7 +32,7 @@ battery: battery { &display_panel { status = "okay"; - compatible = "samsung,s6e3fc2x01"; + compatible = "samsung,s6e3fc2x01-ams641rw", "samsung,s6e3fc2x01"; }; &i2c4 { From 6c55c3c261ed7c17fa7823daf4d8f716504ad46e Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Mon, 3 Nov 2025 12:45:51 +0100 Subject: [PATCH 130/138] arm64: dts: qcom: sdm845-oneplus: Group panel pinctrl As these pins won't be used outside the group, let's group them. Reviewed-by: Dmitry Baryshkov Signed-off-by: David Heidelberg Link: https://lore.kernel.org/r/20251103-s6e3fc2x01-v6-2-d4eb4abaefa4@ixit.cz Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm845-oneplus-common.dtsi | 46 ++++++++++--------- 1 file changed, 24 insertions(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index d619b710c63f..d59a5e8cdeb2 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -450,7 +450,7 @@ display_panel: panel@0 { reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; - pinctrl-0 = <&panel_reset_pins &panel_te_pin &panel_esd_pin>; + pinctrl-0 = <&panel_default>; port { panel_in: endpoint { @@ -841,6 +841,29 @@ alert_slider_default: alert-slider-default-state { bias-disable; }; + panel_default: panel-default-state { + esd-pins { + pins = "gpio30"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + reset-pins { + pins = "gpio6"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + te-pins { + pins = "gpio10"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-disable; + }; + }; + ts_default_pins: ts-int-state { pins = "gpio99", "gpio125"; function = "gpio"; @@ -848,27 +871,6 @@ ts_default_pins: ts-int-state { bias-pull-up; }; - panel_reset_pins: panel-reset-state { - pins = "gpio6"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - - panel_te_pin: panel-te-state { - pins = "gpio10"; - function = "mdp_vsync"; - drive-strength = <2>; - bias-disable; - }; - - panel_esd_pin: panel-esd-state { - pins = "gpio30"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - speaker_default: speaker-default-state { pins = "gpio69"; function = "gpio"; From 8dda2fecf76b6c4db5f4c1b81a765b73a7a878ed Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Mon, 3 Nov 2025 12:45:52 +0100 Subject: [PATCH 131/138] arm64: dts: qcom: sdm845-oneplus: Implement panel sleep pinctrl We can DSI pin from 8mA to 2mA while suspend, do it. In theory, should give us extra 2 hours of idle battery life. cosmetic: sort pinctrl properties. Reviewed-by: Dmitry Baryshkov Signed-off-by: David Heidelberg Link: https://lore.kernel.org/r/20251103-s6e3fc2x01-v6-3-d4eb4abaefa4@ixit.cz Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm845-oneplus-common.dtsi | 26 ++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index d59a5e8cdeb2..f00dbc0fff3d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -449,8 +449,9 @@ display_panel: panel@0 { reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&panel_default>; + pinctrl-1 = <&panel_sleep>; + pinctrl-names = "default", "sleep"; port { panel_in: endpoint { @@ -864,6 +865,29 @@ te-pins { }; }; + panel_sleep: panel-sleep-state { + esd-pins { + pins = "gpio30"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + reset-pins { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + te-pins { + pins = "gpio10"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-disable; + }; + }; + ts_default_pins: ts-int-state { pins = "gpio99", "gpio125"; function = "gpio"; From a3da84c36b1a6b80814b5a72ca1546648aba9e75 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Mon, 3 Nov 2025 12:45:53 +0100 Subject: [PATCH 132/138] arm64: dts: qcom: sdm845-oneplus: Describe TE gpio Describe panel Tearing Effect (TE) GPIO line. Signed-off-by: David Heidelberg Link: https://lore.kernel.org/r/20251103-s6e3fc2x01-v6-4-d4eb4abaefa4@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index f00dbc0fff3d..db6dd04c51bb 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -447,6 +447,7 @@ display_panel: panel@0 { vci-supply = <&panel_vci_3v3>; poc-supply = <&panel_vddi_poc_1p8>; + te-gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>; reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; pinctrl-0 = <&panel_default>; From 35ddab284539c5c4352f07f7866163c5b6c2a236 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Tue, 4 Nov 2025 13:48:14 +0800 Subject: [PATCH 133/138] arm64: dts: qcom: kodiak: add coresight nodes Add TPDM, TPDA, CTI and funnel coresight devices for AOSS and QDSS blocks. Signed-off-by: Jie Gan Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251104-add-coresight-nodes-for-sc7280-v2-1-c67fa3890c2a@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 292 +++++++++++++++++++++++++++ 1 file changed, 292 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index 3ef61af2ed8a..ccbb57f77453 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -3338,6 +3338,86 @@ stm_out: endpoint { }; }; + tpda@6004000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x06004000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1c { + reg = <0x1c>; + + qdss_tpda_in28: endpoint { + remote-endpoint = <&spdm_tpdm_out>; + }; + }; + }; + + out-ports { + port { + qdss_tpda_out: endpoint { + remote-endpoint = <&qdss_dl_funnel_in0>; + }; + }; + }; + }; + + funnel@6005000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x06005000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + qdss_dl_funnel_in0: endpoint { + remote-endpoint = <&qdss_tpda_out>; + }; + }; + }; + + out-ports { + port { + qdss_dl_funnel_out: endpoint { + remote-endpoint = <&funnel0_in6>; + }; + }; + }; + }; + + tpdm@600f000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x0600f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + spdm_tpdm_out: endpoint { + remote-endpoint = <&qdss_tpda_in28>; + }; + }; + }; + }; + + cti@6010000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x06010000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + funnel@6041000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x06041000 0 0x1000>; @@ -3357,6 +3437,14 @@ in-ports { #address-cells = <1>; #size-cells = <0>; + port@6 { + reg = <6>; + + funnel0_in6: endpoint { + remote-endpoint = <&qdss_dl_funnel_out>; + }; + }; + port@7 { reg = <7>; funnel0_in7: endpoint { @@ -3471,6 +3559,38 @@ etr_in: endpoint { }; }; + cti@6b00000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x06b00000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + cti@6b01000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x06b01000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + cti@6b02000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x06b02000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + cti@6b03000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x06b03000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + funnel@6b04000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x06b04000 0 0x1000>; @@ -3490,6 +3610,14 @@ in-ports { #address-cells = <1>; #size-cells = <0>; + port@6 { + reg = <6>; + + swao_funnel_in6: endpoint { + remote-endpoint = <&aoss_tpda_out>; + }; + }; + port@7 { reg = <7>; swao_funnel_in: endpoint { @@ -3548,6 +3676,170 @@ swao_replicator_in: endpoint { }; }; + tpda@6b08000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x06b08000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + aoss_tpda_in0: endpoint { + remote-endpoint = <&swao_prio0_tpdm_out>; + }; + }; + + port@1 { + reg = <1>; + + aoss_tpda_in1: endpoint { + remote-endpoint = <&swao_prio1_tpdm_out>; + }; + }; + + port@2 { + reg = <2>; + + aoss_tpda_in2: endpoint { + remote-endpoint = <&swao_prio2_tpdm_out>; + }; + }; + + port@3 { + reg = <3>; + + aoss_tpda_in3: endpoint { + remote-endpoint = <&swao_prio3_tpdm_out>; + }; + }; + + port@4 { + reg = <4>; + + aoss_tpda_in4: endpoint { + remote-endpoint = <&swao_tpdm_out>; + }; + }; + }; + + out-ports { + port { + aoss_tpda_out: endpoint { + remote-endpoint = <&swao_funnel_in6>; + }; + }; + }; + }; + + tpdm@6b09000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x06b09000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + swao_prio0_tpdm_out: endpoint { + remote-endpoint = <&aoss_tpda_in0>; + }; + }; + }; + }; + + tpdm@6b0a000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x06b0a000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + swao_prio1_tpdm_out: endpoint { + remote-endpoint = <&aoss_tpda_in1>; + }; + }; + }; + }; + + tpdm@6b0b000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x06b0b000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + swao_prio2_tpdm_out: endpoint { + remote-endpoint = <&aoss_tpda_in2>; + }; + }; + }; + }; + + tpdm@6b0c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x06b0c000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + swao_prio3_tpdm_out: endpoint { + remote-endpoint = <&aoss_tpda_in3>; + }; + }; + }; + }; + + tpdm@6b0d000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x06b0d000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + swao_tpdm_out: endpoint { + remote-endpoint = <&aoss_tpda_in4>; + }; + }; + }; + }; + + cti@6b11000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x06b11000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + etm@7040000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07040000 0 0x1000>; From bba4562adc06a9ca70bbbc9c3c17d4174e794bf9 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 10 Nov 2025 12:16:24 -0600 Subject: [PATCH 134/138] Revert "arm64: dts: qcom: sc7280: Increase config size to 256MB for ECAM feature" The author failed to document the dependencies of this commit, resulting in a regression. This reverts commit 03e928442d469f7d8dafc549638730647202d9ce. Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index ccbb57f77453..c2ccbb67f800 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -2332,11 +2332,11 @@ pcie0_phy: phy@1c06000 { pcie1: pcie@1c08000 { compatible = "qcom,pcie-sc7280"; - reg = <0x0 0x01c08000 0 0x3000>, - <0x4 0x10001000 0 0xf1d>, - <0x4 0x10001f20 0 0xa8>, - <0x4 0x10000000 0 0x1000>, - <0x4 0x00000000 0 0x10000000>; + reg = <0 0x01c08000 0 0x3000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40001000 0 0x1000>, + <0 0x40100000 0 0x100000>; reg-names = "parf", "dbi", "elbi", "atu", "config"; device_type = "pci"; @@ -2347,8 +2347,8 @@ pcie1: pcie@1c08000 { #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x0 0x40000000 0x0 0x100000>, - <0x02000000 0x0 0x40100000 0x0 0x40100000 0x0 0x1ff00000>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; interrupts = , , From 9c92d36b0b1ea8b2a19dbe0416434f3491dbfaaf Mon Sep 17 00:00:00 2001 From: Praveen Talari Date: Mon, 10 Nov 2025 15:40:40 +0530 Subject: [PATCH 135/138] arm64: dts: qcom: qrb2210-rb1: Fix UART3 wakeup IRQ storm For BT use cases, pins are configured with pull-up state in sleep state to avoid noise. If IRQ type is configured as level high and the GPIO line is also in a high state, it causes continuous interrupt assertions leading to an IRQ storm when wakeup irq enables at system suspend/runtime suspend. Switching to edge-triggered interrupt (IRQ_TYPE_EDGE_FALLING) resolves this by only triggering on state transitions (high-to-low) rather than maintaining sensitivity to the static level state, effectively preventing the continuous interrupt condition and eliminating the wakeup IRQ storm. Fixes: 9380e0a1d449 ("arm64: dts: qcom: qrb2210-rb1: add Bluetooth support") Signed-off-by: Praveen Talari Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251110101043.2108414-2-praveen.talari@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts index e0e362b140ad..1b9ca957a94b 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -704,7 +704,7 @@ key_volp_n: key-volp-n-state { &uart3 { /delete-property/ interrupts; interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, - <&tlmm 11 IRQ_TYPE_LEVEL_HIGH>; + <&tlmm 11 IRQ_TYPE_EDGE_FALLING>; pinctrl-0 = <&uart3_default>; pinctrl-1 = <&uart3_sleep>; pinctrl-names = "default", "sleep"; From aabd179bcbde9f795a89cc015953a1057600c21e Mon Sep 17 00:00:00 2001 From: Xueyao An Date: Wed, 5 Nov 2025 13:45:47 +0800 Subject: [PATCH 136/138] arm64: dts: qcom: HAMOA-IOT-SOM: Unreserve GPIOs blocking SPI11 access GPIOs 44-47 were previously reserved, preventing Linux from accessing SPI11 (qupv1_se3). Since there is no TZ use case for these pins on Linux, they can be safely unreserved. Removing them from the reserved list resolves the SPI11 access issue for Linux. Signed-off-by: Xueyao An Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251105054548.2347569-1-xueyao.an@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi index 4de7c0abb25a..4a69852e9176 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi @@ -451,8 +451,7 @@ &remoteproc_cdsp { }; &tlmm { - gpio-reserved-ranges = <34 2>, /* TPM LP & INT */ - <44 4>; /* SPI (TPM) */ + gpio-reserved-ranges = <34 2>; /* TPM LP & INT */ pcie4_default: pcie4-default-state { clkreq-n-pins { From 101dae743d4bfa1c779de4ef1c65393cc4824d4e Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Fri, 14 Nov 2025 11:45:52 +0530 Subject: [PATCH 137/138] arm64: dts: qcom: sdx75: Flatten usb controller node Flatten usb controller node and update to using latest bindings and flattened driver approach. Signed-off-by: Krishna Kurapati Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251114061553.512441-2-krishna.kurapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdx75-idp.dts | 6 +-- arch/arm64/boot/dts/qcom/sdx75.dtsi | 62 ++++++++++++-------------- 2 files changed, 31 insertions(+), 37 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdx75-idp.dts b/arch/arm64/boot/dts/qcom/sdx75-idp.dts index 06cacec3461f..6696e1aee243 100644 --- a/arch/arm64/boot/dts/qcom/sdx75-idp.dts +++ b/arch/arm64/boot/dts/qcom/sdx75-idp.dts @@ -337,11 +337,9 @@ &uart1 { }; &usb { - status = "okay"; -}; - -&usb_dwc3 { dr_mode = "peripheral"; + + status = "okay"; }; &usb_hsphy { diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index f26ba90ba66d..e586b55c155b 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -1019,12 +1019,9 @@ opp-384000000 { }; }; - usb: usb@a6f8800 { - compatible = "qcom,sdx75-dwc3", "qcom,dwc3"; - reg = <0x0 0x0a6f8800 0x0 0x400>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + usb: usb@a600000 { + compatible = "qcom,sdx75-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a600000 0x0 0xfc100>; clocks = <&gcc GCC_USB30_SLV_AHB_CLK>, <&gcc GCC_USB30_MASTER_CLK>, @@ -1041,21 +1038,35 @@ usb: usb@a6f8800 { <&gcc GCC_USB30_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <&pdc 10 IRQ_TYPE_EDGE_RISING>, <&pdc 9 IRQ_TYPE_EDGE_RISING>, <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; + iommus = <&apps_smmu 0x80 0x0>; + + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + power-domains = <&gcc GCC_USB30_GDSC>; resets = <&gcc GCC_USB30_BCR>; + phys = <&usb_hsphy>, + <&usb_qmpphy>; + phy-names = "usb2-phy", + "usb3-phy"; + interconnects = <&system_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1065,36 +1076,21 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, status = "disabled"; - usb_dwc3: usb@a600000 { - compatible = "snps,dwc3"; - reg = <0x0 0x0a600000 0x0 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x80 0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - phys = <&usb_hsphy>, - <&usb_qmpphy>; - phy-names = "usb2-phy", - "usb3-phy"; + ports { + #address-cells = <1>; + #size-cells = <0>; - ports { - #address-cells = <1>; - #size-cells = <0>; + port@0 { + reg = <0>; - port@0 { - reg = <0>; - - usb_1_dwc3_hs: endpoint { - }; + usb_1_dwc3_hs: endpoint { }; + }; - port@1 { - reg = <1>; + port@1 { + reg = <1>; - usb_1_dwc3_ss: endpoint { - }; + usb_1_dwc3_ss: endpoint { }; }; }; From f481e772e014da92fa1232de54e4cac66b5fc5e4 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Fri, 14 Nov 2025 11:45:53 +0530 Subject: [PATCH 138/138] arm64: dts: qcom: sdx75: Add missing usb-role-switch property Add missing usb-role-switch property to usb controller node. Signed-off-by: Krishna Kurapati Link: https://lore.kernel.org/r/20251114061553.512441-3-krishna.kurapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index e586b55c155b..eff4c9055d66 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -1074,6 +1074,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, interconnect-names = "usb-ddr", "apps-usb"; + usb-role-switch; + status = "disabled"; ports {