From 21f1208a3af4c30497f60ce220490edd761c5ed9 Mon Sep 17 00:00:00 2001 From: Jimmy Hon Date: Thu, 27 Feb 2025 17:56:20 -0600 Subject: [PATCH 01/15] arm64: dts: rockchip: Enable HDMI0 audio output for Orange Pi 5/5B HDMI audio is available on the Orange Pi 5 HDMI0 TX port. Signed-off-by: Jimmy Hon Link: https://lore.kernel.org/r/20250227235623.1624-2-honyuenkwun@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi index 37b08d1a215f..4fedc50cce8c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi @@ -197,6 +197,10 @@ hdmi0_out_con: endpoint { }; }; +&hdmi0_sound { + status = "okay"; +}; + &hdptxphy0 { status = "okay"; }; @@ -355,6 +359,10 @@ &i2s1m0_sdi1 status = "okay"; }; +&i2s5_8ch { + status = "okay"; +}; + &mdio1 { rgmii_phy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; From 01284d7e38fca8a4d6a9982cc69e618aadd30de1 Mon Sep 17 00:00:00 2001 From: Jimmy Hon Date: Thu, 27 Feb 2025 17:56:21 -0600 Subject: [PATCH 02/15] arm64: dts: rockchip: Enable HDMI audio outputs for Orange Pi 5 Max HDMI audio is available on the Orange Pi 5 Max HDMI TX ports. Enable it for both ports. Signed-off-by: Jimmy Hon Link: https://lore.kernel.org/r/20250227235623.1624-3-honyuenkwun@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588-orangepi-5-max.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts index be8cc96b5308..8b1d35760c3b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts @@ -50,6 +50,10 @@ hdmi0_out_con: endpoint { }; }; +&hdmi0_sound { + status = "okay"; +}; + &hdmi1 { pinctrl-names = "default"; pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd @@ -69,6 +73,10 @@ hdmi1_out_con: endpoint { }; }; +&hdmi1_sound { + status = "okay"; +}; + &hdptxphy0 { status = "okay"; }; @@ -77,6 +85,14 @@ &hdptxphy1 { status = "okay"; }; +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + &led_blue_pwm { pwms = <&pwm4 0 25000 0>; }; From ffafe9c2dc31d1a346aff482157dd37eaadbe054 Mon Sep 17 00:00:00 2001 From: Jimmy Hon Date: Thu, 27 Feb 2025 17:56:22 -0600 Subject: [PATCH 03/15] arm64: dts: rockchip: Enable HDMI1 on Orange Pi 5 Plus Enable the second HDMI output port on the Orange Pi 5 Plus Signed-off-by: Jimmy Hon Reviewed-by: Ondrej Jirman Link: https://lore.kernel.org/r/20250227235623.1624-4-honyuenkwun@gmail.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3588-orangepi-5-plus.dts | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts index 0f874b87b47e..53797f633d3a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts @@ -26,6 +26,17 @@ hdmi0_con_in: endpoint { }; }; + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + ir-receiver { compatible = "gpio-ir-receiver"; gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; @@ -125,10 +136,30 @@ hdmi0_out_con: endpoint { }; }; +&hdmi1 { + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + &hdptxphy0 { status = "okay"; }; +&hdptxphy1 { + status = "okay"; +}; + &hym8563 { interrupt-parent = <&gpio0>; interrupts = ; @@ -342,3 +373,10 @@ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { remote-endpoint = <&hdmi0_in_vp0>; }; }; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = ; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; From 1bfb987d1a54bc139b62261e3698006418835229 Mon Sep 17 00:00:00 2001 From: Jimmy Hon Date: Thu, 27 Feb 2025 17:56:23 -0600 Subject: [PATCH 04/15] arm64: dts: rockchip: Enable HDMI audio outputs for Orange Pi 5 Plus HDMI audio is available on the Orange Pi 5 Plus HDMI TX ports. Enable it for both ports. Signed-off-by: Jimmy Hon Link: https://lore.kernel.org/r/20250227235623.1624-5-honyuenkwun@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts index 53797f633d3a..121e4d1c3fa5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts @@ -124,6 +124,10 @@ &hdmi0 { status = "okay"; }; +&hdmi0_sound { + status = "okay"; +}; + &hdmi0_in { hdmi0_in_vp0: endpoint { remote-endpoint = <&vp0_out_hdmi0>; @@ -152,6 +156,10 @@ hdmi1_out_con: endpoint { }; }; +&hdmi1_sound { + status = "okay"; +}; + &hdptxphy0 { status = "okay"; }; @@ -220,6 +228,14 @@ usbc0_sbu: endpoint { }; }; +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + &led_blue_gpio { gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; status = "okay"; From d6166ea4cc4943cbabdeeedb13f3545fdba3ebf6 Mon Sep 17 00:00:00 2001 From: Jianfeng Liu Date: Tue, 11 Mar 2025 22:27:50 +0800 Subject: [PATCH 05/15] arm64: dts: rockchip: Add AP6275P wireless support to ArmSoM Sige7 ArmSoM Sige7 uses the PCI-e AP6275P Wi-Fi 6 module. The pcie@0 node can be used as Bridge1, so the wifi@0 node is used as a device under the bridge 1 similar with Khadas Edge 2. Signed-off-by: Jianfeng Liu Link: https://lore.kernel.org/r/20250311142825.2727171-1-liujianfeng1994@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588-armsom-sige7.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts index 6a0fffaa26ee..face42bb0d7d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts @@ -300,6 +300,22 @@ &pcie2x1l0 { &pcie2x1l1 { reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; status = "okay"; + + pcie@0,0 { + reg = <0x300000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + device_type = "pci"; + bus-range = <0x30 0x3f>; + + wifi: wifi@0,0 { + compatible = "pci14e4,449d"; + reg = <0x310000 0 0 0 0>; + clocks = <&hym8563>; + clock-names = "lpo"; + }; + }; }; /* phy0 - left ethernet port */ From 8fbb9376f0c489dfdc7e20d16e90686b29dec8f2 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sat, 8 Mar 2025 18:00:01 +0800 Subject: [PATCH 06/15] arm64: dts: rockchip: Move rk356x scmi SHMEM to reserved memory 0x0 to 0xf0000000 are SDRAM memory areas where 0x10f000 is located. So move the SHMEM memory of arm_scmi to the reserved memory node. Fixes: a3adc0b9071d ("arm64: dts: rockchip: add core dtsi for RK3568 SoC") Signed-off-by: Chukun Pan Link: https://lore.kernel.org/r/20250308100001.572657-2-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 25 +++++++++---------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index de5e6c0c3d24..81e635620301 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -174,6 +174,18 @@ psci { method = "smc"; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scmi_shmem: shmem@10f000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x0010f000 0x0 0x100>; + no-map; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , @@ -199,19 +211,6 @@ xin32k: xin32k { #clock-cells = <0>; }; - sram@10f000 { - compatible = "mmio-sram"; - reg = <0x0 0x0010f000 0x0 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x0010f000 0x100>; - - scmi_shmem: sram@0 { - compatible = "arm,scmi-shmem"; - reg = <0x0 0x100>; - }; - }; - sata1: sata@fc400000 { compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; reg = <0 0xfc400000 0 0x1000>; From 6b68387cf5ff5d7b86b189135affb0c679e3384a Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 21 Feb 2025 00:50:51 +0800 Subject: [PATCH 07/15] arm64: dts: rockchip: Remove bluetooth node from rock-3a The Bluetooth node described in the device tree is actually on an M.2 slot. What module is present depends on what the end user installed, and should be left to an overlay. Remove the existing bluetooth node. This gets rid of bogus timeout errors. Fixes: 8cf890aabd45 ("arm64: dts: rockchip: Add nodes for SDIO/UART Wi-Fi/Bluetooth modules to Radxa Rock 3A") Signed-off-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20250220165051.1889055-1-wens@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts index ac79140a9ecd..44cfdfeed668 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -778,20 +778,6 @@ &uart1 { pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; uart-has-rtscts; status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rk809 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>; - vbat-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8>; - /* vddio comes from regulator on module, use IO bank voltage instead */ - }; }; &uart2 { From a98cc47f79ab5b8059b748bf0bd59335edfff7d9 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 5 Mar 2025 21:41:03 +0000 Subject: [PATCH 08/15] arm64: dts: rockchip: Add SDHCI controller for RK3528 The SDHCI controller in Rockchip RK3528 is similar to the one included in RK3588. Add device tree node for the SDHCI controller in RK3528. Signed-off-by: Jonas Karlman Link: https://lore.kernel.org/r/20250305214108.1327208-3-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index c2eaa0c6ea90..26c3559d6a6d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -468,6 +468,30 @@ saradc: adc@ffae0000 { status = "disabled"; }; + sdhci: mmc@ffbf0000 { + compatible = "rockchip,rk3528-dwcmshc", + "rockchip,rk3588-dwcmshc"; + reg = <0x0 0xffbf0000 0x0 0x10000>; + assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, + <&cru CCLK_SRC_EMMC>; + assigned-clock-rates = <200000000>, <24000000>, + <200000000>; + clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>, + <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, + <&cru TCLK_EMMC>; + clock-names = "core", "bus", "axi", "block", "timer"; + interrupts = ; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>, + <&emmc_strb>; + resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, + <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, + <&cru SRST_T_EMMC>; + reset-names = "core", "bus", "axi", "block", "timer"; + status = "disabled"; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3528-pinctrl"; rockchip,grf = <&ioc_grf>; From 3a01b5f14a8ae2d45aea5aeed30001ac1655de86 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 5 Mar 2025 21:41:04 +0000 Subject: [PATCH 09/15] arm64: dts: rockchip: Enable onboard eMMC on Radxa E20C The Radxa E20C may come with an onboard eMMC (8GB / 16GB / 32GB / 64GB). Enable support for the onboard eMMC on Radxa E20C. Signed-off-by: Jonas Karlman Link: https://lore.kernel.org/r/20250305214108.1327208-4-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- .../arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts index 5346ef457c2a..57a446b5cbd6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts @@ -15,6 +15,10 @@ / { model = "Radxa E20C"; compatible = "radxa,e20c", "rockchip,rk3528"; + aliases { + mmc0 = &sdhci; + }; + chosen { stdout-path = "serial0:1500000n8"; }; @@ -133,6 +137,17 @@ &saradc { status = "okay"; }; +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + no-sd; + no-sdio; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0m0_xfer>; From 1f04a241759e78c0295f09731f9de3d7eb1ea6e5 Mon Sep 17 00:00:00 2001 From: Jianfeng Liu Date: Thu, 13 Mar 2025 00:40:49 +0800 Subject: [PATCH 10/15] arm64: dts: rockchip: Enable HDMI audio output for ArmSoM Sige7 HDMI audio is available on the ArmSoM Sige7 HDMI TX port. Enable it for HDMI0 port. Signed-off-by: Jianfeng Liu Link: https://lore.kernel.org/r/20250312164056.3998224-1-liujianfeng1994@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts index face42bb0d7d..ae9274365bed 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts @@ -192,6 +192,10 @@ hdmi0_out_con: endpoint { }; }; +&hdmi0_sound { + status = "okay"; +}; + &hdptxphy0 { status = "okay"; }; @@ -290,6 +294,10 @@ i2s0_8ch_p0_0: endpoint { }; }; +&i2s5_8ch { + status = "okay"; +}; + /* phy1 - right ethernet port */ &pcie2x1l0 { reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; From e0945a08fc7f7ed26c8dae286a3d30a68ad37d50 Mon Sep 17 00:00:00 2001 From: Jianfeng Liu Date: Tue, 11 Mar 2025 22:12:39 +0800 Subject: [PATCH 11/15] arm64: dts: rockchip: Fix pcie reset gpio on Orange Pi 5 Max According to the schematic, pcie reset gpio is GPIO3_D4, not GPIO4_D4. Fixes: c600d252dc52 ("arm64: dts: rockchip: Add Orange Pi 5 Max board") Signed-off-by: Jianfeng Liu Reviewed-by: Jimmy Hon Link: https://lore.kernel.org/r/20250311141245.2719796-1-liujianfeng1994@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-compact.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-compact.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-compact.dtsi index 6e4dcd8fff26..f748c6f760d8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-compact.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-compact.dtsi @@ -64,7 +64,7 @@ &led_blue_pwm { /* phy2 */ &pcie2x1l1 { - reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie_eth>; status = "okay"; }; From 28699ca6d9018201674787e7b6bdce68d9cf7256 Mon Sep 17 00:00:00 2001 From: Nicolas Frattaroli Date: Mon, 10 Mar 2025 10:59:56 +0100 Subject: [PATCH 12/15] dt-bindings: clock: rk3576: add SCMI clocks Mainline Linux uses different clock IDs from both downstream and mainline TF-A, which both got them from downstream Linux. If we want to control clocks through SCMI, we'll need to know about these IDs. Add the relevant ones prefixed with SCMI_ to the header. Signed-off-by: Nicolas Frattaroli Acked-by: "Rob Herring (Arm)" Link: https://lore.kernel.org/r/20250310-rk3576-scmi-clocks-v1-1-e165deb034e8@collabora.com Signed-off-by: Heiko Stuebner --- include/dt-bindings/clock/rockchip,rk3576-cru.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/dt-bindings/clock/rockchip,rk3576-cru.h b/include/dt-bindings/clock/rockchip,rk3576-cru.h index 25aed298ac2c..f576e61bec70 100644 --- a/include/dt-bindings/clock/rockchip,rk3576-cru.h +++ b/include/dt-bindings/clock/rockchip,rk3576-cru.h @@ -589,4 +589,9 @@ #define PCLK_EDP_S 569 #define ACLK_KLAD 570 +/* SCMI clocks, use these when changing clocks through SCMI */ +#define SCMI_ARMCLK_L 10 +#define SCMI_ARMCLK_B 11 +#define SCMI_CLK_GPU 456 + #endif From b5cb721adbe8b6c7a8e3b178fa0feb283f4a660a Mon Sep 17 00:00:00 2001 From: Nicolas Frattaroli Date: Mon, 10 Mar 2025 10:59:57 +0100 Subject: [PATCH 13/15] arm64: dts: rockchip: fix RK3576 SCMI clock IDs Downstream Linux, and consequently both downstream and mainline TF-A, all use a different set of clock IDs from mainline Linux. If we want to fiddle with these clocks through SCMI, we'll need to use the right IDs. If we don't do this we'll end up changing unrelated clocks all over the place. Change the clock IDs to the newly added SCMI clock IDs for the CPU and GPU nodes, which are currently the only ones using SCMI clocks. This fixes the terrible GPU performance, as we weren't reclocking it properly. Fixes: 57b1ce903966 ("arm64: dts: rockchip: Add rk3576 SoC base DT") Reported-by: Jonas Karlman Closes: https://libera.irclog.whitequark.org/linux-rockchip/2025-03-09#1741542223-1741542875; Signed-off-by: Nicolas Frattaroli Link: https://lore.kernel.org/r/20250310-rk3576-scmi-clocks-v1-2-e165deb034e8@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index edfa0326f299..b379e4622947 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -111,7 +111,7 @@ cpu_l0: cpu@0 { reg = <0x0>; enable-method = "psci"; capacity-dmips-mhz = <485>; - clocks = <&scmi_clk ARMCLK_L>; + clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; #cooling-cells = <2>; dynamic-power-coefficient = <120>; @@ -124,7 +124,7 @@ cpu_l1: cpu@1 { reg = <0x1>; enable-method = "psci"; capacity-dmips-mhz = <485>; - clocks = <&scmi_clk ARMCLK_L>; + clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -135,7 +135,7 @@ cpu_l2: cpu@2 { reg = <0x2>; enable-method = "psci"; capacity-dmips-mhz = <485>; - clocks = <&scmi_clk ARMCLK_L>; + clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -146,7 +146,7 @@ cpu_l3: cpu@3 { reg = <0x3>; enable-method = "psci"; capacity-dmips-mhz = <485>; - clocks = <&scmi_clk ARMCLK_L>; + clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -157,7 +157,7 @@ cpu_b0: cpu@100 { reg = <0x100>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk ARMCLK_B>; + clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; #cooling-cells = <2>; dynamic-power-coefficient = <320>; @@ -170,7 +170,7 @@ cpu_b1: cpu@101 { reg = <0x101>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk ARMCLK_B>; + clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -181,7 +181,7 @@ cpu_b2: cpu@102 { reg = <0x102>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk ARMCLK_B>; + clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -192,7 +192,7 @@ cpu_b3: cpu@103 { reg = <0x103>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk ARMCLK_B>; + clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -932,7 +932,7 @@ power-domain@RK3576_PD_VO1 { gpu: gpu@27800000 { compatible = "rockchip,rk3576-mali", "arm,mali-bifrost"; reg = <0x0 0x27800000 0x0 0x200000>; - assigned-clocks = <&scmi_clk CLK_GPU>; + assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; assigned-clock-rates = <198000000>; clocks = <&cru CLK_GPU>; clock-names = "core"; From 09b0a7b63a6cda138e2e47c6acb2aee80338624c Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Mon, 10 Mar 2025 14:09:17 +0000 Subject: [PATCH 14/15] arm64: dts: rockchip: Fix PWM pinctrl names These Rockchip boards assign "active" as the pinctrl name for PWM controllers, which has never been supported in mainline Rockchip PWM driver. It seems the name used by downstream kernel is accidentally brought into maineline. Let's fix them. Fixes: 4403e1237be3 ("arm64: dts: rockchip: Add devicetree for board roc-rk3308-cc") Fixes: 964ed0807b5f ("arm64: dts: rockchip: add rk3318 A95X Z2 board") Fixes: e7a095908227 ("arm64: dts: rockchip: Add devicetree for NanoPC-T4") Fixes: 3f5d336d64d6 ("arm64: dts: rockchip: Add support for rk3588s based board Cool Pi 4B") Signed-off-by: Yao Zi Link: https://lore.kernel.org/r/20250310140916.14384-2-ziyao@disroot.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts | 4 ++-- arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi | 2 +- arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts index 629121de5a13..5e7181948992 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts @@ -147,7 +147,7 @@ rtc: rtc@51 { &pwm5 { status = "okay"; - pinctrl-names = "active"; + pinctrl-names = "default"; pinctrl-0 = <&pwm5_pin_pull_down>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts b/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts index a94114fb7cc1..96c27fc5005d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts @@ -274,13 +274,13 @@ otg_vbus_drv: otg-vbus-drv { &pwm0 { pinctrl-0 = <&pwm0_pin_pull_up>; - pinctrl-names = "active"; + pinctrl-names = "default"; status = "okay"; }; &pwm1 { pinctrl-0 = <&pwm1_pin_pull_up>; - pinctrl-names = "active"; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi index b169be06d4d1..c8eb5481f43d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi @@ -603,7 +603,7 @@ &pwm1 { }; &pwm2 { - pinctrl-names = "active"; + pinctrl-names = "default"; pinctrl-0 = <&pwm2_pin_pull_down>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts index 8f00e0444c00..8b717c4017a4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts @@ -433,7 +433,7 @@ &pwm2 { }; &pwm13 { - pinctrl-names = "active"; + pinctrl-names = "default"; pinctrl-0 = <&pwm13m2_pins>; status = "okay"; }; From 73d246b4402c3356f6b3d13665de3a51eea7b555 Mon Sep 17 00:00:00 2001 From: Nicolas Frattaroli Date: Fri, 14 Mar 2025 16:35:50 +0100 Subject: [PATCH 15/15] arm64: dts: rockchip: remove ethm0_clk0_25m_out from Sige5 gmac0 The GPIO3 A4 pin on the ArmSoM Sige5 is routed to the 40-pin GPIO header. This pin can serve a variety of functions, including ones of questionable use to us on a GPIO header such as the 25MHz clock of the ethernet controller. Unfortunately, this is the precise function that it is being claimed for by the gmac0 node in the Sige5 board dts, meaning it can't be used for anything else despite serving no useful function in this role. Since it goes through a RS0108 bidirectional voltage level translator with a maximum data rate of 24Mbit/s in push-pull mode and 2Mbit/s data rate in open-drain mode, it's doubtful as to whether the 25MHz clock signal would even survive to the actual user-accessible pin it terminates in. Remove it to leave the pin for users to play with. It's infinitely more useful as a GPIO or even as a PWM. Fixes: 40f742b07ab2 ("arm64: dts: rockchip: Add rk3576-armsom-sige5 board") Signed-off-by: Nicolas Frattaroli Link: https://lore.kernel.org/r/20250314-rk3576-sige5-eth-clk-begone-v1-1-2858338fc555@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts index 78798b0722a3..828bde7fab68 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts @@ -194,8 +194,7 @@ &gmac0 { ð0m0_tx_bus2 ð0m0_rx_bus2 ð0m0_rgmii_clk - ð0m0_rgmii_bus - ðm0_clk0_25m_out>; + ð0m0_rgmii_bus>; phy-handle = <&rgmii_phy0>; status = "okay";