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drm/etnaviv: force flush on power register ops

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Add gpu_write_power_sync to verify that power register modifications
have reached the endpoint device in sequence specific sections that do
not validate device state.

These sequence specific areas have been detected experimentally with an
am57xx-evm through numerous boot and module load+unload cycles.

Signed-off-by: Randolph Sapp <rs@ti.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Link: https://patch.msgid.link/20251013170122.1145387-2-rs@ti.com
This commit is contained in:
Randolph Sapp 2025-10-13 12:01:23 -05:00 committed by Lucas Stach
parent 9c99e09777
commit c182a2ae13
2 changed files with 11 additions and 5 deletions
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10
drivers/gpu/drm/etnaviv/etnaviv_gpu.c
View File

@ -545,13 +545,13 @@ static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
u32 pulse_eater = 0x01590880;
/* disable clock gating */
gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, 0x0);
gpu_write_power_sync(gpu, VIVS_PM_POWER_CONTROLS, 0x0);
/* disable pulse eater */
pulse_eater |= BIT(17);
gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
pulse_eater |= BIT(0);
gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
gpu_write_power_sync(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
/* enable clock */
control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
@ -662,7 +662,7 @@ static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
gpu->identity.revision == 0x4302)
ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING;
gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, ppc);
gpu_write_power_sync(gpu, VIVS_PM_POWER_CONTROLS, ppc);
pmc = gpu_read_power(gpu, VIVS_PM_MODULE_CONTROLS);
@ -706,7 +706,7 @@ static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
gpu_write_power(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
gpu_write_power_sync(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
}
void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
@ -772,7 +772,7 @@ static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
pulse_eater |= BIT(18);
}
gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
gpu_write_power_sync(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
}
static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)

6
drivers/gpu/drm/etnaviv/etnaviv_gpu.h
View File

@ -204,6 +204,12 @@ static inline u32 gpu_read_power(struct etnaviv_gpu *gpu, u32 reg)
return readl(gpu->mmio + gpu_fix_power_address(gpu, reg));
}
static inline void gpu_write_power_sync(struct etnaviv_gpu *gpu, u32 reg, u32 data)
{
gpu_write_power(gpu, reg, data);
gpu_read_power(gpu, reg);
}
int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value);
int etnaviv_gpu_init(struct etnaviv_gpu *gpu);