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drm/msm/dpu: allocate single CTL for DPU >= 5.0

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Unlike previous generation, since DPU 5.0 it is possible to use just one
CTL to handle all INTF and WB blocks for a single output. And one has to
use single CTL to support bonded DSI config. Allocate single CTL for
these DPU versions.

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/641587/
Link: https://lore.kernel.org/r/20250307-dpu-active-ctl-v3-6-5d20655f10ca@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
This commit is contained in:
Dmitry Baryshkov 2025-03-07 08:24:54 +02:00 committed by Dmitry Baryshkov
parent e93eee524b
commit c1824a7992
2 changed files with 17 additions and 13 deletions
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28
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
View File

@ -53,6 +53,8 @@ int dpu_rm_init(struct drm_device *dev,
/* Clear, setup lists */
memset(rm, 0, sizeof(*rm));
rm->has_legacy_ctls = (cat->mdss_ver->core_major_ver < 5);
/* Interrogate HW catalog and create tracking items for hw blocks */
for (i = 0; i < cat->mixer_count; i++) {
struct dpu_hw_mixer *hw;
@ -434,20 +436,19 @@ static int _dpu_rm_reserve_ctls(
int i = 0, j, num_ctls;
bool needs_split_display;
/*
* For non-CWB mode, each hw_intf needs its own hw_ctl to program its
* control path.
*
* Hardcode num_ctls to 1 if CWB is enabled because in CWB, both the
* writeback and real-time encoders must be driven by the same control
* path
*/
if (top->cwb_enabled)
num_ctls = 1;
else
if (rm->has_legacy_ctls) {
/*
* TODO: check if there is a need for special handling if
* DPU < 5.0 get CWB support.
*/
num_ctls = top->num_intf;
needs_split_display = _dpu_rm_needs_split_display(top);
needs_split_display = _dpu_rm_needs_split_display(top);
} else {
/* use single CTL */
num_ctls = 1;
needs_split_display = false;
}
for (j = 0; j < ARRAY_SIZE(rm->ctl_blks); j++) {
const struct dpu_hw_ctl *ctl;
@ -465,7 +466,8 @@ static int _dpu_rm_reserve_ctls(
DPU_DEBUG("ctl %d caps 0x%lX\n", j + CTL_0, features);
if (needs_split_display != has_split_display)
if (rm->has_legacy_ctls &&
needs_split_display != has_split_display)
continue;
ctl_idx[i] = j;

2
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
View File

@ -24,6 +24,7 @@ struct dpu_global_state;
* @dspp_blks: array of dspp hardware resources
* @hw_sspp: array of sspp hardware resources
* @cdm_blk: cdm hardware resource
* @has_legacy_ctls: DPU uses pre-ACTIVE CTL blocks.
*/
struct dpu_rm {
struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0];
@ -37,6 +38,7 @@ struct dpu_rm {
struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
struct dpu_hw_sspp *hw_sspp[SSPP_MAX - SSPP_NONE];
struct dpu_hw_blk *cdm_blk;
bool has_legacy_ctls;
};
struct dpu_rm_sspp_requirements {