From c15787255a9cc0279053510174bcdde5627aaab8 Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Tue, 26 Apr 2022 15:50:12 -0700 Subject: [PATCH] dt-bindings: Add snapshot of header files from msm-5.15 Add snapshot of binding header files as of 'commit 8bc1219b2b23 ("Merge "ARM: dts: qcom: Add hotplug mitigation for cpu TSENS thermal zones"")' from msm-5.15/msm-5.15. Change-Id: I07ab7223a35a05e1b7e1f84ffa652876f5b8f472 Signed-off-by: Guru Das Srinagesh Signed-off-by: Huang Yiwei --- include/dt-bindings/clock/qcom,aop-qmp.h | 20 + include/dt-bindings/clock/qcom,camcc-kalama.h | 176 ++++ .../dt-bindings/clock/qcom,dispcc-kalama.h | 97 +++ include/dt-bindings/clock/qcom,gcc-kalama.h | 220 +++++ include/dt-bindings/clock/qcom,gpucc-kalama.h | 46 + include/dt-bindings/clock/qcom,rpmh.h | 2 +- .../dt-bindings/clock/qcom,tcsrcc-kalama.h | 17 + .../dt-bindings/clock/qcom,videocc-kalama.h | 38 + include/dt-bindings/input/qcom,hv-haptics.h | 2 +- .../dt-bindings/interconnect/qcom,kalama.h | 175 ++++ .../dt-bindings/phy/qcom,usb3-4nm-qmp-combo.h | 810 ++++++++++++++++++ include/dt-bindings/power/qcom-aoss-qmp.h | 14 + include/dt-bindings/soc/qcom,dcc_v2.h | 14 + include/dt-bindings/thermal/thermal_qti.h | 98 +++ 14 files changed, 1727 insertions(+), 2 deletions(-) create mode 100644 include/dt-bindings/clock/qcom,aop-qmp.h create mode 100644 include/dt-bindings/clock/qcom,camcc-kalama.h create mode 100644 include/dt-bindings/clock/qcom,dispcc-kalama.h create mode 100644 include/dt-bindings/clock/qcom,gcc-kalama.h create mode 100644 include/dt-bindings/clock/qcom,gpucc-kalama.h create mode 100644 include/dt-bindings/clock/qcom,tcsrcc-kalama.h create mode 100644 include/dt-bindings/clock/qcom,videocc-kalama.h create mode 100644 include/dt-bindings/interconnect/qcom,kalama.h create mode 100644 include/dt-bindings/phy/qcom,usb3-4nm-qmp-combo.h create mode 100644 include/dt-bindings/power/qcom-aoss-qmp.h create mode 100644 include/dt-bindings/soc/qcom,dcc_v2.h create mode 100644 include/dt-bindings/thermal/thermal_qti.h diff --git a/include/dt-bindings/clock/qcom,aop-qmp.h b/include/dt-bindings/clock/qcom,aop-qmp.h new file mode 100644 index 000000000000..6eea6fe56d24 --- /dev/null +++ b/include/dt-bindings/clock/qcom,aop-qmp.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */ + +#ifndef _DT_BINDINGS_CLK_QCOM_AOP_QMP_H +#define _DT_BINDINGS_CLK_QCOM_AOP_QMP_H + +#define QDSS_CLK_LEVEL_OFF 0 +#define QDSS_CLK_LEVEL_DYNAMIC 1 +#define QDSS_CLK_LEVEL_TURBO 2 +#define QDSS_CLK_LEVEL_NOMINAL 3 +#define QDSS_CLK_LEVEL_SVS_L1 4 +#define QDSS_CLK_LEVEL_SVS 5 +#define QDSS_CLK_LEVEL_LOW_SVS 6 +#define QDSS_CLK_LEVEL_MIN_SVS 7 + +/* clocks id */ +#define QDSS_CLK 0 +#define QDSS_AO_CLK 1 +#define BIMC_CLK 2 +#endif diff --git a/include/dt-bindings/clock/qcom,camcc-kalama.h b/include/dt-bindings/clock/qcom,camcc-kalama.h new file mode 100644 index 000000000000..2889e0a819db --- /dev/null +++ b/include/dt-bindings/clock/qcom,camcc-kalama.h @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_KALAMA_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_KALAMA_H + +/* CAM_CC clocks */ +#define CAM_CC_BPS_AHB_CLK 0 +#define CAM_CC_BPS_CLK 1 +#define CAM_CC_BPS_CLK_SRC 2 +#define CAM_CC_BPS_FAST_AHB_CLK 3 +#define CAM_CC_CAMNOC_AXI_CLK 4 +#define CAM_CC_CAMNOC_AXI_CLK_SRC 5 +#define CAM_CC_CAMNOC_DCD_XO_CLK 6 +#define CAM_CC_CAMNOC_XO_CLK 7 +#define CAM_CC_CCI_0_CLK 8 +#define CAM_CC_CCI_0_CLK_SRC 9 +#define CAM_CC_CCI_1_CLK 10 +#define CAM_CC_CCI_1_CLK_SRC 11 +#define CAM_CC_CCI_2_CLK 12 +#define CAM_CC_CCI_2_CLK_SRC 13 +#define CAM_CC_CORE_AHB_CLK 14 +#define CAM_CC_CPAS_AHB_CLK 15 +#define CAM_CC_CPAS_BPS_CLK 16 +#define CAM_CC_CPAS_CRE_CLK 17 +#define CAM_CC_CPAS_FAST_AHB_CLK 18 +#define CAM_CC_CPAS_IFE_0_CLK 19 +#define CAM_CC_CPAS_IFE_1_CLK 20 +#define CAM_CC_CPAS_IFE_2_CLK 21 +#define CAM_CC_CPAS_IFE_LITE_CLK 22 +#define CAM_CC_CPAS_IPE_NPS_CLK 23 +#define CAM_CC_CPAS_SBI_CLK 24 +#define CAM_CC_CPAS_SFE_0_CLK 25 +#define CAM_CC_CPAS_SFE_1_CLK 26 +#define CAM_CC_CPHY_RX_CLK_SRC 27 +#define CAM_CC_CRE_AHB_CLK 28 +#define CAM_CC_CRE_CLK 29 +#define CAM_CC_CRE_CLK_SRC 30 +#define CAM_CC_CSI0PHYTIMER_CLK 31 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 32 +#define CAM_CC_CSI1PHYTIMER_CLK 33 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 34 +#define CAM_CC_CSI2PHYTIMER_CLK 35 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 36 +#define CAM_CC_CSI3PHYTIMER_CLK 37 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC 38 +#define CAM_CC_CSI4PHYTIMER_CLK 39 +#define CAM_CC_CSI4PHYTIMER_CLK_SRC 40 +#define CAM_CC_CSI5PHYTIMER_CLK 41 +#define CAM_CC_CSI5PHYTIMER_CLK_SRC 42 +#define CAM_CC_CSI6PHYTIMER_CLK 43 +#define CAM_CC_CSI6PHYTIMER_CLK_SRC 44 +#define CAM_CC_CSI7PHYTIMER_CLK 45 +#define CAM_CC_CSI7PHYTIMER_CLK_SRC 46 +#define CAM_CC_CSID_CLK 47 +#define CAM_CC_CSID_CLK_SRC 48 +#define CAM_CC_CSID_CSIPHY_RX_CLK 49 +#define CAM_CC_CSIPHY0_CLK 50 +#define CAM_CC_CSIPHY1_CLK 51 +#define CAM_CC_CSIPHY2_CLK 52 +#define CAM_CC_CSIPHY3_CLK 53 +#define CAM_CC_CSIPHY4_CLK 54 +#define CAM_CC_CSIPHY5_CLK 55 +#define CAM_CC_CSIPHY6_CLK 56 +#define CAM_CC_CSIPHY7_CLK 57 +#define CAM_CC_DRV_AHB_CLK 58 +#define CAM_CC_DRV_XO_CLK 59 +#define CAM_CC_FAST_AHB_CLK_SRC 60 +#define CAM_CC_GDSC_CLK 61 +#define CAM_CC_ICP_AHB_CLK 62 +#define CAM_CC_ICP_CLK 63 +#define CAM_CC_ICP_CLK_SRC 64 +#define CAM_CC_IFE_0_CLK 65 +#define CAM_CC_IFE_0_CLK_SRC 66 +#define CAM_CC_IFE_0_DSP_CLK 67 +#define CAM_CC_IFE_0_DSP_CLK_SRC 68 +#define CAM_CC_IFE_0_FAST_AHB_CLK 69 +#define CAM_CC_IFE_1_CLK 70 +#define CAM_CC_IFE_1_CLK_SRC 71 +#define CAM_CC_IFE_1_DSP_CLK 72 +#define CAM_CC_IFE_1_DSP_CLK_SRC 73 +#define CAM_CC_IFE_1_FAST_AHB_CLK 74 +#define CAM_CC_IFE_2_CLK 75 +#define CAM_CC_IFE_2_CLK_SRC 76 +#define CAM_CC_IFE_2_DSP_CLK 77 +#define CAM_CC_IFE_2_DSP_CLK_SRC 78 +#define CAM_CC_IFE_2_FAST_AHB_CLK 79 +#define CAM_CC_IFE_LITE_AHB_CLK 80 +#define CAM_CC_IFE_LITE_CLK 81 +#define CAM_CC_IFE_LITE_CLK_SRC 82 +#define CAM_CC_IFE_LITE_CPHY_RX_CLK 83 +#define CAM_CC_IFE_LITE_CSID_CLK 84 +#define CAM_CC_IFE_LITE_CSID_CLK_SRC 85 +#define CAM_CC_IPE_NPS_AHB_CLK 86 +#define CAM_CC_IPE_NPS_CLK 87 +#define CAM_CC_IPE_NPS_CLK_SRC 88 +#define CAM_CC_IPE_NPS_FAST_AHB_CLK 89 +#define CAM_CC_IPE_PPS_CLK 90 +#define CAM_CC_IPE_PPS_FAST_AHB_CLK 91 +#define CAM_CC_JPEG_1_CLK 92 +#define CAM_CC_JPEG_CLK 93 +#define CAM_CC_JPEG_CLK_SRC 94 +#define CAM_CC_MCLK0_CLK 95 +#define CAM_CC_MCLK0_CLK_SRC 96 +#define CAM_CC_MCLK1_CLK 97 +#define CAM_CC_MCLK1_CLK_SRC 98 +#define CAM_CC_MCLK2_CLK 99 +#define CAM_CC_MCLK2_CLK_SRC 100 +#define CAM_CC_MCLK3_CLK 101 +#define CAM_CC_MCLK3_CLK_SRC 102 +#define CAM_CC_MCLK4_CLK 103 +#define CAM_CC_MCLK4_CLK_SRC 104 +#define CAM_CC_MCLK5_CLK 105 +#define CAM_CC_MCLK5_CLK_SRC 106 +#define CAM_CC_MCLK6_CLK 107 +#define CAM_CC_MCLK6_CLK_SRC 108 +#define CAM_CC_MCLK7_CLK 109 +#define CAM_CC_MCLK7_CLK_SRC 110 +#define CAM_CC_PLL0 111 +#define CAM_CC_PLL0_OUT_EVEN 112 +#define CAM_CC_PLL0_OUT_ODD 113 +#define CAM_CC_PLL1 114 +#define CAM_CC_PLL10 115 +#define CAM_CC_PLL10_OUT_EVEN 116 +#define CAM_CC_PLL11 117 +#define CAM_CC_PLL11_OUT_EVEN 118 +#define CAM_CC_PLL12 119 +#define CAM_CC_PLL12_OUT_EVEN 120 +#define CAM_CC_PLL1_OUT_EVEN 121 +#define CAM_CC_PLL2 122 +#define CAM_CC_PLL3 123 +#define CAM_CC_PLL3_OUT_EVEN 124 +#define CAM_CC_PLL4 125 +#define CAM_CC_PLL4_OUT_EVEN 126 +#define CAM_CC_PLL5 127 +#define CAM_CC_PLL5_OUT_EVEN 128 +#define CAM_CC_PLL6 129 +#define CAM_CC_PLL6_OUT_EVEN 130 +#define CAM_CC_PLL7 131 +#define CAM_CC_PLL7_OUT_EVEN 132 +#define CAM_CC_PLL8 133 +#define CAM_CC_PLL8_OUT_EVEN 134 +#define CAM_CC_PLL9 135 +#define CAM_CC_PLL9_OUT_EVEN 136 +#define CAM_CC_QDSS_DEBUG_CLK 137 +#define CAM_CC_QDSS_DEBUG_CLK_SRC 138 +#define CAM_CC_QDSS_DEBUG_XO_CLK 139 +#define CAM_CC_SBI_CLK 140 +#define CAM_CC_SBI_FAST_AHB_CLK 141 +#define CAM_CC_SFE_0_CLK 142 +#define CAM_CC_SFE_0_CLK_SRC 143 +#define CAM_CC_SFE_0_FAST_AHB_CLK 144 +#define CAM_CC_SFE_1_CLK 145 +#define CAM_CC_SFE_1_CLK_SRC 146 +#define CAM_CC_SFE_1_FAST_AHB_CLK 147 +#define CAM_CC_SLEEP_CLK 148 +#define CAM_CC_SLEEP_CLK_SRC 149 +#define CAM_CC_SLOW_AHB_CLK_SRC 150 +#define CAM_CC_XO_CLK_SRC 151 + +/* CAM_CC resets */ +#define CAM_CC_BPS_BCR 0 +#define CAM_CC_DRV_BCR 1 +#define CAM_CC_ICP_BCR 2 +#define CAM_CC_IFE_0_BCR 3 +#define CAM_CC_IFE_1_BCR 4 +#define CAM_CC_IFE_2_BCR 5 +#define CAM_CC_IPE_0_BCR 6 +#define CAM_CC_QDSS_DEBUG_BCR 7 +#define CAM_CC_SBI_BCR 8 +#define CAM_CC_SFE_0_BCR 9 +#define CAM_CC_SFE_1_BCR 10 + +#endif diff --git a/include/dt-bindings/clock/qcom,dispcc-kalama.h b/include/dt-bindings/clock/qcom,dispcc-kalama.h new file mode 100644 index 000000000000..bc886312d4e1 --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-kalama.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_KALAMA_H +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_KALAMA_H + +/* DISP_CC clocks */ +#define DISP_CC_MDSS_ACCU_CLK 0 +#define DISP_CC_MDSS_AHB1_CLK 1 +#define DISP_CC_MDSS_AHB_CLK 2 +#define DISP_CC_MDSS_AHB_CLK_SRC 3 +#define DISP_CC_MDSS_BYTE0_CLK 4 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 5 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 7 +#define DISP_CC_MDSS_BYTE1_CLK 8 +#define DISP_CC_MDSS_BYTE1_CLK_SRC 9 +#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 10 +#define DISP_CC_MDSS_BYTE1_INTF_CLK 11 +#define DISP_CC_MDSS_DPTX0_AUX_CLK 12 +#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 13 +#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 14 +#define DISP_CC_MDSS_DPTX0_LINK_CLK 15 +#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 16 +#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 17 +#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 18 +#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 19 +#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 20 +#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 21 +#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 22 +#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 23 +#define DISP_CC_MDSS_DPTX1_AUX_CLK 24 +#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 25 +#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 26 +#define DISP_CC_MDSS_DPTX1_LINK_CLK 27 +#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 28 +#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 29 +#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 30 +#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 31 +#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 32 +#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 33 +#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 34 +#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 35 +#define DISP_CC_MDSS_DPTX2_AUX_CLK 36 +#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 37 +#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 38 +#define DISP_CC_MDSS_DPTX2_LINK_CLK 39 +#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 40 +#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 41 +#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 42 +#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 43 +#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 44 +#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 45 +#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 46 +#define DISP_CC_MDSS_DPTX3_AUX_CLK 47 +#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 48 +#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 49 +#define DISP_CC_MDSS_DPTX3_LINK_CLK 50 +#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 51 +#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 52 +#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 53 +#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 54 +#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 55 +#define DISP_CC_MDSS_ESC0_CLK 56 +#define DISP_CC_MDSS_ESC0_CLK_SRC 57 +#define DISP_CC_MDSS_ESC1_CLK 58 +#define DISP_CC_MDSS_ESC1_CLK_SRC 59 +#define DISP_CC_MDSS_MDP1_CLK 60 +#define DISP_CC_MDSS_MDP_CLK 61 +#define DISP_CC_MDSS_MDP_CLK_SRC 62 +#define DISP_CC_MDSS_MDP_LUT1_CLK 63 +#define DISP_CC_MDSS_MDP_LUT_CLK 64 +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 65 +#define DISP_CC_MDSS_PCLK0_CLK 66 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 67 +#define DISP_CC_MDSS_PCLK1_CLK 68 +#define DISP_CC_MDSS_PCLK1_CLK_SRC 69 +#define DISP_CC_MDSS_RSCC_AHB_CLK 70 +#define DISP_CC_MDSS_RSCC_VSYNC_CLK 71 +#define DISP_CC_MDSS_VSYNC1_CLK 72 +#define DISP_CC_MDSS_VSYNC_CLK 73 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 74 +#define DISP_CC_PLL0 75 +#define DISP_CC_PLL1 76 +#define DISP_CC_SLEEP_CLK 77 +#define DISP_CC_SLEEP_CLK_SRC 78 +#define DISP_CC_XO_CLK 79 +#define DISP_CC_XO_CLK_SRC 80 + +/* DISP_CC resets */ +#define DISP_CC_MDSS_CORE_BCR 0 +#define DISP_CC_MDSS_CORE_INT2_BCR 1 +#define DISP_CC_MDSS_RSCC_BCR 2 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-kalama.h b/include/dt-bindings/clock/qcom,gcc-kalama.h new file mode 100644 index 000000000000..e7e6ada4e19b --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-kalama.h @@ -0,0 +1,220 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_KALAMA_H +#define _DT_BINDINGS_CLK_QCOM_GCC_KALAMA_H + +/* GCC clocks */ +#define GCC_AGGRE_NOC_PCIE_AXI_CLK 0 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 1 +#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 2 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3 +#define GCC_AHB2PHY_0_CLK 4 +#define GCC_BOOT_ROM_AHB_CLK 5 +#define GCC_CAMERA_AHB_CLK 6 +#define GCC_CAMERA_HF_AXI_CLK 7 +#define GCC_CAMERA_SF_AXI_CLK 8 +#define GCC_CAMERA_XO_CLK 9 +#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 10 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 11 +#define GCC_CNOC_PCIE_SF_AXI_CLK 12 +#define GCC_DDRSS_GPU_AXI_CLK 13 +#define GCC_DDRSS_PCIE_SF_QTB_CLK 14 +#define GCC_DISP_AHB_CLK 15 +#define GCC_DISP_HF_AXI_CLK 16 +#define GCC_DISP_XO_CLK 17 +#define GCC_GP1_CLK 18 +#define GCC_GP1_CLK_SRC 19 +#define GCC_GP2_CLK 20 +#define GCC_GP2_CLK_SRC 21 +#define GCC_GP3_CLK 22 +#define GCC_GP3_CLK_SRC 23 +#define GCC_GPLL0 24 +#define GCC_GPLL0_OUT_EVEN 25 +#define GCC_GPLL4 26 +#define GCC_GPLL7 27 +#define GCC_GPLL9 28 +#define GCC_GPU_CFG_AHB_CLK 29 +#define GCC_GPU_GPLL0_CLK_SRC 30 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 31 +#define GCC_GPU_MEMNOC_GFX_CLK 32 +#define GCC_GPU_SNOC_DVM_GFX_CLK 33 +#define GCC_PCIE_0_AUX_CLK 34 +#define GCC_PCIE_0_AUX_CLK_SRC 35 +#define GCC_PCIE_0_CFG_AHB_CLK 36 +#define GCC_PCIE_0_MSTR_AXI_CLK 37 +#define GCC_PCIE_0_PHY_RCHNG_CLK 38 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 39 +#define GCC_PCIE_0_PIPE_CLK 40 +#define GCC_PCIE_0_PIPE_CLK_SRC 41 +#define GCC_PCIE_0_SLV_AXI_CLK 42 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 43 +#define GCC_PCIE_1_AUX_CLK 44 +#define GCC_PCIE_1_AUX_CLK_SRC 45 +#define GCC_PCIE_1_CFG_AHB_CLK 46 +#define GCC_PCIE_1_MSTR_AXI_CLK 47 +#define GCC_PCIE_1_PHY_AUX_CLK 48 +#define GCC_PCIE_1_PHY_AUX_CLK_SRC 49 +#define GCC_PCIE_1_PHY_RCHNG_CLK 50 +#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 51 +#define GCC_PCIE_1_PIPE_CLK 52 +#define GCC_PCIE_1_PIPE_CLK_SRC 53 +#define GCC_PCIE_1_SLV_AXI_CLK 54 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 55 +#define GCC_PDM2_CLK 56 +#define GCC_PDM2_CLK_SRC 57 +#define GCC_PDM_AHB_CLK 58 +#define GCC_PDM_XO4_CLK 59 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 60 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 61 +#define GCC_QMIP_DISP_AHB_CLK 62 +#define GCC_QMIP_GPU_AHB_CLK 63 +#define GCC_QMIP_PCIE_AHB_CLK 64 +#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 65 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 66 +#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 67 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 68 +#define GCC_QUPV3_I2C_CORE_CLK 69 +#define GCC_QUPV3_I2C_S0_CLK 70 +#define GCC_QUPV3_I2C_S0_CLK_SRC 71 +#define GCC_QUPV3_I2C_S1_CLK 72 +#define GCC_QUPV3_I2C_S1_CLK_SRC 73 +#define GCC_QUPV3_I2C_S2_CLK 74 +#define GCC_QUPV3_I2C_S2_CLK_SRC 75 +#define GCC_QUPV3_I2C_S3_CLK 76 +#define GCC_QUPV3_I2C_S3_CLK_SRC 77 +#define GCC_QUPV3_I2C_S4_CLK 78 +#define GCC_QUPV3_I2C_S4_CLK_SRC 79 +#define GCC_QUPV3_I2C_S5_CLK 80 +#define GCC_QUPV3_I2C_S5_CLK_SRC 81 +#define GCC_QUPV3_I2C_S6_CLK 82 +#define GCC_QUPV3_I2C_S6_CLK_SRC 83 +#define GCC_QUPV3_I2C_S7_CLK 84 +#define GCC_QUPV3_I2C_S7_CLK_SRC 85 +#define GCC_QUPV3_I2C_S8_CLK 86 +#define GCC_QUPV3_I2C_S8_CLK_SRC 87 +#define GCC_QUPV3_I2C_S9_CLK 88 +#define GCC_QUPV3_I2C_S9_CLK_SRC 89 +#define GCC_QUPV3_I2C_S_AHB_CLK 90 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 91 +#define GCC_QUPV3_WRAP1_CORE_CLK 92 +#define GCC_QUPV3_WRAP1_S0_CLK 93 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 94 +#define GCC_QUPV3_WRAP1_S1_CLK 95 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 96 +#define GCC_QUPV3_WRAP1_S2_CLK 97 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 98 +#define GCC_QUPV3_WRAP1_S3_CLK 99 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 100 +#define GCC_QUPV3_WRAP1_S4_CLK 101 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 102 +#define GCC_QUPV3_WRAP1_S5_CLK 103 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 104 +#define GCC_QUPV3_WRAP1_S6_CLK 105 +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 106 +#define GCC_QUPV3_WRAP1_S7_CLK 107 +#define GCC_QUPV3_WRAP1_S7_CLK_SRC 108 +#define GCC_QUPV3_WRAP2_CORE_2X_CLK 109 +#define GCC_QUPV3_WRAP2_CORE_CLK 110 +#define GCC_QUPV3_WRAP2_S0_CLK 111 +#define GCC_QUPV3_WRAP2_S0_CLK_SRC 112 +#define GCC_QUPV3_WRAP2_S1_CLK 113 +#define GCC_QUPV3_WRAP2_S1_CLK_SRC 114 +#define GCC_QUPV3_WRAP2_S2_CLK 115 +#define GCC_QUPV3_WRAP2_S2_CLK_SRC 116 +#define GCC_QUPV3_WRAP2_S3_CLK 117 +#define GCC_QUPV3_WRAP2_S3_CLK_SRC 118 +#define GCC_QUPV3_WRAP2_S4_CLK 119 +#define GCC_QUPV3_WRAP2_S4_CLK_SRC 120 +#define GCC_QUPV3_WRAP2_S5_CLK 121 +#define GCC_QUPV3_WRAP2_S5_CLK_SRC 122 +#define GCC_QUPV3_WRAP2_S6_CLK 123 +#define GCC_QUPV3_WRAP2_S6_CLK_SRC 124 +#define GCC_QUPV3_WRAP2_S7_CLK 125 +#define GCC_QUPV3_WRAP2_S7_CLK_SRC 126 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 127 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 128 +#define GCC_QUPV3_WRAP_2_M_AHB_CLK 129 +#define GCC_QUPV3_WRAP_2_S_AHB_CLK 130 +#define GCC_SDCC2_AHB_CLK 131 +#define GCC_SDCC2_APPS_CLK 132 +#define GCC_SDCC2_APPS_CLK_SRC 133 +#define GCC_SDCC4_AHB_CLK 134 +#define GCC_SDCC4_APPS_CLK 135 +#define GCC_SDCC4_APPS_CLK_SRC 136 +#define GCC_UFS_PHY_AHB_CLK 137 +#define GCC_UFS_PHY_AXI_CLK 138 +#define GCC_UFS_PHY_AXI_CLK_SRC 139 +#define GCC_UFS_PHY_AXI_HW_CTL_CLK 140 +#define GCC_UFS_PHY_ICE_CORE_CLK 141 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 142 +#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 143 +#define GCC_UFS_PHY_PHY_AUX_CLK 144 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 145 +#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 146 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 147 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 148 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 149 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 150 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 151 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 152 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 153 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 154 +#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 155 +#define GCC_USB30_PRIM_MASTER_CLK 156 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 157 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 158 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 159 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 160 +#define GCC_USB30_PRIM_SLEEP_CLK 161 +#define GCC_USB3_PRIM_PHY_AUX_CLK 162 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 163 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 164 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 165 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 166 +#define GCC_VIDEO_AHB_CLK 167 +#define GCC_VIDEO_AXI0_CLK 168 +#define GCC_VIDEO_AXI1_CLK 169 +#define GCC_VIDEO_XO_CLK 170 + +/* GCC resets */ +#define GCC_CAMERA_BCR 0 +#define GCC_DISPLAY_BCR 1 +#define GCC_GPU_BCR 2 +#define GCC_PCIE_0_BCR 3 +#define GCC_PCIE_0_LINK_DOWN_BCR 4 +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5 +#define GCC_PCIE_0_PHY_BCR 6 +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7 +#define GCC_PCIE_1_BCR 8 +#define GCC_PCIE_1_LINK_DOWN_BCR 9 +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 10 +#define GCC_PCIE_1_PHY_BCR 11 +#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 12 +#define GCC_PCIE_PHY_BCR 13 +#define GCC_PCIE_PHY_CFG_AHB_BCR 14 +#define GCC_PCIE_PHY_COM_BCR 15 +#define GCC_PDM_BCR 16 +#define GCC_QUPV3_WRAPPER_1_BCR 17 +#define GCC_QUPV3_WRAPPER_2_BCR 18 +#define GCC_QUPV3_WRAPPER_I2C_BCR 19 +#define GCC_QUSB2PHY_PRIM_BCR 20 +#define GCC_QUSB2PHY_SEC_BCR 21 +#define GCC_SDCC2_BCR 22 +#define GCC_SDCC4_BCR 23 +#define GCC_UFS_PHY_BCR 24 +#define GCC_USB30_PRIM_BCR 25 +#define GCC_USB3_DP_PHY_PRIM_BCR 26 +#define GCC_USB3_DP_PHY_SEC_BCR 27 +#define GCC_USB3_PHY_PRIM_BCR 28 +#define GCC_USB3_PHY_SEC_BCR 29 +#define GCC_USB3PHY_PHY_PRIM_BCR 30 +#define GCC_USB3PHY_PHY_SEC_BCR 31 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 32 +#define GCC_VIDEO_AXI0_CLK_ARES 33 +#define GCC_VIDEO_AXI1_CLK_ARES 34 +#define GCC_VIDEO_BCR 35 + +#endif diff --git a/include/dt-bindings/clock/qcom,gpucc-kalama.h b/include/dt-bindings/clock/qcom,gpucc-kalama.h new file mode 100644 index 000000000000..851e149fb401 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-kalama.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_KALAMA_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_KALAMA_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CRC_AHB_CLK 1 +#define GPU_CC_CX_FF_CLK 2 +#define GPU_CC_CX_GMU_CLK 3 +#define GPU_CC_CXO_AON_CLK 4 +#define GPU_CC_CXO_CLK 5 +#define GPU_CC_DEMET_CLK 6 +#define GPU_CC_FF_CLK_SRC 7 +#define GPU_CC_FREQ_MEASURE_CLK 8 +#define GPU_CC_GMU_CLK_SRC 9 +#define GPU_CC_GX_FF_CLK 10 +#define GPU_CC_GX_GFX3D_CLK 11 +#define GPU_CC_GX_GFX3D_RDVM_CLK 12 +#define GPU_CC_GX_GMU_CLK 13 +#define GPU_CC_GX_VSENSE_CLK 14 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 15 +#define GPU_CC_HUB_AON_CLK 16 +#define GPU_CC_HUB_CLK_SRC 17 +#define GPU_CC_HUB_CX_INT_CLK 18 +#define GPU_CC_MEMNOC_GFX_CLK 19 +#define GPU_CC_MND1X_0_GFX3D_CLK 20 +#define GPU_CC_MND1X_1_GFX3D_CLK 21 +#define GPU_CC_PLL0 22 +#define GPU_CC_PLL1 23 +#define GPU_CC_SLEEP_CLK 24 + +/* GPU_CC resets */ +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CX_BCR 1 +#define GPUCC_GPU_CC_FAST_HUB_BCR 2 +#define GPUCC_GPU_CC_FF_BCR 3 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 4 +#define GPUCC_GPU_CC_GMU_BCR 5 +#define GPUCC_GPU_CC_GX_BCR 6 +#define GPUCC_GPU_CC_XO_BCR 7 + +#endif diff --git a/include/dt-bindings/clock/qcom,rpmh.h b/include/dt-bindings/clock/qcom,rpmh.h index f3e0288420ce..aebed7816862 100644 --- a/include/dt-bindings/clock/qcom,rpmh.h +++ b/include/dt-bindings/clock/qcom,rpmh.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved. */ +/* Copyright (c) 2018, 2020 The Linux Foundation. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_MSM_RPMH_H diff --git a/include/dt-bindings/clock/qcom,tcsrcc-kalama.h b/include/dt-bindings/clock/qcom,tcsrcc-kalama.h new file mode 100644 index 000000000000..a5af037a6b36 --- /dev/null +++ b/include/dt-bindings/clock/qcom,tcsrcc-kalama.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_KALAMA_H +#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_KALAMA_H + +/* TCSR_CC clocks */ +#define TCSR_PCIE_0_CLKREF_EN 0 +#define TCSR_PCIE_1_CLKREF_EN 1 +#define TCSR_UFS_CLKREF_EN 2 +#define TCSR_UFS_PAD_CLKREF_EN 3 +#define TCSR_USB2_CLKREF_EN 4 +#define TCSR_USB3_CLKREF_EN 5 + +#endif diff --git a/include/dt-bindings/clock/qcom,videocc-kalama.h b/include/dt-bindings/clock/qcom,videocc-kalama.h new file mode 100644 index 000000000000..eccef4407bd9 --- /dev/null +++ b/include/dt-bindings/clock/qcom,videocc-kalama.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_KALAMA_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_KALAMA_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_AHB_CLK 0 +#define VIDEO_CC_AHB_CLK_SRC 1 +#define VIDEO_CC_MVS0_CLK 2 +#define VIDEO_CC_MVS0_CLK_SRC 3 +#define VIDEO_CC_MVS0_DIV_CLK_SRC 4 +#define VIDEO_CC_MVS0C_CLK 5 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 6 +#define VIDEO_CC_MVS1_CLK 7 +#define VIDEO_CC_MVS1_CLK_SRC 8 +#define VIDEO_CC_MVS1_DIV_CLK_SRC 9 +#define VIDEO_CC_MVS1C_CLK 10 +#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 11 +#define VIDEO_CC_PLL0 12 +#define VIDEO_CC_PLL1 13 +#define VIDEO_CC_SLEEP_CLK 14 +#define VIDEO_CC_SLEEP_CLK_SRC 15 +#define VIDEO_CC_XO_CLK 16 +#define VIDEO_CC_XO_CLK_SRC 17 + +/* VIDEO_CC resets */ +#define CVP_VIDEO_CC_INTERFACE_BCR 0 +#define CVP_VIDEO_CC_MVS0_BCR 1 +#define VIDEO_CC_MVS0C_CLK_ARES 2 +#define CVP_VIDEO_CC_MVS0C_BCR 3 +#define CVP_VIDEO_CC_MVS1_BCR 4 +#define VIDEO_CC_MVS1C_CLK_ARES 5 +#define CVP_VIDEO_CC_MVS1C_BCR 6 + +#endif diff --git a/include/dt-bindings/input/qcom,hv-haptics.h b/include/dt-bindings/input/qcom,hv-haptics.h index b39c24d5ccb8..8453d2ae9de6 100644 --- a/include/dt-bindings/input/qcom,hv-haptics.h +++ b/include/dt-bindings/input/qcom,hv-haptics.h @@ -30,7 +30,7 @@ #define S_PERIOD_T_LRA_X_8 6 /* F_8KHZ to F_48KHZ periods can only be specified for FIFO based effects */ #define S_PERIOD_F_8KHZ 8 -#define S_PERIOD_F_16HKZ 9 +#define S_PERIOD_F_16KHZ 9 #define S_PERIOD_F_24KHZ 10 #define S_PERIOD_F_32KHZ 11 #define S_PERIOD_F_44P1KHZ 12 diff --git a/include/dt-bindings/interconnect/qcom,kalama.h b/include/dt-bindings/interconnect/qcom,kalama.h new file mode 100644 index 000000000000..5c95af0e05cf --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,kalama.h @@ -0,0 +1,175 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_KALAMA_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_KALAMA_H + +#define MASTER_GPU_TCU 0 +#define MASTER_SYS_TCU 1 +#define MASTER_APPSS_PROC 2 +#define MASTER_LLCC 3 +#define MASTER_GIC_AHB 4 +#define MASTER_QDSS_BAM 5 +#define MASTER_QSPI_0 6 +#define MASTER_QUP_1 7 +#define MASTER_QUP_2 8 +#define MASTER_A1NOC_SNOC 9 +#define MASTER_A2NOC_SNOC 10 +#define MASTER_CAMNOC_HF 11 +#define MASTER_CAMNOC_ICP 12 +#define MASTER_CAMNOC_SF 13 +#define MASTER_GEM_NOC_CNOC 14 +#define MASTER_GEM_NOC_PCIE_SNOC 15 +#define MASTER_GFX3D 16 +#define MASTER_LPASS_GEM_NOC 17 +#define MASTER_LPASS_LPINOC 18 +#define MASTER_LPIAON_NOC 19 +#define MASTER_MDP 20 +#define MASTER_MSS_PROC 21 +#define MASTER_MNOC_HF_MEM_NOC 22 +#define MASTER_MNOC_SF_MEM_NOC 23 +#define MASTER_COMPUTE_NOC 24 +#define MASTER_ANOC_PCIE_GEM_NOC 25 +#define MASTER_SNOC_GC_MEM_NOC 26 +#define MASTER_SNOC_SF_MEM_NOC 27 +#define MASTER_CDSP_HCP 28 +#define MASTER_VIDEO 29 +#define MASTER_VIDEO_CV_PROC 30 +#define MASTER_VIDEO_PROC 31 +#define MASTER_VIDEO_V_PROC 32 +#define MASTER_CNOC_CFG 33 +#define MASTER_CNOC_MNOC_CFG 34 +#define MASTER_PCIE_ANOC_CFG 35 +#define MASTER_QUP_CORE_0 36 +#define MASTER_QUP_CORE_1 37 +#define MASTER_QUP_CORE_2 38 +#define MASTER_CRYPTO 39 +#define MASTER_IPA 40 +#define MASTER_LPASS_PROC 41 +#define MASTER_CDSP_PROC 42 +#define MASTER_SP 43 +#define MASTER_GIC 44 +#define MASTER_PCIE_0 45 +#define MASTER_PCIE_1 46 +#define MASTER_QDSS_ETR 47 +#define MASTER_QDSS_ETR_1 48 +#define MASTER_SDCC_2 49 +#define MASTER_SDCC_4 50 +#define MASTER_UFS_MEM 51 +#define MASTER_USB3_0 52 +#define SLAVE_EBI1 512 +#define SLAVE_AHB2PHY_SOUTH 513 +#define SLAVE_AHB2PHY_NORTH 514 +#define SLAVE_AOSS 515 +#define SLAVE_APPSS 516 +#define SLAVE_CAMERA_CFG 517 +#define SLAVE_CLK_CTL 518 +#define SLAVE_RBCPR_CX_CFG 519 +#define SLAVE_RBCPR_MMCX_CFG 520 +#define SLAVE_RBCPR_MXA_CFG 521 +#define SLAVE_RBCPR_MXC_CFG 522 +#define SLAVE_CPR_NSPCX 523 +#define SLAVE_CRYPTO_0_CFG 524 +#define SLAVE_CX_RDPM 525 +#define SLAVE_DISPLAY_CFG 526 +#define SLAVE_GFX3D_CFG 527 +#define SLAVE_I2C 528 +#define SLAVE_IMEM_CFG 529 +#define SLAVE_IPA_CFG 530 +#define SLAVE_IPC_ROUTER_CFG 531 +#define SLAVE_CNOC_MSS 532 +#define SLAVE_MX_RDPM 533 +#define SLAVE_PCIE_0_CFG 534 +#define SLAVE_PCIE_1_CFG 535 +#define SLAVE_PDM 536 +#define SLAVE_PIMEM_CFG 537 +#define SLAVE_PRNG 538 +#define SLAVE_QDSS_CFG 539 +#define SLAVE_QSPI_0 540 +#define SLAVE_QUP_1 541 +#define SLAVE_QUP_2 542 +#define SLAVE_SDCC_2 543 +#define SLAVE_SDCC_4 544 +#define SLAVE_SPSS_CFG 545 +#define SLAVE_TCSR 546 +#define SLAVE_TLMM 547 +#define SLAVE_TME_CFG 548 +#define SLAVE_UFS_MEM_CFG 549 +#define SLAVE_USB3_0 550 +#define SLAVE_VENUS_CFG 551 +#define SLAVE_VSENSE_CTRL_CFG 552 +#define SLAVE_A1NOC_SNOC 553 +#define SLAVE_A2NOC_SNOC 554 +#define SLAVE_GEM_NOC_CNOC 555 +#define SLAVE_SNOC_GEM_NOC_GC 556 +#define SLAVE_SNOC_GEM_NOC_SF 557 +#define SLAVE_LLCC 558 +#define SLAVE_LPASS_GEM_NOC 559 +#define SLAVE_LPIAON_NOC_LPASS_AG_NOC 560 +#define SLAVE_LPICX_NOC_LPIAON_NOC 561 +#define SLAVE_MNOC_HF_MEM_NOC 562 +#define SLAVE_MNOC_SF_MEM_NOC 563 +#define SLAVE_CDSP_MEM_NOC 564 +#define SLAVE_MEM_NOC_PCIE_SNOC 565 +#define SLAVE_ANOC_PCIE_GEM_NOC 566 +#define SLAVE_CNOC_CFG 567 +#define SLAVE_DDRSS_CFG 568 +#define SLAVE_LPASS_QTB_CFG 569 +#define SLAVE_CNOC_MNOC_CFG 570 +#define SLAVE_NSP_QTB_CFG 571 +#define SLAVE_PCIE_ANOC_CFG 572 +#define SLAVE_QUP_CORE_0 573 +#define SLAVE_QUP_CORE_1 574 +#define SLAVE_QUP_CORE_2 575 +#define SLAVE_BOOT_IMEM 576 +#define SLAVE_IMEM 577 +#define SLAVE_SERVICE_MNOC 578 +#define SLAVE_SERVICE_PCIE_ANOC 579 +#define SLAVE_PCIE_0 580 +#define SLAVE_PCIE_1 581 +#define SLAVE_QDSS_STM 582 +#define SLAVE_TCU 583 +#define MASTER_LLCC_DISP 1000 +#define MASTER_MDP_DISP 1001 +#define MASTER_MNOC_HF_MEM_NOC_DISP 1002 +#define MASTER_ANOC_PCIE_GEM_NOC_DISP 1003 +#define SLAVE_EBI1_DISP 1512 +#define SLAVE_LLCC_DISP 1513 +#define SLAVE_MNOC_HF_MEM_NOC_DISP 1514 +#define MASTER_LLCC_CAM_IFE_0 2000 +#define MASTER_CAMNOC_HF_CAM_IFE_0 2001 +#define MASTER_CAMNOC_ICP_CAM_IFE_0 2002 +#define MASTER_CAMNOC_SF_CAM_IFE_0 2003 +#define MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0 2004 +#define MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0 2005 +#define MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_0 2006 +#define SLAVE_EBI1_CAM_IFE_0 2512 +#define SLAVE_LLCC_CAM_IFE_0 2513 +#define SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0 2514 +#define SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0 2515 +#define MASTER_LLCC_CAM_IFE_1 3000 +#define MASTER_CAMNOC_HF_CAM_IFE_1 3001 +#define MASTER_CAMNOC_ICP_CAM_IFE_1 3002 +#define MASTER_CAMNOC_SF_CAM_IFE_1 3003 +#define MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1 3004 +#define MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1 3005 +#define MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_1 3006 +#define SLAVE_EBI1_CAM_IFE_1 3512 +#define SLAVE_LLCC_CAM_IFE_1 3513 +#define SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1 3514 +#define SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1 3515 +#define MASTER_LLCC_CAM_IFE_2 4000 +#define MASTER_CAMNOC_HF_CAM_IFE_2 4001 +#define MASTER_CAMNOC_ICP_CAM_IFE_2 4002 +#define MASTER_CAMNOC_SF_CAM_IFE_2 4003 +#define MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2 4004 +#define MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2 4005 +#define MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2 4006 +#define SLAVE_EBI1_CAM_IFE_2 4512 +#define SLAVE_LLCC_CAM_IFE_2 4513 +#define SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2 4514 +#define SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2 4515 + +#endif diff --git a/include/dt-bindings/phy/qcom,usb3-4nm-qmp-combo.h b/include/dt-bindings/phy/qcom,usb3-4nm-qmp-combo.h new file mode 100644 index 000000000000..3c0845bca908 --- /dev/null +++ b/include/dt-bindings/phy/qcom,usb3-4nm-qmp-combo.h @@ -0,0 +1,810 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + */ +#ifndef _DT_BINDINGS_PHY_QCOM_4NM_QMP_COMBO_USB_H +#define _DT_BINDINGS_PHY_QCOM_4NM_QMP_COMBO_USB_H + +/* USB3-DP Combo PHY register offsets */ +/* Module: USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM */ +#define USB3_DP_COM_PHY_MODE_CTRL 0x0000 +#define USB3_DP_COM_SW_RESET 0x0004 +#define USB3_DP_COM_POWER_DOWN_CTRL 0x0008 +#define USB3_DP_COM_SWI_CTRL 0x000C +#define USB3_DP_COM_TYPEC_CTRL 0x0010 +#define USB3_DP_COM_TYPEC_PWRDN_CTRL 0x0014 +#define USB3_DP_COM_DP_BIST_CFG_0 0x0018 +#define USB3_DP_COM_RESET_OVRD_CTRL 0x001C +#define USB3_DP_COM_DBG_CLK_MUX_CTRL 0x0020 +#define USB3_DP_COM_TYPEC_STATUS 0x0024 +#define USB3_DP_COM_PLACEHOLDER_STATUS 0x0028 +#define USB3_DP_COM_REVISION_ID0 0x002C +#define USB3_DP_COM_REVISION_ID1 0x0030 +#define USB3_DP_COM_REVISION_ID2 0x0034 +#define USB3_DP_COM_REVISION_ID3 0x0038 + +/* Module: USB3_DP_PHY_USB3_DP_DBGINT_USB3_DP_DBGINT_USB3_PCS_DEBUG_INT */ +#define USB3_DP_DBGINT_INTGEN_STATUS1 0x0200 +#define USB3_DP_DBGINT_INTGEN_STATUS2 0x0204 +#define USB3_DP_DBGINT_CONFIG1 0x0208 +#define USB3_DP_DBGINT_SIGNALBLK1_CONFIG1 0x020C +#define USB3_DP_DBGINT_SIGNALBLK1_CONFIG2 0x0210 +#define USB3_DP_DBGINT_SIGNALBLK1_CONFIG3 0x0214 +#define USB3_DP_DBGINT_SIGNALBLK1_CONFIG4 0x0218 +#define USB3_DP_DBGINT_SIGNALBLK1_CONFIG5 0x021C +#define USB3_DP_DBGINT_SIGNALBLK2_CONFIG1 0x0220 +#define USB3_DP_DBGINT_SIGNALBLK2_CONFIG2 0x0224 +#define USB3_DP_DBGINT_SIGNALBLK2_CONFIG3 0x0228 +#define USB3_DP_DBGINT_SIGNALBLK2_CONFIG4 0x022C +#define USB3_DP_DBGINT_SIGNALBLK2_CONFIG5 0x0230 +#define USB3_DP_DBGINT_STRINGBLK1_CONFIG1 0x0234 +#define USB3_DP_DBGINT_STRINGBLK1_CONFIG2 0x0238 +#define USB3_DP_DBGINT_STRINGBLK1_CONFIG3 0x023C +#define USB3_DP_DBGINT_STRINGBLK1_CONFIG4 0x0240 +#define USB3_DP_DBGINT_STRINGBLK1_CONFIG5 0x0244 +#define USB3_DP_DBGINT_STRINGBLK2_CONFIG1 0x0248 +#define USB3_DP_DBGINT_STRINGBLK2_CONFIG2 0x024C +#define USB3_DP_DBGINT_STRINGBLK2_CONFIG3 0x0250 +#define USB3_DP_DBGINT_STRINGBLK2_CONFIG4 0x0254 +#define USB3_DP_DBGINT_STRINGBLK2_CONFIG5 0x0258 + +/* Module: USB3_DP_PHY_USB3_QSERDES_COM_USB3_QSERDES_COM_USB3_DP_QMP_PLL */ +#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0x1000 +#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x1004 +#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE1 0x1008 +#define USB3_DP_QSERDES_COM_CLK_EP_DIV_MODE1 0x100C +#define USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x1010 +#define USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x1014 +#define USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x1018 +#define USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x101C +#define USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x1020 +#define USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x1024 +#define USB3_DP_QSERDES_COM_DEC_START_MODE1 0x1028 +#define USB3_DP_QSERDES_COM_DEC_START_MSB_MODE1 0x102C +#define USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0x1030 +#define USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0x1034 +#define USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x1038 +#define USB3_DP_QSERDES_COM_HSCLK_SEL_1 0x103C +#define USB3_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x1040 +#define USB3_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x1044 +#define USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x1048 +#define USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x104C +#define USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1050 +#define USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1054 +#define USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1058 +#define USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x105C +#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0x1060 +#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x1064 +#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE0 0x1068 +#define USB3_DP_QSERDES_COM_CLK_EP_DIV_MODE0 0x106C +#define USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x1070 +#define USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x1074 +#define USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x1078 +#define USB3_DP_QSERDES_COM_CORECLK_DIV_MODE0 0x107C +#define USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x1080 +#define USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x1084 +#define USB3_DP_QSERDES_COM_DEC_START_MODE0 0x1088 +#define USB3_DP_QSERDES_COM_DEC_START_MSB_MODE0 0x108C +#define USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0x1090 +#define USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0x1094 +#define USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x1098 +#define USB3_DP_QSERDES_COM_HSCLK_HS_SWITCH_SEL_1 0x109C +#define USB3_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x10A0 +#define USB3_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10A4 +#define USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x10A8 +#define USB3_DP_QSERDES_COM_VCO_TUNE2_MODE0 0x10AC +#define USB3_DP_QSERDES_COM_ATB_SEL1 0x10B0 +#define USB3_DP_QSERDES_COM_ATB_SEL2 0x10B4 +#define USB3_DP_QSERDES_COM_FREQ_UPDATE 0x10B8 +#define USB3_DP_QSERDES_COM_BG_TIMER 0x10BC +#define USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x10C0 +#define USB3_DP_QSERDES_COM_SSC_ADJ_PER1 0x10C4 +#define USB3_DP_QSERDES_COM_SSC_ADJ_PER2 0x10C8 +#define USB3_DP_QSERDES_COM_SSC_PER1 0x10CC +#define USB3_DP_QSERDES_COM_SSC_PER2 0x10D0 +#define USB3_DP_QSERDES_COM_POST_DIV 0x10D4 +#define USB3_DP_QSERDES_COM_POST_DIV_MUX 0x10D8 +#define USB3_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x10DC +#define USB3_DP_QSERDES_COM_CLK_ENABLE1 0x10E0 +#define USB3_DP_QSERDES_COM_SYS_CLK_CTRL 0x10E4 +#define USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x10E8 +#define USB3_DP_QSERDES_COM_PLL_EN 0x10EC +#define USB3_DP_QSERDES_COM_DEBUG_BUS_OVRD 0x10F0 +#define USB3_DP_QSERDES_COM_PLL_IVCO 0x10F4 +#define USB3_DP_QSERDES_COM_PLL_IVCO_MODE1 0x10F8 +#define USB3_DP_QSERDES_COM_CMN_IETRIM 0x10FC +#define USB3_DP_QSERDES_COM_CMN_IPTRIM 0x1100 +#define USB3_DP_QSERDES_COM_EP_CLOCK_DETECT_CTRL 0x1104 +#define USB3_DP_QSERDES_COM_PLL_CNTRL 0x1108 +#define USB3_DP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x110C +#define USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1110 +#define USB3_DP_QSERDES_COM_CML_SYSCLK_SEL 0x1114 +#define USB3_DP_QSERDES_COM_RESETSM_CNTRL 0x1118 +#define USB3_DP_QSERDES_COM_RESETSM_CNTRL2 0x111C +#define USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x1120 +#define USB3_DP_QSERDES_COM_LOCK_CMP_CFG 0x1124 +#define USB3_DP_QSERDES_COM_INTEGLOOP_INITVAL 0x1128 +#define USB3_DP_QSERDES_COM_INTEGLOOP_EN 0x112C +#define USB3_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0 0x1130 +#define USB3_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1 0x1134 +#define USB3_DP_QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x1138 +#define USB3_DP_QSERDES_COM_VCO_TUNE_CTRL 0x113C +#define USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x1140 +#define USB3_DP_QSERDES_COM_VCO_TUNE_INITVAL1 0x1144 +#define USB3_DP_QSERDES_COM_VCO_TUNE_INITVAL2 0x1148 +#define USB3_DP_QSERDES_COM_VCO_TUNE_MINVAL1 0x114C +#define USB3_DP_QSERDES_COM_VCO_TUNE_MINVAL2 0x1150 +#define USB3_DP_QSERDES_COM_VCO_TUNE_MAXVAL1 0x1154 +#define USB3_DP_QSERDES_COM_VCO_TUNE_MAXVAL2 0x1158 +#define USB3_DP_QSERDES_COM_VCO_TUNE_TIMER1 0x115C +#define USB3_DP_QSERDES_COM_VCO_TUNE_TIMER2 0x1160 +#define USB3_DP_QSERDES_COM_CLK_SELECT 0x1164 +#define USB3_DP_QSERDES_COM_PLL_ANALOG 0x1168 +#define USB3_DP_QSERDES_COM_SW_RESET 0x116C +#define USB3_DP_QSERDES_COM_CORE_CLK_EN 0x1170 +#define USB3_DP_QSERDES_COM_CMN_CONFIG_1 0x1174 +#define USB3_DP_QSERDES_COM_CMN_RATE_OVERRIDE 0x1178 +#define USB3_DP_QSERDES_COM_SVS_MODE_CLK_SEL 0x117C +#define USB3_DP_QSERDES_COM_DEBUG_BUS_SEL 0x1180 +#define USB3_DP_QSERDES_COM_CMN_MISC1 0x1184 +#define USB3_DP_QSERDES_COM_CMN_MODE 0x1188 +#define USB3_DP_QSERDES_COM_CMN_MODE_CONTD 0x118C +#define USB3_DP_QSERDES_COM_CMN_MODE_CONTD1 0x1190 +#define USB3_DP_QSERDES_COM_CMN_MODE_CONTD2 0x1194 +#define USB3_DP_QSERDES_COM_VCO_DC_LEVEL_CTRL 0x1198 +#define USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_1 0x119C +#define USB3_DP_QSERDES_COM_ADDITIONAL_CTRL_1 0x11A0 +#define USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_1 0x11A4 +#define USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_2 0x11A8 +#define USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_3 0x11AC +#define USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_4 0x11B0 +#define USB3_DP_QSERDES_COM_ADDITIONAL_MISC 0x11B4 +#define USB3_DP_QSERDES_COM_ADDITIONAL_MISC_2 0x11B8 +#define USB3_DP_QSERDES_COM_ADDITIONAL_MISC_3 0x11BC +#define USB3_DP_QSERDES_COM_ADDITIONAL_MISC_4 0x11C0 +#define USB3_DP_QSERDES_COM_ADDITIONAL_MISC_5 0x11C4 +#define USB3_DP_QSERDES_COM_MODE_OPERATION_STATUS 0x11C8 +#define USB3_DP_QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x11CC +#define USB3_DP_QSERDES_COM_CMN_STATUS 0x11D0 +#define USB3_DP_QSERDES_COM_RESET_SM_STATUS 0x11D4 +#define USB3_DP_QSERDES_COM_RESTRIM_CODE_STATUS 0x11D8 +#define USB3_DP_QSERDES_COM_PLLCAL_CODE1_STATUS 0x11DC +#define USB3_DP_QSERDES_COM_PLLCAL_CODE2_STATUS 0x11E0 +#define USB3_DP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS 0x11E4 +#define USB3_DP_QSERDES_COM_DEBUG_BUS0 0x11E8 +#define USB3_DP_QSERDES_COM_DEBUG_BUS1 0x11EC +#define USB3_DP_QSERDES_COM_DEBUG_BUS2 0x11F0 +#define USB3_DP_QSERDES_COM_DEBUG_BUS3 0x11F4 +#define USB3_DP_QSERDES_COM_C_READY_STATUS 0x11F8 +#define USB3_DP_QSERDES_COM_READ_DUMMY_1 0x11FC + +/* Module: USB3_DP_PHY_USB3_QSERDES_TXA_USB3_QSERDES_TXA_USB3_DP_QMP_TX */ +#define USB3_DP_QSERDES_TXA_BIST_MODE_LANENO 0x1200 +#define USB3_DP_QSERDES_TXA_BIST_INVERT 0x1204 +#define USB3_DP_QSERDES_TXA_CLKBUF_ENABLE 0x1208 +#define USB3_DP_QSERDES_TXA_TX_EMP_POST1_LVL 0x120C +#define USB3_DP_QSERDES_TXA_TX_IDLE_LVL_LARGE_AMP 0x1210 +#define USB3_DP_QSERDES_TXA_TX_DRV_LVL 0x1214 +#define USB3_DP_QSERDES_TXA_TX_DRV_LVL_OFFSET 0x1218 +#define USB3_DP_QSERDES_TXA_RESET_TSYNC_EN 0x121C +#define USB3_DP_QSERDES_TXA_PRE_STALL_LDO_BOOST_EN 0x1220 +#define USB3_DP_QSERDES_TXA_TX_BAND 0x1224 +#define USB3_DP_QSERDES_TXA_SLEW_CNTL 0x1228 +#define USB3_DP_QSERDES_TXA_INTERFACE_SELECT 0x122C +#define USB3_DP_QSERDES_TXA_LPB_EN 0x1230 +#define USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x1234 +#define USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x1238 +#define USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x123C +#define USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x1240 +#define USB3_DP_QSERDES_TXA_PERL_LENGTH1 0x1244 +#define USB3_DP_QSERDES_TXA_PERL_LENGTH2 0x1248 +#define USB3_DP_QSERDES_TXA_SERDES_BYP_EN_OUT 0x124C +#define USB3_DP_QSERDES_TXA_DEBUG_BUS_SEL 0x1250 +#define USB3_DP_QSERDES_TXA_TRANSCEIVER_BIAS_EN 0x1254 +#define USB3_DP_QSERDES_TXA_HIGHZ_DRVR_EN 0x1258 +#define USB3_DP_QSERDES_TXA_TX_POL_INV 0x125C +#define USB3_DP_QSERDES_TXA_PARRATE_REC_DETECT_IDLE_EN 0x1260 +#define USB3_DP_QSERDES_TXA_BIST_PATTERN1 0x1264 +#define USB3_DP_QSERDES_TXA_BIST_PATTERN2 0x1268 +#define USB3_DP_QSERDES_TXA_BIST_PATTERN3 0x126C +#define USB3_DP_QSERDES_TXA_BIST_PATTERN4 0x1270 +#define USB3_DP_QSERDES_TXA_BIST_PATTERN5 0x1274 +#define USB3_DP_QSERDES_TXA_BIST_PATTERN6 0x1278 +#define USB3_DP_QSERDES_TXA_BIST_PATTERN7 0x127C +#define USB3_DP_QSERDES_TXA_BIST_PATTERN8 0x1280 +#define USB3_DP_QSERDES_TXA_LANE_MODE_1 0x1284 +#define USB3_DP_QSERDES_TXA_LANE_MODE_2 0x1288 +#define USB3_DP_QSERDES_TXA_LANE_MODE_3 0x128C +#define USB3_DP_QSERDES_TXA_LANE_MODE_4 0x1290 +#define USB3_DP_QSERDES_TXA_LANE_MODE_5 0x1294 +#define USB3_DP_QSERDES_TXA_ATB_SEL1 0x1298 +#define USB3_DP_QSERDES_TXA_ATB_SEL2 0x129C +#define USB3_DP_QSERDES_TXA_RCV_DETECT_LVL 0x12A0 +#define USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12A4 +#define USB3_DP_QSERDES_TXA_PRBS_SEED1 0x12A8 +#define USB3_DP_QSERDES_TXA_PRBS_SEED2 0x12AC +#define USB3_DP_QSERDES_TXA_PRBS_SEED3 0x12B0 +#define USB3_DP_QSERDES_TXA_PRBS_SEED4 0x12B4 +#define USB3_DP_QSERDES_TXA_RESET_GEN 0x12B8 +#define USB3_DP_QSERDES_TXA_RESET_GEN_MUXES 0x12BC +#define USB3_DP_QSERDES_TXA_TRAN_DRVR_EMP_EN 0x12C0 +#define USB3_DP_QSERDES_TXA_TX_INTERFACE_MODE 0x12C4 +#define USB3_DP_QSERDES_TXA_VMODE_CTRL1 0x12C8 +#define USB3_DP_QSERDES_TXA_ALOG_OBSV_BUS_CTRL_1 0x12CC +#define USB3_DP_QSERDES_TXA_BIST_STATUS 0x12D0 +#define USB3_DP_QSERDES_TXA_BIST_ERROR_COUNT1 0x12D4 +#define USB3_DP_QSERDES_TXA_BIST_ERROR_COUNT2 0x12D8 +#define USB3_DP_QSERDES_TXA_ALOG_OBSV_BUS_STATUS_1 0x12DC +#define USB3_DP_QSERDES_TXA_LANE_DIG_CONFIG 0x12E0 +#define USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x12E4 +#define USB3_DP_QSERDES_TXA_PRE_EMPH 0x12E8 +#define USB3_DP_QSERDES_TXA_SW_RESET 0x12EC +#define USB3_DP_QSERDES_TXA_DCC_OFFSET 0x12F0 +#define USB3_DP_QSERDES_TXA_DCC_CMUX_POSTCAL_OFFSET 0x12F4 +#define USB3_DP_QSERDES_TXA_DCC_CMUX_CAL_CTRL1 0x12F8 +#define USB3_DP_QSERDES_TXA_DCC_CMUX_CAL_CTRL2 0x12FC +#define USB3_DP_QSERDES_TXA_DIG_BKUP_CTRL 0x1300 +#define USB3_DP_QSERDES_TXA_DEBUG_BUS0 0x1304 +#define USB3_DP_QSERDES_TXA_DEBUG_BUS1 0x1308 +#define USB3_DP_QSERDES_TXA_DEBUG_BUS2 0x130C +#define USB3_DP_QSERDES_TXA_DEBUG_BUS3 0x1310 +#define USB3_DP_QSERDES_TXA_READ_EQCODE 0x1314 +#define USB3_DP_QSERDES_TXA_READ_OFFSETCODE 0x1318 +#define USB3_DP_QSERDES_TXA_IA_ERROR_COUNTER_LOW 0x131C +#define USB3_DP_QSERDES_TXA_IA_ERROR_COUNTER_HIGH 0x1320 +#define USB3_DP_QSERDES_TXA_VGA_READ_CODE 0x1324 +#define USB3_DP_QSERDES_TXA_VTH_READ_CODE 0x1328 +#define USB3_DP_QSERDES_TXA_DFE_TAP1_READ_CODE 0x132C +#define USB3_DP_QSERDES_TXA_DFE_TAP2_READ_CODE 0x1330 +#define USB3_DP_QSERDES_TXA_IDAC_STATUS_I 0x1334 +#define USB3_DP_QSERDES_TXA_IDAC_STATUS_IBAR 0x1338 +#define USB3_DP_QSERDES_TXA_IDAC_STATUS_Q 0x133C +#define USB3_DP_QSERDES_TXA_IDAC_STATUS_QBAR 0x1340 +#define USB3_DP_QSERDES_TXA_IDAC_STATUS_A 0x1344 +#define USB3_DP_QSERDES_TXA_IDAC_STATUS_ABAR 0x1348 +#define USB3_DP_QSERDES_TXA_IDAC_STATUS_SM_ON 0x134C +#define USB3_DP_QSERDES_TXA_IDAC_STATUS_CAL_DONE 0x1350 +#define USB3_DP_QSERDES_TXA_IDAC_STATUS_SIGNERROR 0x1354 +#define USB3_DP_QSERDES_TXA_DCC_CAL_STATUS 0x1358 +#define USB3_DP_QSERDES_TXA_DCC_READ_CODE_STATUS 0x135C +#define USB3_DP_QSERDES_TXA_SIGDET_CAL_ENGINE_STATUS 0x1360 +#define USB3_DP_QSERDES_TXA_AC_JTAG_OUTP_OUTN_STATUS 0x1364 + +/* Module: USB3_DP_PHY_USB3_QSERDES_RXA_USB3_QSERDES_RXA_USB3_DP_QMP_RX */ +#define USB3_DP_QSERDES_RXA_UCDR_FO_GAIN_HALF 0x1400 +#define USB3_DP_QSERDES_RXA_UCDR_FO_GAIN_QUARTER 0x1404 +#define USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x1408 +#define USB3_DP_QSERDES_RXA_UCDR_SO_GAIN_HALF 0x140C +#define USB3_DP_QSERDES_RXA_UCDR_SO_GAIN_QUARTER 0x1410 +#define USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x1414 +#define USB3_DP_QSERDES_RXA_UCDR_SVS_FO_GAIN_HALF 0x1418 +#define USB3_DP_QSERDES_RXA_UCDR_SVS_FO_GAIN_QUARTER 0x141C +#define USB3_DP_QSERDES_RXA_UCDR_SVS_FO_GAIN 0x1420 +#define USB3_DP_QSERDES_RXA_UCDR_SVS_SO_GAIN_HALF 0x1424 +#define USB3_DP_QSERDES_RXA_UCDR_SVS_SO_GAIN_QUARTER 0x1428 +#define USB3_DP_QSERDES_RXA_UCDR_SVS_SO_GAIN 0x142C +#define USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x1430 +#define USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x1434 +#define USB3_DP_QSERDES_RXA_UCDR_FO_TO_SO_DELAY 0x1438 +#define USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0x143C +#define USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x1440 +#define USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x1444 +#define USB3_DP_QSERDES_RXA_UCDR_PI_CTRL2 0x1448 +#define USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x144C +#define USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x1450 +#define USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x1454 +#define USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x1458 +#define USB3_DP_QSERDES_RXA_AUX_CONTROL 0x145C +#define USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0x1460 +#define USB3_DP_QSERDES_RXA_RCLK_AUXDATA_SEL 0x1464 +#define USB3_DP_QSERDES_RXA_AC_JTAG_ENABLE 0x1468 +#define USB3_DP_QSERDES_RXA_AC_JTAG_INITP 0x146C +#define USB3_DP_QSERDES_RXA_AC_JTAG_INITN 0x1470 +#define USB3_DP_QSERDES_RXA_AC_JTAG_LVL 0x1474 +#define USB3_DP_QSERDES_RXA_AC_JTAG_MODE 0x1478 +#define USB3_DP_QSERDES_RXA_AC_JTAG_RESET 0x147C +#define USB3_DP_QSERDES_RXA_RX_TERM_BW 0x1480 +#define USB3_DP_QSERDES_RXA_RX_RCVR_IQ_EN 0x1484 +#define USB3_DP_QSERDES_RXA_RX_IDAC_I_DC_OFFSETS 0x1488 +#define USB3_DP_QSERDES_RXA_RX_IDAC_IBAR_DC_OFFSETS 0x148C +#define USB3_DP_QSERDES_RXA_RX_IDAC_Q_DC_OFFSETS 0x1490 +#define USB3_DP_QSERDES_RXA_RX_IDAC_QBAR_DC_OFFSETS 0x1494 +#define USB3_DP_QSERDES_RXA_RX_IDAC_A_DC_OFFSETS 0x1498 +#define USB3_DP_QSERDES_RXA_RX_IDAC_ABAR_DC_OFFSETS 0x149C +#define USB3_DP_QSERDES_RXA_RX_IDAC_EN 0x14A0 +#define USB3_DP_QSERDES_RXA_RX_IDAC_ENABLES 0x14A4 +#define USB3_DP_QSERDES_RXA_RX_IDAC_SIGN 0x14A8 +#define USB3_DP_QSERDES_RXA_RX_HIGHZ_HIGHRATE 0x14AC +#define USB3_DP_QSERDES_RXA_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x14B0 +#define USB3_DP_QSERDES_RXA_DFE_1 0x14B4 +#define USB3_DP_QSERDES_RXA_DFE_2 0x14B8 +#define USB3_DP_QSERDES_RXA_DFE_3 0x14BC +#define USB3_DP_QSERDES_RXA_DFE_4 0x14C0 +#define USB3_DP_QSERDES_RXA_TX_ADAPT_PRE_THRESH1 0x14C4 +#define USB3_DP_QSERDES_RXA_TX_ADAPT_PRE_THRESH2 0x14C8 +#define USB3_DP_QSERDES_RXA_TX_ADAPT_POST_THRESH 0x14CC +#define USB3_DP_QSERDES_RXA_TX_ADAPT_MAIN_THRESH 0x14D0 +#define USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x14D4 +#define USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x14D8 +#define USB3_DP_QSERDES_RXA_GM_CAL 0x14DC +#define USB3_DP_QSERDES_RXA_RX_VGA_GAIN2_LSB 0x14E0 +#define USB3_DP_QSERDES_RXA_RX_VGA_GAIN2_MSB 0x14E4 +#define USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL1 0x14E8 +#define USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x14EC +#define USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x14F0 +#define USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x14F4 +#define USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0x14F8 +#define USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x14FC +#define USB3_DP_QSERDES_RXA_RX_IDAC_MEASURE_TIME 0x1500 +#define USB3_DP_QSERDES_RXA_RX_IDAC_ACCUMULATOR 0x1504 +#define USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_LSB 0x1508 +#define USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_MSB 0x150C +#define USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1510 +#define USB3_DP_QSERDES_RXA_RX_OFFSET_ADAPTOR_CNTRL2 0x1514 +#define USB3_DP_QSERDES_RXA_SIGDET_ENABLES 0x1518 +#define USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x151C +#define USB3_DP_QSERDES_RXA_SIGDET_LVL 0x1520 +#define USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x1524 +#define USB3_DP_QSERDES_RXA_RX_BAND 0x1528 +#define USB3_DP_QSERDES_RXA_CDR_FREEZE_UP_DN 0x152C +#define USB3_DP_QSERDES_RXA_CDR_RESET_OVERRIDE 0x1530 +#define USB3_DP_QSERDES_RXA_RX_INTERFACE_MODE 0x1534 +#define USB3_DP_QSERDES_RXA_JITTER_GEN_MODE 0x1538 +#define USB3_DP_QSERDES_RXA_SJ_AMP1 0x153C +#define USB3_DP_QSERDES_RXA_SJ_AMP2 0x1540 +#define USB3_DP_QSERDES_RXA_SJ_PER1 0x1544 +#define USB3_DP_QSERDES_RXA_SJ_PER2 0x1548 +#define USB3_DP_QSERDES_RXA_PPM_OFFSET1 0x154C +#define USB3_DP_QSERDES_RXA_PPM_OFFSET2 0x1550 +#define USB3_DP_QSERDES_RXA_SIGN_PPM_PERIOD1 0x1554 +#define USB3_DP_QSERDES_RXA_SIGN_PPM_PERIOD2 0x1558 +#define USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0x155C +#define USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x1560 +#define USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0x1564 +#define USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x1568 +#define USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0x156C +#define USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x1570 +#define USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x1574 +#define USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x1578 +#define USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x157C +#define USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0x1580 +#define USB3_DP_QSERDES_RXA_RX_MODE_10_LOW 0x1584 +#define USB3_DP_QSERDES_RXA_RX_MODE_10_HIGH 0x1588 +#define USB3_DP_QSERDES_RXA_RX_MODE_10_HIGH2 0x158C +#define USB3_DP_QSERDES_RXA_RX_MODE_10_HIGH3 0x1590 +#define USB3_DP_QSERDES_RXA_RX_MODE_10_HIGH4 0x1594 +#define USB3_DP_QSERDES_RXA_PHPRE_CTRL 0x1598 +#define USB3_DP_QSERDES_RXA_PHPRE_INITVAL 0x159C +#define USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x15A0 +#define USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x15A4 +#define USB3_DP_QSERDES_RXA_DCC_CTRL1 0x15A8 +#define USB3_DP_QSERDES_RXA_DCC_CTRL2 0x15AC +#define USB3_DP_QSERDES_RXA_VTH_CODE 0x15B0 +#define USB3_DP_QSERDES_RXA_VTH_MIN_THRESH 0x15B4 +#define USB3_DP_QSERDES_RXA_VTH_MAX_THRESH 0x15B8 +#define USB3_DP_QSERDES_RXA_ALOG_OBSV_BUS_CTRL_1 0x15BC +#define USB3_DP_QSERDES_RXA_PI_CTRL1 0x15C0 +#define USB3_DP_QSERDES_RXA_PI_CTRL2 0x15C4 +#define USB3_DP_QSERDES_RXA_PI_QUAD 0x15C8 +#define USB3_DP_QSERDES_RXA_IDATA1 0x15CC +#define USB3_DP_QSERDES_RXA_IDATA2 0x15D0 +#define USB3_DP_QSERDES_RXA_AUX_DATA1 0x15D4 +#define USB3_DP_QSERDES_RXA_AUX_DATA2 0x15D8 +#define USB3_DP_QSERDES_RXA_RX_SIGDET_AND_CDR_FALSE_LOCK_STATUS 0x15DC +#define USB3_DP_QSERDES_RXA_ALOG_OBSV_BUS_STATUS_1 0x15E0 +#define USB3_DP_QSERDES_RXA_SIGDET_CAL_CTRL1 0x15E4 +#define USB3_DP_QSERDES_RXA_SIGDET_CAL_CTRL2_AND_CDR_LOCK_EDGE 0x15E8 +#define USB3_DP_QSERDES_RXA_CDR_LOCK_ON_EDGE_DURATION 0x15EC +#define USB3_DP_QSERDES_RXA_CDR_LOCK_ON_EDGE_THRESH 0x15F0 +#define USB3_DP_QSERDES_QSERDES_RXA_RX_ADAPTOR_CNTRL 0x15F4 +#define USB3_DP_QSERDES_RXA_SIGDET_CAL_TRIM 0x15F8 +#define USB3_DP_QSERDES_RXA_CAL_POST_WRAP 0x15FC + +/* Module: USB3_DP_PHY_USB3_QSERDES_TXB_USB3_QSERDES_TXB_USB3_DP_QMP_TX */ +#define USB3_DP_QSERDES_TXB_BIST_MODE_LANENO 0x1600 +#define USB3_DP_QSERDES_TXB_BIST_INVERT 0x1604 +#define USB3_DP_QSERDES_TXB_CLKBUF_ENABLE 0x1608 +#define USB3_DP_QSERDES_TXB_TX_EMP_POST1_LVL 0x160C +#define USB3_DP_QSERDES_TXB_TX_IDLE_LVL_LARGE_AMP 0x1610 +#define USB3_DP_QSERDES_TXB_TX_DRV_LVL 0x1614 +#define USB3_DP_QSERDES_TXB_TX_DRV_LVL_OFFSET 0x1618 +#define USB3_DP_QSERDES_TXB_RESET_TSYNC_EN 0x161C +#define USB3_DP_QSERDES_TXB_PRE_STALL_LDO_BOOST_EN 0x1620 +#define USB3_DP_QSERDES_TXB_TX_BAND 0x1624 +#define USB3_DP_QSERDES_TXB_SLEW_CNTL 0x1628 +#define USB3_DP_QSERDES_TXB_INTERFACE_SELECT 0x162C +#define USB3_DP_QSERDES_TXB_LPB_EN 0x1630 +#define USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x1634 +#define USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x1638 +#define USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x163C +#define USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x1640 +#define USB3_DP_QSERDES_TXB_PERL_LENGTH1 0x1644 +#define USB3_DP_QSERDES_TXB_PERL_LENGTH2 0x1648 +#define USB3_DP_QSERDES_TXB_SERDES_BYP_EN_OUT 0x164C +#define USB3_DP_QSERDES_TXB_DEBUG_BUS_SEL 0x1650 +#define USB3_DP_QSERDES_TXB_TRANSCEIVER_BIAS_EN 0x1654 +#define USB3_DP_QSERDES_TXB_HIGHZ_DRVR_EN 0x1658 +#define USB3_DP_QSERDES_TXB_TX_POL_INV 0x165C +#define USB3_DP_QSERDES_TXB_PARRATE_REC_DETECT_IDLE_EN 0x1660 +#define USB3_DP_QSERDES_TXB_BIST_PATTERN1 0x1664 +#define USB3_DP_QSERDES_TXB_BIST_PATTERN2 0x1668 +#define USB3_DP_QSERDES_TXB_BIST_PATTERN3 0x166C +#define USB3_DP_QSERDES_TXB_BIST_PATTERN4 0x1670 +#define USB3_DP_QSERDES_TXB_BIST_PATTERN5 0x1674 +#define USB3_DP_QSERDES_TXB_BIST_PATTERN6 0x1678 +#define USB3_DP_QSERDES_TXB_BIST_PATTERN7 0x167C +#define USB3_DP_QSERDES_TXB_BIST_PATTERN8 0x1680 +#define USB3_DP_QSERDES_TXB_LANE_MODE_1 0x1684 +#define USB3_DP_QSERDES_TXB_LANE_MODE_2 0x1688 +#define USB3_DP_QSERDES_TXB_LANE_MODE_3 0x168C +#define USB3_DP_QSERDES_TXB_LANE_MODE_4 0x1690 +#define USB3_DP_QSERDES_TXB_LANE_MODE_5 0x1694 +#define USB3_DP_QSERDES_TXB_ATB_SEL1 0x1698 +#define USB3_DP_QSERDES_TXB_ATB_SEL2 0x169C +#define USB3_DP_QSERDES_TXB_RCV_DETECT_LVL 0x16A0 +#define USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x16A4 +#define USB3_DP_QSERDES_TXB_PRBS_SEED1 0x16A8 +#define USB3_DP_QSERDES_TXB_PRBS_SEED2 0x16AC +#define USB3_DP_QSERDES_TXB_PRBS_SEED3 0x16B0 +#define USB3_DP_QSERDES_TXB_PRBS_SEED4 0x16B4 +#define USB3_DP_QSERDES_TXB_RESET_GEN 0x16B8 +#define USB3_DP_QSERDES_TXB_RESET_GEN_MUXES 0x16BC +#define USB3_DP_QSERDES_TXB_TRAN_DRVR_EMP_EN 0x16C0 +#define USB3_DP_QSERDES_TXB_TX_INTERFACE_MODE 0x16C4 +#define USB3_DP_QSERDES_TXB_VMODE_CTRL1 0x16C8 +#define USB3_DP_QSERDES_TXB_ALOG_OBSV_BUS_CTRL_1 0x16CC +#define USB3_DP_QSERDES_TXB_BIST_STATUS 0x16D0 +#define USB3_DP_QSERDES_TXB_BIST_ERROR_COUNT1 0x16D4 +#define USB3_DP_QSERDES_TXB_BIST_ERROR_COUNT2 0x16D8 +#define USB3_DP_QSERDES_TXB_ALOG_OBSV_BUS_STATUS_1 0x16DC +#define USB3_DP_QSERDES_TXB_LANE_DIG_CONFIG 0x16E0 +#define USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x16E4 +#define USB3_DP_QSERDES_TXB_PRE_EMPH 0x16E8 +#define USB3_DP_QSERDES_TXB_SW_RESET 0x16EC +#define USB3_DP_QSERDES_TXB_DCC_OFFSET 0x16F0 +#define USB3_DP_QSERDES_TXB_DCC_CMUX_POSTCAL_OFFSET 0x16F4 +#define USB3_DP_QSERDES_TXB_DCC_CMUX_CAL_CTRL1 0x16F8 +#define USB3_DP_QSERDES_TXB_DCC_CMUX_CAL_CTRL2 0x16FC +#define USB3_DP_QSERDES_TXB_DIG_BKUP_CTRL 0x1700 +#define USB3_DP_QSERDES_TXB_DEBUG_BUS0 0x1704 +#define USB3_DP_QSERDES_TXB_DEBUG_BUS1 0x1708 +#define USB3_DP_QSERDES_TXB_DEBUG_BUS2 0x170C +#define USB3_DP_QSERDES_TXB_DEBUG_BUS3 0x1710 +#define USB3_DP_QSERDES_TXB_READ_EQCODE 0x1714 +#define USB3_DP_QSERDES_TXB_READ_OFFSETCODE 0x1718 +#define USB3_DP_QSERDES_TXB_IA_ERROR_COUNTER_LOW 0x171C +#define USB3_DP_QSERDES_TXB_IA_ERROR_COUNTER_HIGH 0x1720 +#define USB3_DP_QSERDES_TXB_VGA_READ_CODE 0x1724 +#define USB3_DP_QSERDES_TXB_VTH_READ_CODE 0x1728 +#define USB3_DP_QSERDES_TXB_DFE_TAP1_READ_CODE 0x172C +#define USB3_DP_QSERDES_TXB_DFE_TAP2_READ_CODE 0x1730 +#define USB3_DP_QSERDES_TXB_IDAC_STATUS_I 0x1734 +#define USB3_DP_QSERDES_TXB_IDAC_STATUS_IBAR 0x1738 +#define USB3_DP_QSERDES_TXB_IDAC_STATUS_Q 0x173C +#define USB3_DP_QSERDES_TXB_IDAC_STATUS_QBAR 0x1740 +#define USB3_DP_QSERDES_TXB_IDAC_STATUS_A 0x1744 +#define USB3_DP_QSERDES_TXB_IDAC_STATUS_ABAR 0x1748 +#define USB3_DP_QSERDES_TXB_IDAC_STATUS_SM_ON 0x174C +#define USB3_DP_QSERDES_TXB_IDAC_STATUS_CAL_DONE 0x1750 +#define USB3_DP_QSERDES_TXB_IDAC_STATUS_SIGNERROR 0x1754 +#define USB3_DP_QSERDES_TXB_DCC_CAL_STATUS 0x1758 +#define USB3_DP_QSERDES_TXB_DCC_READ_CODE_STATUS 0x175C +#define USB3_DP_QSERDES_TXB_SIGDET_CAL_ENGINE_STATUS 0x1760 +#define USB3_DP_QSERDES_TXB_AC_JTAG_OUTP_OUTN_STATUS 0x1764 + +/* Module: USB3_DP_PHY_USB3_QSERDES_RXB_USB3_QSERDES_RXB_USB3_DP_QMP_RX */ +#define USB3_DP_QSERDES_RXB_UCDR_FO_GAIN_HALF 0x1800 +#define USB3_DP_QSERDES_RXB_UCDR_FO_GAIN_QUARTER 0x1804 +#define USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x1808 +#define USB3_DP_QSERDES_RXB_UCDR_SO_GAIN_HALF 0x180C +#define USB3_DP_QSERDES_RXB_UCDR_SO_GAIN_QUARTER 0x1810 +#define USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x1814 +#define USB3_DP_QSERDES_RXB_UCDR_SVS_FO_GAIN_HALF 0x1818 +#define USB3_DP_QSERDES_RXB_UCDR_SVS_FO_GAIN_QUARTER 0x181C +#define USB3_DP_QSERDES_RXB_UCDR_SVS_FO_GAIN 0x1820 +#define USB3_DP_QSERDES_RXB_UCDR_SVS_SO_GAIN_HALF 0x1824 +#define USB3_DP_QSERDES_RXB_UCDR_SVS_SO_GAIN_QUARTER 0x1828 +#define USB3_DP_QSERDES_RXB_UCDR_SVS_SO_GAIN 0x182C +#define USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x1830 +#define USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x1834 +#define USB3_DP_QSERDES_RXB_UCDR_FO_TO_SO_DELAY 0x1838 +#define USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0x183C +#define USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x1840 +#define USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x1844 +#define USB3_DP_QSERDES_RXB_UCDR_PI_CTRL2 0x1848 +#define USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x184C +#define USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x1850 +#define USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x1854 +#define USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x1858 +#define USB3_DP_QSERDES_RXB_AUX_CONTROL 0x185C +#define USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0x1860 +#define USB3_DP_QSERDES_RXB_RCLK_AUXDATA_SEL 0x1864 +#define USB3_DP_QSERDES_RXB_AC_JTAG_ENABLE 0x1868 +#define USB3_DP_QSERDES_RXB_AC_JTAG_INITP 0x186C +#define USB3_DP_QSERDES_RXB_AC_JTAG_INITN 0x1870 +#define USB3_DP_QSERDES_RXB_AC_JTAG_LVL 0x1874 +#define USB3_DP_QSERDES_RXB_AC_JTAG_MODE 0x1878 +#define USB3_DP_QSERDES_RXB_AC_JTAG_RESET 0x187C +#define USB3_DP_QSERDES_RXB_RX_TERM_BW 0x1880 +#define USB3_DP_QSERDES_RXB_RX_RCVR_IQ_EN 0x1884 +#define USB3_DP_QSERDES_RXB_RX_IDAC_I_DC_OFFSETS 0x1888 +#define USB3_DP_QSERDES_RXB_RX_IDAC_IBAR_DC_OFFSETS 0x188C +#define USB3_DP_QSERDES_RXB_RX_IDAC_Q_DC_OFFSETS 0x1890 +#define USB3_DP_QSERDES_RXB_RX_IDAC_QBAR_DC_OFFSETS 0x1894 +#define USB3_DP_QSERDES_RXB_RX_IDAC_A_DC_OFFSETS 0x1898 +#define USB3_DP_QSERDES_RXB_RX_IDAC_ABAR_DC_OFFSETS 0x189C +#define USB3_DP_QSERDES_RXB_RX_IDAC_EN 0x18A0 +#define USB3_DP_QSERDES_RXB_RX_IDAC_ENABLES 0x18A4 +#define USB3_DP_QSERDES_RXB_RX_IDAC_SIGN 0x18A8 +#define USB3_DP_QSERDES_RXB_RX_HIGHZ_HIGHRATE 0x18AC +#define USB3_DP_QSERDES_RXB_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x18B0 +#define USB3_DP_QSERDES_RXB_DFE_1 0x18B4 +#define USB3_DP_QSERDES_RXB_DFE_2 0x18B8 +#define USB3_DP_QSERDES_RXB_DFE_3 0x18BC +#define USB3_DP_QSERDES_RXB_DFE_4 0x18C0 +#define USB3_DP_QSERDES_RXB_TX_ADAPT_PRE_THRESH1 0x18C4 +#define USB3_DP_QSERDES_RXB_TX_ADAPT_PRE_THRESH2 0x18C8 +#define USB3_DP_QSERDES_RXB_TX_ADAPT_POST_THRESH 0x18CC +#define USB3_DP_QSERDES_RXB_TX_ADAPT_MAIN_THRESH 0x18D0 +#define USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x18D4 +#define USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x18D8 +#define USB3_DP_QSERDES_RXB_GM_CAL 0x18DC +#define USB3_DP_QSERDES_RXB_RX_VGA_GAIN2_LSB 0x18E0 +#define USB3_DP_QSERDES_RXB_RX_VGA_GAIN2_MSB 0x18E4 +#define USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL1 0x18E8 +#define USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x18EC +#define USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x18F0 +#define USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x18F4 +#define USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0x18F8 +#define USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x18FC +#define USB3_DP_QSERDES_RXB_RX_IDAC_MEASURE_TIME 0x1900 +#define USB3_DP_QSERDES_RXB_RX_IDAC_ACCUMULATOR 0x1904 +#define USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_LSB 0x1908 +#define USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_MSB 0x190C +#define USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1910 +#define USB3_DP_QSERDES_RXB_RX_OFFSET_ADAPTOR_CNTRL2 0x1914 +#define USB3_DP_QSERDES_RXB_SIGDET_ENABLES 0x1918 +#define USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x191C +#define USB3_DP_QSERDES_RXB_SIGDET_LVL 0x1920 +#define USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x1924 +#define USB3_DP_QSERDES_RXB_RX_BAND 0x1928 +#define USB3_DP_QSERDES_RXB_CDR_FREEZE_UP_DN 0x192C +#define USB3_DP_QSERDES_RXB_CDR_RESET_OVERRIDE 0x1930 +#define USB3_DP_QSERDES_RXB_RX_INTERFACE_MODE 0x1934 +#define USB3_DP_QSERDES_RXB_JITTER_GEN_MODE 0x1938 +#define USB3_DP_QSERDES_RXB_SJ_AMP1 0x193C +#define USB3_DP_QSERDES_RXB_SJ_AMP2 0x1940 +#define USB3_DP_QSERDES_RXB_SJ_PER1 0x1944 +#define USB3_DP_QSERDES_RXB_SJ_PER2 0x1948 +#define USB3_DP_QSERDES_RXB_PPM_OFFSET1 0x194C +#define USB3_DP_QSERDES_RXB_PPM_OFFSET2 0x1950 +#define USB3_DP_QSERDES_RXB_SIGN_PPM_PERIOD1 0x1954 +#define USB3_DP_QSERDES_RXB_SIGN_PPM_PERIOD2 0x1958 +#define USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0x195C +#define USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0x1960 +#define USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0x1964 +#define USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x1968 +#define USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0x196C +#define USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x1970 +#define USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x1974 +#define USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x1978 +#define USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x197C +#define USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0x1980 +#define USB3_DP_QSERDES_RXB_RX_MODE_10_LOW 0x1984 +#define USB3_DP_QSERDES_RXB_RX_MODE_10_HIGH 0x1988 +#define USB3_DP_QSERDES_RXB_RX_MODE_10_HIGH2 0x198C +#define USB3_DP_QSERDES_RXB_RX_MODE_10_HIGH3 0x1990 +#define USB3_DP_QSERDES_RXB_RX_MODE_10_HIGH4 0x1994 +#define USB3_DP_QSERDES_RXB_PHPRE_CTRL 0x1998 +#define USB3_DP_QSERDES_RXB_PHPRE_INITVAL 0x199C +#define USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x19A0 +#define USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x19A4 +#define USB3_DP_QSERDES_RXB_DCC_CTRL1 0x19A8 +#define USB3_DP_QSERDES_RXB_DCC_CTRL2 0x19AC +#define USB3_DP_QSERDES_RXB_VTH_CODE 0x19B0 +#define USB3_DP_QSERDES_RXB_VTH_MIN_THRESH 0x19B4 +#define USB3_DP_QSERDES_RXB_VTH_MAX_THRESH 0x19B8 +#define USB3_DP_QSERDES_RXB_ALOG_OBSV_BUS_CTRL_1 0x19BC +#define USB3_DP_QSERDES_RXB_PI_CTRL1 0x19C0 +#define USB3_DP_QSERDES_RXB_PI_CTRL2 0x19C4 +#define USB3_DP_QSERDES_RXB_PI_QUAD 0x19C8 +#define USB3_DP_QSERDES_RXB_IDATA1 0x19CC +#define USB3_DP_QSERDES_RXB_IDATA2 0x19D0 +#define USB3_DP_QSERDES_RXB_AUX_DATA1 0x19D4 +#define USB3_DP_QSERDES_RXB_AUX_DATA2 0x19D8 +#define USB3_DP_QSERDES_RXB_RX_SIGDET_AND_CDR_FALSE_LOCK_STATUS 0x19DC +#define USB3_DP_QSERDES_RXB_ALOG_OBSV_BUS_STATUS_1 0x19E0 +#define USB3_DP_QSERDES_RXB_SIGDET_CAL_CTRL1 0x19E4 +#define USB3_DP_QSERDES_RXB_SIGDET_CAL_CTRL2_AND_CDR_LOCK_EDGE 0x19E8 +#define USB3_DP_QSERDES_RXB_CDR_LOCK_ON_EDGE_DURATION 0x19EC +#define USB3_DP_QSERDES_RXB_CDR_LOCK_ON_EDGE_THRESH 0x19F0 +#define USB3_DP_QSERDES_RXB_RX_ADAPTOR_CNTRL 0x19F4 +#define USB3_DP_QSERDES_RXB_SIGDET_CAL_TRIM 0x19F8 +#define USB3_DP_QSERDES_RXB_CAL_POST_WRAP 0x19FC + +/* Module: USB3_DP_PHY_USB3_PCS_MISC_USB3_PCS_MISC_USB3_PCS_MISC */ +#define USB3_DP_PCS_MISC_TYPEC_CTRL 0x1A00 +#define USB3_DP_PCS_MISC_TYPEC_PWRDN_CTRL 0x1A04 +#define USB3_DP_PCS_MISC_PCS_MISC_CONFIG1 0x1A08 +#define USB3_DP_PCS_MISC_CLAMP_ENABLE 0x1A0C +#define USB3_DP_PCS_MISC_TYPEC_STATUS 0x1A10 +#define USB3_DP_PCS_MISC_PLACEHOLDER_STATUS 0x1A14 + +/* Module: USB3_DP_PHY_USB3_PCS_LN_USB3_PCS_LN_USB3_PCS_LANE */ +#define USB3_DP_PCS_LN_PCS_STATUS1 0x1B00 +#define USB3_DP_PCS_LN_PCS_STATUS2 0x1B04 +#define USB3_DP_PCS_LN_PCS_STATUS2_CLEAR 0x1B08 +#define USB3_DP_PCS_LN_PCS_STATUS3 0x1B0C +#define USB3_DP_PCS_LN_BIST_CHK_ERR_CNT_L_STATUS 0x1B10 +#define USB3_DP_PCS_LN_BIST_CHK_ERR_CNT_H_STATUS 0x1B14 +#define USB3_DP_PCS_LN_BIST_CHK_STATUS 0x1B18 +#define USB3_DP_PCS_LN_INSIG_SW_CTRL1 0x1B1C +#define USB3_DP_PCS_LN_INSIG_MX_CTRL1 0x1B20 +#define USB3_DP_PCS_LN_OUTSIG_SW_CTRL1 0x1B24 +#define USB3_DP_PCS_LN_OUTSIG_MX_CTRL1 0x1B28 +#define USB3_DP_PCS_LN_TEST_CONTROL1 0x1B2C +#define USB3_DP_PCS_LN_BIST_CTRL 0x1B30 +#define USB3_DP_PCS_LN_PRBS_SEED0 0x1B34 +#define USB3_DP_PCS_LN_PRBS_SEED1 0x1B38 +#define USB3_DP_PCS_LN_FIXED_PAT_CTRL 0x1B3C +#define USB3_DP_PCS_LN_EQ_CONFIG 0x1B40 +#define USB3_DP_PCS_LN_TEST_CONTROL2 0x1B44 +#define USB3_DP_PCS_LN_TEST_CONTROL3 0x1B48 + +/* Module: USB3_DP_PHY_USB3_PCS_USB3_PCS_USB3_PCS */ +#define USB3_DP_PCS_SW_RESET 0x1C00 +#define USB3_DP_PCS_REVISION_ID0 0x1C04 +#define USB3_DP_PCS_REVISION_ID1 0x1C08 +#define USB3_DP_PCS_REVISION_ID2 0x1C0C +#define USB3_DP_PCS_REVISION_ID3 0x1C10 +#define USB3_DP_PCS_PCS_STATUS1 0x1C14 +#define USB3_DP_PCS_PCS_STATUS2 0x1C18 +#define USB3_DP_PCS_PCS_STATUS3 0x1C1C +#define USB3_DP_PCS_PCS_STATUS4 0x1C20 +#define USB3_DP_PCS_PCS_STATUS5 0x1C24 +#define USB3_DP_PCS_PCS_STATUS6 0x1C28 +#define USB3_DP_PCS_PCS_STATUS7 0x1C2C +#define USB3_DP_PCS_DEBUG_BUS_0_STATUS 0x1C30 +#define USB3_DP_PCS_DEBUG_BUS_1_STATUS 0x1C34 +#define USB3_DP_PCS_DEBUG_BUS_2_STATUS 0x1C38 +#define USB3_DP_PCS_DEBUG_BUS_3_STATUS 0x1C3C +#define USB3_DP_PCS_POWER_DOWN_CONTROL 0x1C40 +#define USB3_DP_PCS_START_CONTROL 0x1C44 +#define USB3_DP_PCS_INSIG_SW_CTRL1 0x1C48 +#define USB3_DP_PCS_INSIG_SW_CTRL2 0x1C4C +#define USB3_DP_PCS_INSIG_SW_CTRL3 0x1C50 +#define USB3_DP_PCS_INSIG_SW_CTRL4 0x1C54 +#define USB3_DP_PCS_INSIG_SW_CTRL5 0x1C58 +#define USB3_DP_PCS_INSIG_SW_CTRL6 0x1C5C +#define USB3_DP_PCS_INSIG_SW_CTRL7 0x1C60 +#define USB3_DP_PCS_INSIG_SW_CTRL8 0x1C64 +#define USB3_DP_PCS_INSIG_MX_CTRL1 0x1C68 +#define USB3_DP_PCS_INSIG_MX_CTRL2 0x1C6C +#define USB3_DP_PCS_INSIG_MX_CTRL3 0x1C70 +#define USB3_DP_PCS_INSIG_MX_CTRL4 0x1C74 +#define USB3_DP_PCS_INSIG_MX_CTRL5 0x1C78 +#define USB3_DP_PCS_INSIG_MX_CTRL7 0x1C7C +#define USB3_DP_PCS_INSIG_MX_CTRL8 0x1C80 +#define USB3_DP_PCS_OUTSIG_SW_CTRL1 0x1C84 +#define USB3_DP_PCS_OUTSIG_MX_CTRL1 0x1C88 +#define USB3_DP_PCS_CLAMP_ENABLE 0x1C8C +#define USB3_DP_PCS_POWER_STATE_CONFIG1 0x1C90 +#define USB3_DP_PCS_POWER_STATE_CONFIG2 0x1C94 +#define USB3_DP_PCS_FLL_CNTRL1 0x1C98 +#define USB3_DP_PCS_FLL_CNTRL2 0x1C9C +#define USB3_DP_PCS_FLL_CNT_VAL_L 0x1CA0 +#define USB3_DP_PCS_FLL_CNT_VAL_H_TOL 0x1CA4 +#define USB3_DP_PCS_FLL_MAN_CODE 0x1CA8 +#define USB3_DP_PCS_TEST_CONTROL1 0x1CAC +#define USB3_DP_PCS_TEST_CONTROL2 0x1CB0 +#define USB3_DP_PCS_TEST_CONTROL3 0x1CB4 +#define USB3_DP_PCS_TEST_CONTROL4 0x1CB8 +#define USB3_DP_PCS_TEST_CONTROL5 0x1CBC +#define USB3_DP_PCS_TEST_CONTROL6 0x1CC0 +#define USB3_DP_PCS_LOCK_DETECT_CONFIG1 0x1CC4 +#define USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x1CC8 +#define USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x1CCC +#define USB3_DP_PCS_LOCK_DETECT_CONFIG4 0x1CD0 +#define USB3_DP_PCS_LOCK_DETECT_CONFIG5 0x1CD4 +#define USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x1CD8 +#define USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x1CDC +#define USB3_DP_PCS_REFGEN_REQ_CONFIG2 0x1CE0 +#define USB3_DP_PCS_REFGEN_REQ_CONFIG3 0x1CE4 +#define USB3_DP_PCS_BIST_CTRL 0x1CE8 +#define USB3_DP_PCS_PRBS_POLY0 0x1CEC +#define USB3_DP_PCS_PRBS_POLY1 0x1CF0 +#define USB3_DP_PCS_FIXED_PAT0 0x1CF4 +#define USB3_DP_PCS_FIXED_PAT1 0x1CF8 +#define USB3_DP_PCS_FIXED_PAT2 0x1CFC +#define USB3_DP_PCS_FIXED_PAT3 0x1D00 +#define USB3_DP_PCS_FIXED_PAT4 0x1D04 +#define USB3_DP_PCS_FIXED_PAT5 0x1D08 +#define USB3_DP_PCS_FIXED_PAT6 0x1D0C +#define USB3_DP_PCS_FIXED_PAT7 0x1D10 +#define USB3_DP_PCS_FIXED_PAT8 0x1D14 +#define USB3_DP_PCS_FIXED_PAT9 0x1D18 +#define USB3_DP_PCS_FIXED_PAT10 0x1D1C +#define USB3_DP_PCS_FIXED_PAT11 0x1D20 +#define USB3_DP_PCS_FIXED_PAT12 0x1D24 +#define USB3_DP_PCS_FIXED_PAT13 0x1D28 +#define USB3_DP_PCS_FIXED_PAT14 0x1D2C +#define USB3_DP_PCS_FIXED_PAT15 0x1D30 +#define USB3_DP_PCS_TXMGN_CONFIG 0x1D34 +#define USB3_DP_PCS_G12S1_TXMGN_V0 0x1D38 +#define USB3_DP_PCS_G12S1_TXMGN_V1 0x1D3C +#define USB3_DP_PCS_G12S1_TXMGN_V2 0x1D40 +#define USB3_DP_PCS_G12S1_TXMGN_V3 0x1D44 +#define USB3_DP_PCS_G12S1_TXMGN_V4 0x1D48 +#define USB3_DP_PCS_G12S1_TXMGN_V0_RS 0x1D4C +#define USB3_DP_PCS_G12S1_TXMGN_V1_RS 0x1D50 +#define USB3_DP_PCS_G12S1_TXMGN_V2_RS 0x1D54 +#define USB3_DP_PCS_G12S1_TXMGN_V3_RS 0x1D58 +#define USB3_DP_PCS_G12S1_TXMGN_V4_RS 0x1D5C +#define USB3_DP_PCS_G3S2_TXMGN_MAIN 0x1D60 +#define USB3_DP_PCS_G3S2_TXMGN_MAIN_RS 0x1D64 +#define USB3_DP_PCS_G12S1_TXDEEMPH_M6DB 0x1D68 +#define USB3_DP_PCS_G12S1_TXDEEMPH_M3P5DB 0x1D6C +#define USB3_DP_PCS_G3S2_PRE_GAIN 0x1D70 +#define USB3_DP_PCS_G3S2_POST_GAIN 0x1D74 +#define USB3_DP_PCS_G3S2_PRE_POST_OFFSET 0x1D78 +#define USB3_DP_PCS_G3S2_PRE_GAIN_RS 0x1D7C +#define USB3_DP_PCS_G3S2_POST_GAIN_RS 0x1D80 +#define USB3_DP_PCS_G3S2_PRE_POST_OFFSET_RS 0x1D84 +#define USB3_DP_PCS_RX_SIGDET_LVL 0x1D88 +#define USB3_DP_PCS_RX_SIGDET_DTCT_CNTRL 0x1D8C +#define USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0x1D90 +#define USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x1D94 +#define USB3_DP_PCS_RATE_SLEW_CNTRL1 0x1D98 +#define USB3_DP_PCS_RATE_SLEW_CNTRL2 0x1D9C +#define USB3_DP_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1DA0 +#define USB3_DP_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1DA4 +#define USB3_DP_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1DA8 +#define USB3_DP_PCS_TSYNC_RSYNC_TIME 0x1DAC +#define USB3_DP_PCS_CDR_RESET_TIME 0x1DB0 +#define USB3_DP_PCS_TSYNC_DLY_TIME 0x1DB4 +#define USB3_DP_PCS_ELECIDLE_DLY_SEL 0x1DB8 +#define USB3_DP_PCS_CMN_ACK_OUT_SEL 0x1DBC +#define USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x1DC0 +#define USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x1DC4 +#define USB3_DP_PCS_ALIGN_DETECT_CONFIG3 0x1DC8 +#define USB3_DP_PCS_ALIGN_DETECT_CONFIG4 0x1DCC +#define USB3_DP_PCS_PCS_TX_RX_CONFIG 0x1DD0 +#define USB3_DP_PCS_RX_IDLE_DTCT_CNTRL 0x1DD4 +#define USB3_DP_PCS_RX_DCC_CAL_CONFIG 0x1DD8 +#define USB3_DP_PCS_EQ_CONFIG1 0x1DDC +#define USB3_DP_PCS_EQ_CONFIG2 0x1DE0 +#define USB3_DP_PCS_EQ_CONFIG3 0x1DE4 +#define USB3_DP_PCS_EQ_CONFIG4 0x1DE8 +#define USB3_DP_PCS_EQ_CONFIG5 0x1DEC + +/* Module: USB3_DP_PHY_USB3_PCS_AON_USB3_PCS_AON_USB3_PCS_AON */ +#define USB3_DP_PCS_AON_CLAMP_ENABLE 0x1E00 + +/* Module: USB3_DP_PHY_USB3_PCS_USB3_USB3_PCS_USB3_USB3_PCS_USB3 */ +#define USB3_DP_PCS_USB3_POWER_STATE_CONFIG1 0x1F00 +#define USB3_DP_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x1F04 +#define USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x1F08 +#define USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x1F0C +#define USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x1F10 +#define USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x1F14 +#define USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x1F18 +#define USB3_DP_PCS_USB3_LFPS_TX_ECSTART 0x1F1C +#define USB3_DP_PCS_USB3_LFPS_PER_TIMER_VAL 0x1F20 +#define USB3_DP_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x1F24 +#define USB3_DP_PCS_USB3_LFPS_CONFIG1 0x1F28 +#define USB3_DP_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x1F2C +#define USB3_DP_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x1F30 +#define USB3_DP_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x1F34 +#define USB3_DP_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x1F38 +#define USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x1F3C +#define USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x1F40 +#define USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x1F44 +#define USB3_DP_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x1F48 +#define USB3_DP_PCS_USB3_ARCVR_DTCT_CM_DLY 0x1F4C +#define USB3_DP_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x1F50 +#define USB3_DP_PCS_USB3_ALFPS_DEGLITCH_VAL 0x1F54 +#define USB3_DP_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x1F58 +#define USB3_DP_PCS_USB3_TEST_CONTROL 0x1F5C +#define USB3_DP_PCS_USB3_RXTERMINATION_DLY_SEL 0x1F60 + +#endif /* _DT_BINDINGS_PHY_QCOM_4NM_QMP_COMBO_USB_H */ diff --git a/include/dt-bindings/power/qcom-aoss-qmp.h b/include/dt-bindings/power/qcom-aoss-qmp.h new file mode 100644 index 000000000000..ec336d31dee4 --- /dev/null +++ b/include/dt-bindings/power/qcom-aoss-qmp.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018, Linaro Ltd. */ + +#ifndef __DT_BINDINGS_POWER_QCOM_AOSS_QMP_H +#define __DT_BINDINGS_POWER_QCOM_AOSS_QMP_H + +#define AOSS_QMP_LS_CDSP 0 +#define AOSS_QMP_LS_LPASS 1 +#define AOSS_QMP_LS_MODEM 2 +#define AOSS_QMP_LS_SLPI 3 +#define AOSS_QMP_LS_SPSS 4 +#define AOSS_QMP_LS_VENUS 5 + +#endif diff --git a/include/dt-bindings/soc/qcom,dcc_v2.h b/include/dt-bindings/soc/qcom,dcc_v2.h new file mode 100644 index 000000000000..2898ab083c45 --- /dev/null +++ b/include/dt-bindings/soc/qcom,dcc_v2.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2019,2021 The Linux Foundation. All rights reserved. + */ + +#ifndef __DT_BINDINGS_QCOM_DCC_V2_H +#define __DT_BINDINGS_QCOM_DCC_V2_H + +#define DCC_READ 0 +#define DCC_WRITE 1 +#define DCC_LOOP 2 +#define DCC_READ_WRITE 3 + +#endif diff --git a/include/dt-bindings/thermal/thermal_qti.h b/include/dt-bindings/thermal/thermal_qti.h new file mode 100644 index 000000000000..44c9e11a5ab4 --- /dev/null +++ b/include/dt-bindings/thermal/thermal_qti.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +#ifndef _DT_BINDINGS_QTI_THERMAL_H +#define _DT_BINDINGS_QTI_THERMAL_H + +#define THERMAL_MAX_LIMIT (THERMAL_NO_LIMIT - 1) +#define AGGREGATE_COEFF_VALUE 0 +#define AGGREGATE_MAX_VALUE 1 +#define AGGREGATE_MIN_VALUE 2 + +#define QMI_PA 0 +#define QMI_PA_1 1 +#define QMI_PA_2 2 +#define QMI_QFE_PA_0 3 +#define QMI_QFE_WTR_0 4 +#define QMI_MODEM_TSENS 5 +#define QMI_QFE_MMW_0 6 +#define QMI_QFE_MMW_1 7 +#define QMI_QFE_MMW_2 8 +#define QMI_QFE_MMW_3 9 +#define QMI_XO_THERM 10 +#define QMI_QFE_PA_MDM 11 +#define QMI_QFE_PA_WTR 12 +#define QMI_QFE_MMW_STREAMER_0 13 +#define QMI_QFE_MMW_0_MOD 14 +#define QMI_QFE_MMW_1_MOD 15 +#define QMI_QFE_MMW_2_MOD 16 +#define QMI_QFE_MMW_3_MOD 17 +#define QMI_QFE_RET_PA_0 18 +#define QMI_QFE_WTR_PA_0 19 +#define QMI_QFE_WTR_PA_1 20 +#define QMI_QFE_WTR_PA_2 21 +#define QMI_QFE_WTR_PA_3 22 +#define QMI_SYS_THERM_1 23 +#define QMI_SYS_THERM_2 24 +#define QMI_MODEM_TSENS_1 25 +#define QMI_MMW_PA1 26 +#define QMI_MMW_PA2 27 +#define QMI_MMW_PA3 28 +#define QMI_SDR_MMW 29 +#define QMI_QTM_THERM 30 +#define QMI_BCL_WARN 31 +#define QMI_SDR0_PA0 32 +#define QMI_SDR0_PA1 33 +#define QMI_SDR0_PA2 34 +#define QMI_SDR0_PA3 35 +#define QMI_SDR0_PA4 36 +#define QMI_SDR0_PA5 37 +#define QMI_SDR0 38 +#define QMI_SDR1_PA0 39 +#define QMI_SDR1_PA1 40 +#define QMI_SDR1_PA2 41 +#define QMI_SDR1_PA3 42 +#define QMI_SDR1_PA4 43 +#define QMI_SDR1_PA5 44 +#define QMI_SDR1 45 +#define QMI_MMW0 46 +#define QMI_MMW1 47 +#define QMI_MMW2 48 +#define QMI_MMW3 49 +#define QMI_MMW_IFIC0 50 +#define QMI_SUB1_MODEM_CFG 51 +#define QMI_SUB1_LTE_CC 52 +#define QMI_SUB1_MCG_FR1_CC 53 +#define QMI_SUB1_MCG_FR2_CC 54 +#define QMI_SUB1_SCG_FR1_CC 55 +#define QMI_SUB1_SCG_FR2_CC 56 +#define QMI_SUB2_MODEM_CFG 57 +#define QMI_SUB2_LTE_CC 58 +#define QMI_SUB2_MCG_FR1_CC 59 +#define QMI_SUB2_MCG_FR2_CC 60 +#define QMI_SUB2_SCG_FR1_CC 61 +#define QMI_SUB2_SCG_FR2_CC 62 +#define QMI_NSP_ISENSE_TRIM 63 +#define QMI_EPM0 64 +#define QMI_EPM1 65 +#define QMI_EPM2 66 +#define QMI_EPM3 67 +#define QMI_EPM4 68 +#define QMI_EPM5 69 +#define QMI_EPM6 70 +#define QMI_EPM7 71 +#define QMI_SDR0_PA 72 +#define QMI_SDR1_PA 73 + +#define QMI_MODEM_INST_ID 0x0 +#define QMI_ADSP_INST_ID 0x1 +#define QMI_CDSP_INST_ID 0x43 +#define QMI_SLPI_INST_ID 0x53 +#define QMI_MODEM_NR_INST_ID 0x64 + +#endif