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Merge 65b55d4c85 ("Merge tag 'arm-soc-fixes-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc") into android-mainline

Browse Source 
Steps on the way to 5.10-rc2

Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Change-Id: I2aae8375aa349bd63596d4bd29e50e36993c764f
This commit is contained in:
Greg Kroah-Hartman 2020-11-02 11:04:03 +01:00
commit c13605829f
159 changed files with 1203 additions and 605 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
CREDITS
View File

@ -1910,6 +1910,15 @@ S: 660 Harvard Ave. #7
S: Santa Clara, CA 95051
S: USA
N: Kukjin Kim
E: kgene@kernel.org
D: Samsung S3C, S5P and Exynos ARM architectures
N: Sangbeom Kim
E: sbkim73@samsung.com
D: Samsung SoC Audio (ASoC) drivers
D: Samsung PMIC (RTC, regulators, MFD) drivers
N: Russell King
E: rmk@arm.linux.org.uk
D: Linux/arm integrator, maintainer & hacker

4
Documentation/devicetree/bindings/display/panel/mantix,mlaf057we51-x.yaml
View File

@ -37,6 +37,9 @@ properties:
reset-gpios: true
'mantix,tp-rstn-gpios':
description: second reset line that triggers DSI config load
backlight: true
required:
@ -63,6 +66,7 @@ examples:
avee-supply = <&reg_avee>;
vddi-supply = <&reg_1v8_p>;
reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
mantix,tp-rstn-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
backlight = <&backlight>;
};
};

3
Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml
View File

@ -33,6 +33,9 @@ properties:
- const: allwinner,sun4i-a10-system-control
- const: allwinner,sun8i-a23-system-control
- const: allwinner,sun8i-h3-system-control
- items:
- const: allwinner,sun8i-v3s-system-control
- const: allwinner,sun8i-h3-system-control
- items:
- const: allwinner,sun8i-r40-system-control
- const: allwinner,sun4i-a10-system-control

11
MAINTAINERS
View File

@ -2375,7 +2375,6 @@ F: sound/soc/rockchip/
N: rockchip
ARM/SAMSUNG EXYNOS ARM ARCHITECTURES
M: Kukjin Kim <kgene@kernel.org>
M: Krzysztof Kozlowski <krzk@kernel.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-samsung-soc@vger.kernel.org
@ -2642,10 +2641,8 @@ F: drivers/pinctrl/visconti/
N: visconti
ARM/UNIPHIER ARCHITECTURE
M: Masahiro Yamada <yamada.masahiro@socionext.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier.git
S: Orphan
F: Documentation/devicetree/bindings/arm/socionext/uniphier.yaml
F: Documentation/devicetree/bindings/gpio/socionext,uniphier-gpio.yaml
F: Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml
@ -5006,9 +5003,8 @@ T: git git://linuxtv.org/media_tree.git
F: drivers/media/platform/sti/delta
DENALI NAND DRIVER
M: Masahiro Yamada <yamada.masahiro@socionext.com>
L: linux-mtd@lists.infradead.org
S: Supported
S: Orphan
F: drivers/mtd/nand/raw/denali*
DESIGNWARE EDMA CORE IP DRIVER
@ -15385,7 +15381,6 @@ F: security/safesetid/
SAMSUNG AUDIO (ASoC) DRIVERS
M: Krzysztof Kozlowski <krzk@kernel.org>
M: Sangbeom Kim <sbkim73@samsung.com>
M: Sylwester Nawrocki <s.nawrocki@samsung.com>
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
S: Supported
@ -15420,7 +15415,6 @@ S: Maintained
F: drivers/platform/x86/samsung-laptop.c
SAMSUNG MULTIFUNCTION PMIC DEVICE DRIVERS
M: Sangbeom Kim <sbkim73@samsung.com>
M: Krzysztof Kozlowski <krzk@kernel.org>
M: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
L: linux-kernel@vger.kernel.org
@ -15502,7 +15496,6 @@ F: include/linux/clk/samsung.h
F: include/linux/platform_data/clk-s3c2410.h
SAMSUNG SPI DRIVERS
M: Kukjin Kim <kgene@kernel.org>
M: Krzysztof Kozlowski <krzk@kernel.org>
M: Andi Shyti <andi@etezian.org>
L: linux-spi@vger.kernel.org

4
arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts
View File

@ -227,12 +227,12 @@ &ssp3 {
/delete-property/ #size-cells;
spi-slave;
status = "okay";
ready-gpio = <&gpio 125 GPIO_ACTIVE_HIGH>;
ready-gpios = <&gpio 125 GPIO_ACTIVE_HIGH>;
slave {
compatible = "olpc,xo1.75-ec";
spi-cpha;
cmd-gpio = <&gpio 155 GPIO_ACTIVE_HIGH>;
cmd-gpios = <&gpio 155 GPIO_ACTIVE_HIGH>;
};
};

2
arch/arm/boot/dts/mmp3.dtsi
View File

@ -296,6 +296,7 @@ camera0: camera@d420a000 {
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&soc_clocks MMP2_CLK_CCIC0>;
clock-names = "axi";
power-domains = <&soc_clocks MMP3_POWER_DOMAIN_CAMERA>;
#clock-cells = <0>;
clock-output-names = "mclk";
status = "disabled";
@ -307,6 +308,7 @@ camera1: camera@d420a800 {
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&soc_clocks MMP2_CLK_CCIC1>;
clock-names = "axi";
power-domains = <&soc_clocks MMP3_POWER_DOMAIN_CAMERA>;
#clock-cells = <0>;
clock-output-names = "mclk";
status = "disabled";

15
arch/arm/boot/dts/stm32mp157c-ed1.dts
View File

@ -89,6 +89,14 @@ sd_switch: regulator-sd_switch {
states = <1800000 0x1>,
<2900000 0x0>;
};
vin: vin {
compatible = "regulator-fixed";
regulator-name = "vin";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
};
&adc {
@ -150,11 +158,18 @@ pmic: stpmic@33 {
regulators {
compatible = "st,stpmic1-regulators";
buck1-supply = <&vin>;
buck2-supply = <&vin>;
buck3-supply = <&vin>;
buck4-supply = <&vin>;
ldo1-supply = <&v3v3>;
ldo2-supply = <&v3v3>;
ldo3-supply = <&vdd_ddr>;
ldo4-supply = <&vin>;
ldo5-supply = <&v3v3>;
ldo6-supply = <&v3v3>;
vref_ddr-supply = <&vin>;
boost-supply = <&vin>;
pwr_sw1-supply = <&bst_out>;
pwr_sw2-supply = <&bst_out>;

17
arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
View File

@ -80,6 +80,14 @@ sound {
dais = <&sai2a_port &sai2b_port &i2s2_port>;
status = "okay";
};
vin: vin {
compatible = "regulator-fixed";
regulator-name = "vin";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
};
&adc {
@ -240,9 +248,18 @@ pmic: stpmic@33 {
regulators {
compatible = "st,stpmic1-regulators";
buck1-supply = <&vin>;
buck2-supply = <&vin>;
buck3-supply = <&vin>;
buck4-supply = <&vin>;
ldo1-supply = <&v3v3>;
ldo2-supply = <&vin>;
ldo3-supply = <&vdd_ddr>;
ldo4-supply = <&vin>;
ldo5-supply = <&vin>;
ldo6-supply = <&v3v3>;
vref_ddr-supply = <&vin>;
boost-supply = <&vin>;
pwr_sw1-supply = <&bst_out>;
pwr_sw2-supply = <&bst_out>;

2
arch/arm/boot/dts/sun4i-a10.dtsi
View File

@ -143,7 +143,7 @@ map0 {
trips {
cpu_alert0: cpu-alert0 {
/* milliCelsius */
temperature = <850000>;
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};

1
arch/arm/configs/imx_v4_v5_defconfig
View File

@ -93,6 +93,7 @@ CONFIG_SPI=y
CONFIG_SPI_IMX=y
CONFIG_SPI_SPIDEV=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_MXC=y
CONFIG_W1=y
CONFIG_W1_MASTER_MXC=y
CONFIG_W1_SLAVE_THERM=y

1
arch/arm/configs/imx_v6_v7_defconfig
View File

@ -217,6 +217,7 @@ CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCF857X=y
CONFIG_GPIO_STMPE=y
CONFIG_GPIO_74X164=y
CONFIG_GPIO_MXC=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_RESET_SYSCON_POWEROFF=y

1
arch/arm/configs/multi_v5_defconfig
View File

@ -166,6 +166,7 @@ CONFIG_SPI_IMX=y
CONFIG_SPI_ORION=y
CONFIG_GPIO_ASPEED=m
CONFIG_GPIO_ASPEED_SGPIO=y
CONFIG_GPIO_MXC=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_RESET_QNAP=y

1
arch/arm/configs/multi_v7_defconfig
View File

@ -465,6 +465,7 @@ CONFIG_GPIO_PALMAS=y
CONFIG_GPIO_TPS6586X=y
CONFIG_GPIO_TPS65910=y
CONFIG_GPIO_TWL4030=y
CONFIG_GPIO_MXC=y
CONFIG_POWER_AVS=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_POWER_RESET_AS3722=y

7
arch/arm/mach-mvebu/coherency_ll.S
View File

@ -35,13 +35,8 @@ ENTRY(ll_get_coherency_base)
/*
* MMU is disabled, use the physical address of the coherency
* base address. However, if the coherency fabric isn't mapped
* (i.e its virtual address is zero), it means coherency is
* not enabled, so we return 0.
* base address, (or 0x0 if the coherency fabric is not mapped)
*/
ldr r1, =coherency_base
cmp r1, #0
beq 2f
adr r1, 3f
ldr r3, [r1]
ldr r1, [r1, r3]

1
arch/arm64/Kconfig.platforms
View File

@ -54,6 +54,7 @@ config ARCH_BCM_IPROC
config ARCH_BERLIN
bool "Marvell Berlin SoC Family"
select DW_APB_ICTL
select DW_APB_TIMER_OF
select GPIOLIB
select PINCTRL
help

6
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
View File

@ -584,3 +584,9 @@ &uart_AO {
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&usb {
status = "okay";
dr_mode = "otg";
vbus-supply = <&usb_pwr>;
};

52
arch/arm64/boot/dts/amlogic/meson-axg.dtsi
View File

@ -171,6 +171,46 @@ soc {
#size-cells = <2>;
ranges;
usb: usb@ffe09080 {
compatible = "amlogic,meson-axg-usb-ctrl";
reg = <0x0 0xffe09080 0x0 0x20>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
clock-names = "usb_ctrl", "ddr";
resets = <&reset RESET_USB_OTG>;
dr_mode = "otg";
phys = <&usb2_phy1>;
phy-names = "usb2-phy1";
dwc2: usb@ff400000 {
compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
reg = <0x0 0xff400000 0x0 0x40000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_USB1>;
clock-names = "otg";
phys = <&usb2_phy1>;
dr_mode = "peripheral";
g-rx-fifo-size = <192>;
g-np-tx-fifo-size = <128>;
g-tx-fifo-size = <128 128 16 16 16>;
};
dwc3: usb@ff500000 {
compatible = "snps,dwc3";
reg = <0x0 0xff500000 0x0 0x100000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
maximum-speed = "high-speed";
snps,dis_u2_susphy_quirk;
};
};
ethmac: ethernet@ff3f0000 {
compatible = "amlogic,meson-axg-dwmac",
"snps,dwmac-3.70a",
@ -187,6 +227,8 @@ ethmac: ethernet@ff3f0000 {
"timing-adjustment";
rx-fifo-depth = <4096>;
tx-fifo-depth = <2048>;
resets = <&reset RESET_ETHERNET>;
reset-names = "stmmaceth";
status = "disabled";
};
@ -1734,6 +1776,16 @@ sd_emmc_c: mmc@7000 {
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_C>;
};
usb2_phy1: phy@9020 {
compatible = "amlogic,meson-gxl-usb2-phy";
#phy-cells = <0>;
reg = <0x0 0x9020 0x0 0x20>;
clocks = <&clkc CLKID_USB>;
clock-names = "phy";
resets = <&reset RESET_USB_OTG>;
reset-names = "phy";
};
};
sram: sram@fffc0000 {

6
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
View File

@ -209,7 +209,7 @@ map {
};
ethmac: ethernet@ff3f0000 {
compatible = "amlogic,meson-axg-dwmac",
compatible = "amlogic,meson-g12a-dwmac",
"snps,dwmac-3.70a",
"snps,dwmac";
reg = <0x0 0xff3f0000 0x0 0x10000>,
@ -224,6 +224,8 @@ ethmac: ethernet@ff3f0000 {
"timing-adjustment";
rx-fifo-depth = <4096>;
tx-fifo-depth = <2048>;
resets = <&reset RESET_ETHERNET>;
reset-names = "stmmaceth";
status = "disabled";
mdio0: mdio {
@ -282,6 +284,8 @@ apb_efuse: bus@30000 {
hwrng: rng@218 {
compatible = "amlogic,meson-rng";
reg = <0x0 0x218 0x0 0x4>;
clocks = <&clkc CLKID_RNG0>;
clock-names = "core";
};
};

2
arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts
View File

@ -19,7 +19,7 @@ &vddcpu_a {
regulator-min-microvolt = <680000>;
regulator-max-microvolt = <1040000>;
pwms = <&pwm_AO_cd 1 1500 0>;
pwms = <&pwm_ab 0 1500 0>;
};
&vddcpu_b {

3
arch/arm64/boot/dts/amlogic/meson-gx.dtsi
View File

@ -13,6 +13,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/meson-gxbb-power.h>
#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@ -575,6 +576,8 @@ ethmac: ethernet@c9410000 {
interrupt-names = "macirq";
rx-fifo-depth = <4096>;
tx-fifo-depth = <2048>;
resets = <&reset RESET_ETHERNET>;
reset-names = "stmmaceth";
power-domains = <&pwrc PWRC_GXBB_ETHERNET_MEM_ID>;
status = "disabled";
};

10
arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts
View File

@ -20,17 +20,23 @@ / {
compatible = "globalscale,espressobin-v7-emmc", "globalscale,espressobin-v7",
"globalscale,espressobin", "marvell,armada3720",
"marvell,armada3710";
aliases {
/* ethernet1 is wan port */
ethernet1 = &switch0port3;
ethernet3 = &switch0port1;
};
};
&switch0 {
ports {
port@1 {
switch0port1: port@1 {
reg = <1>;
label = "lan1";
phy-handle = <&switch0phy0>;
};
port@3 {
switch0port3: port@3 {
reg = <3>;
label = "wan";
phy-handle = <&switch0phy2>;

10
arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts
View File

@ -19,17 +19,23 @@ / {
model = "Globalscale Marvell ESPRESSOBin Board V7";
compatible = "globalscale,espressobin-v7", "globalscale,espressobin",
"marvell,armada3720", "marvell,armada3710";
aliases {
/* ethernet1 is wan port */
ethernet1 = &switch0port3;
ethernet3 = &switch0port1;
};
};
&switch0 {
ports {
port@1 {
switch0port1: port@1 {
reg = <1>;
label = "lan1";
phy-handle = <&switch0phy0>;
};
port@3 {
switch0port3: port@3 {
reg = <3>;
label = "wan";
phy-handle = <&switch0phy2>;

12
arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
View File

@ -13,6 +13,10 @@
/ {
aliases {
ethernet0 = &eth0;
/* for dsa slave device */
ethernet1 = &switch0port1;
ethernet2 = &switch0port2;
ethernet3 = &switch0port3;
serial0 = &uart0;
serial1 = &uart1;
};
@ -120,7 +124,7 @@ ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
switch0port0: port@0 {
reg = <0>;
label = "cpu";
ethernet = <&eth0>;
@ -131,19 +135,19 @@ fixed-link {
};
};
port@1 {
switch0port1: port@1 {
reg = <1>;
label = "wan";
phy-handle = <&switch0phy0>;
};
port@2 {
switch0port2: port@2 {
reg = <2>;
label = "lan0";
phy-handle = <&switch0phy1>;
};
port@3 {
switch0port3: port@3 {
reg = <3>;
label = "lan1";
phy-handle = <&switch0phy2>;

1
arch/arm64/configs/defconfig
View File

@ -500,6 +500,7 @@ CONFIG_GPIO_ALTERA=m
CONFIG_GPIO_DWAPB=y
CONFIG_GPIO_MB86S7X=y
CONFIG_GPIO_MPC8XXX=y
CONFIG_GPIO_MXC=y
CONFIG_GPIO_PL061=y
CONFIG_GPIO_RCAR=y
CONFIG_GPIO_UNIPHIER=y

13
drivers/acpi/button.c
View File

@ -73,19 +73,6 @@ MODULE_DEVICE_TABLE(acpi, button_device_ids);
/* Please keep this list sorted alphabetically by vendor and model */
static const struct dmi_system_id dmi_lid_quirks[] = {
{
/*
* Acer Switch 10 SW5-012. _LID method messes with home and
* power button GPIO IRQ settings causing an interrupt storm on
* both GPIOs. This is unfixable without a DSDT override, so we
* have to disable the lid-switch functionality altogether :|
*/
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
DMI_MATCH(DMI_PRODUCT_NAME, "Aspire SW5-012"),
},
.driver_data = (void *)(long)ACPI_BUTTON_LID_INIT_DISABLED,
},
{
/* GP-electronic T701, _LID method points to a floating GPIO */
.matches = {

3
drivers/acpi/dock.c
View File

@ -231,7 +231,8 @@ static void hot_remove_dock_devices(struct dock_station *ds)
* between them).
*/
list_for_each_entry_reverse(dd, &ds->dependent_devices, list)
dock_hotplug_event(dd, ACPI_NOTIFY_EJECT_REQUEST, false);
dock_hotplug_event(dd, ACPI_NOTIFY_EJECT_REQUEST,
DOCK_CALL_HANDLER);
list_for_each_entry_reverse(dd, &ds->dependent_devices, list)
acpi_bus_trim(dd->adev);

2
drivers/acpi/nfit/core.c
View File

@ -1564,7 +1564,7 @@ static ssize_t format1_show(struct device *dev,
le16_to_cpu(nfit_dcr->dcr->code));
break;
}
if (rc != ENXIO)
if (rc != -ENXIO)
break;
}
mutex_unlock(&acpi_desc->init_mutex);

4
drivers/base/core.c
View File

@ -4264,6 +4264,7 @@ static inline bool fwnode_is_primary(struct fwnode_handle *fwnode)
*/
void set_primary_fwnode(struct device *dev, struct fwnode_handle *fwnode)
{
struct device *parent = dev->parent;
struct fwnode_handle *fn = dev->fwnode;
if (fwnode) {
@ -4278,7 +4279,8 @@ void set_primary_fwnode(struct device *dev, struct fwnode_handle *fwnode)
} else {
if (fwnode_is_primary(fn)) {
dev->fwnode = fn->secondary;
fn->secondary = NULL;
if (!(parent && fn == parent->fwnode))
fn->secondary = ERR_PTR(-ENODEV);
} else {
dev->fwnode = NULL;
}

2
drivers/cpufreq/Kconfig
View File

@ -78,6 +78,7 @@ config CPU_FREQ_DEFAULT_GOV_USERSPACE
config CPU_FREQ_DEFAULT_GOV_ONDEMAND
bool "ondemand"
depends on !(X86_INTEL_PSTATE && SMP)
select CPU_FREQ_GOV_ONDEMAND
select CPU_FREQ_GOV_PERFORMANCE
help
@ -90,6 +91,7 @@ config CPU_FREQ_DEFAULT_GOV_ONDEMAND
config CPU_FREQ_DEFAULT_GOV_CONSERVATIVE
bool "conservative"
depends on !(X86_INTEL_PSTATE && SMP)
select CPU_FREQ_GOV_CONSERVATIVE
select CPU_FREQ_GOV_PERFORMANCE
help

15
drivers/cpufreq/cpufreq.c
View File

@ -1910,6 +1910,18 @@ void cpufreq_resume(void)
}
}
/**
* cpufreq_driver_test_flags - Test cpufreq driver's flags against given ones.
* @flags: Flags to test against the current cpufreq driver's flags.
*
* Assumes that the driver is there, so callers must ensure that this is the
* case.
*/
bool cpufreq_driver_test_flags(u16 flags)
{
return !!(cpufreq_driver->flags & flags);
}
/**
* cpufreq_get_current_driver - return current driver's name
*
@ -2190,7 +2202,8 @@ int __cpufreq_driver_target(struct cpufreq_policy *policy,
* exactly same freq is called again and so we can save on few function
* calls.
*/
if (target_freq == policy->cur)
if (target_freq == policy->cur &&
!(cpufreq_driver->flags & CPUFREQ_NEED_UPDATE_LIMITS))
return 0;
/* Save last value to restore later on errors */

1
drivers/cpufreq/e_powersaver.c
View File

@ -223,7 +223,6 @@ static int eps_cpu_init(struct cpufreq_policy *policy)
case EPS_BRAND_C3:
pr_cont("C3\n");
return -ENODEV;
break;
}
/* Enable Enhanced PowerSaver */
rdmsrl(MSR_IA32_MISC_ENABLE, val);

13
drivers/cpufreq/intel_pstate.c
View File

@ -2568,14 +2568,12 @@ static int intel_cpufreq_update_pstate(struct cpudata *cpu, int target_pstate,
int old_pstate = cpu->pstate.current_pstate;
target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
if (target_pstate != old_pstate) {
if (hwp_active) {
intel_cpufreq_adjust_hwp(cpu, target_pstate, fast_switch);
cpu->pstate.current_pstate = target_pstate;
} else if (target_pstate != old_pstate) {
intel_cpufreq_adjust_perf_ctl(cpu, target_pstate, fast_switch);
cpu->pstate.current_pstate = target_pstate;
if (hwp_active)
intel_cpufreq_adjust_hwp(cpu, target_pstate,
fast_switch);
else
intel_cpufreq_adjust_perf_ctl(cpu, target_pstate,
fast_switch);
}
intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH :
@ -3032,6 +3030,7 @@ static int __init intel_pstate_init(void)
hwp_mode_bdw = id->driver_data;
intel_pstate.attr = hwp_cpufreq_attrs;
intel_cpufreq.attr = hwp_cpufreq_attrs;
intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS;
if (!default_driver)
default_driver = &intel_pstate;

1
drivers/cpufreq/longhaul.c
View File

@ -593,7 +593,6 @@ static void longhaul_setup_voltagescaling(void)
break;
default:
return;
break;
}
if (min_vid_speed >= highest_speed)
return;

2
drivers/cpufreq/speedstep-lib.c
View File

@ -240,7 +240,7 @@ unsigned int speedstep_get_frequency(enum speedstep_processor processor)
return pentium3_get_frequency(processor);
default:
return 0;
};
}
return 0;
}
EXPORT_SYMBOL_GPL(speedstep_get_frequency);

2
drivers/firmware/arm_scmi/base.c
View File

@ -197,6 +197,8 @@ static int scmi_base_implementation_list_get(const struct scmi_handle *handle,
protocols_imp[tot_num_ret + loop] = *(list + loop);
tot_num_ret += loop_num_ret;
scmi_reset_rx_to_maxsz(handle, t);
} while (loop_num_ret);
scmi_xfer_put(handle, t);

2
drivers/firmware/arm_scmi/clock.c
View File

@ -192,6 +192,8 @@ scmi_clock_describe_rates_get(const struct scmi_handle *handle, u32 clk_id,
}
tot_rate_cnt += num_returned;
scmi_reset_rx_to_maxsz(handle, t);
/*
* check for both returned and remaining to avoid infinite
* loop due to buggy firmware

2
drivers/firmware/arm_scmi/common.h
View File

@ -147,6 +147,8 @@ int scmi_do_xfer_with_response(const struct scmi_handle *h,
struct scmi_xfer *xfer);
int scmi_xfer_get_init(const struct scmi_handle *h, u8 msg_id, u8 prot_id,
size_t tx_size, size_t rx_size, struct scmi_xfer **p);
void scmi_reset_rx_to_maxsz(const struct scmi_handle *handle,
struct scmi_xfer *xfer);
int scmi_handle_put(const struct scmi_handle *handle);
struct scmi_handle *scmi_handle_get(struct device *dev);
void scmi_set_handle(struct scmi_device *scmi_dev);

8
drivers/firmware/arm_scmi/driver.c
View File

@ -402,6 +402,14 @@ int scmi_do_xfer(const struct scmi_handle *handle, struct scmi_xfer *xfer)
return ret;
}
void scmi_reset_rx_to_maxsz(const struct scmi_handle *handle,
struct scmi_xfer *xfer)
{
struct scmi_info *info = handle_to_scmi_info(handle);
xfer->rx.len = info->desc->max_msg_size;
}
#define SCMI_MAX_RESPONSE_TIMEOUT (2 * MSEC_PER_SEC)
/**

22
drivers/firmware/arm_scmi/notify.c
View File

@ -1403,15 +1403,21 @@ static void scmi_protocols_late_init(struct work_struct *work)
"finalized PENDING handler - key:%X\n",
hndl->key);
ret = scmi_event_handler_enable_events(hndl);
if (ret) {
dev_dbg(ni->handle->dev,
"purging INVALID handler - key:%X\n",
hndl->key);
scmi_put_active_handler(ni, hndl);
}
} else {
ret = scmi_valid_pending_handler(ni, hndl);
}
if (ret) {
dev_dbg(ni->handle->dev,
"purging PENDING handler - key:%X\n",
hndl->key);
/* this hndl can be only a pending one */
scmi_put_handler_unlocked(ni, hndl);
if (ret) {
dev_dbg(ni->handle->dev,
"purging PENDING handler - key:%X\n",
hndl->key);
/* this hndl can be only a pending one */
scmi_put_handler_unlocked(ni, hndl);
}
}
}
mutex_unlock(&ni->pending_mtx);
@ -1468,7 +1474,7 @@ int scmi_notification_init(struct scmi_handle *handle)
ni->gid = gid;
ni->handle = handle;
ni->notify_wq = alloc_workqueue("scmi_notify",
ni->notify_wq = alloc_workqueue(dev_name(handle->dev),
WQ_UNBOUND | WQ_FREEZABLE | WQ_SYSFS,
0);
if (!ni->notify_wq)

2
drivers/firmware/arm_scmi/perf.c
View File

@ -304,6 +304,8 @@ scmi_perf_describe_levels_get(const struct scmi_handle *handle, u32 domain,
}
tot_opp_cnt += num_returned;
scmi_reset_rx_to_maxsz(handle, t);
/*
* check for both returned and remaining to avoid infinite
* loop due to buggy firmware

4
drivers/firmware/arm_scmi/reset.c
View File

@ -36,9 +36,7 @@ struct scmi_msg_reset_domain_reset {
#define EXPLICIT_RESET_ASSERT BIT(1)
#define ASYNCHRONOUS_RESET BIT(2)
__le32 reset_state;
#define ARCH_RESET_TYPE BIT(31)
#define COLD_RESET_STATE BIT(0)
#define ARCH_COLD_RESET (ARCH_RESET_TYPE | COLD_RESET_STATE)
#define ARCH_COLD_RESET 0
};
struct scmi_msg_reset_notify {

2
drivers/firmware/arm_scmi/sensors.c
View File

@ -166,6 +166,8 @@ static int scmi_sensor_description_get(const struct scmi_handle *handle,
}
desc_index += num_returned;
scmi_reset_rx_to_maxsz(handle, t);
/*
* check for both returned and remaining to avoid infinite
* loop due to buggy firmware

2
drivers/firmware/arm_scmi/smc.c
View File

@ -149,6 +149,6 @@ static const struct scmi_transport_ops scmi_smc_ops = {
const struct scmi_desc scmi_smc_desc = {
.ops = &scmi_smc_ops,
.max_rx_timeout_ms = 30,
.max_msg = 1,
.max_msg = 20,
.max_msg_size = 128,
};

1
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
View File

@ -1066,6 +1066,7 @@ static const struct pci_device_id pciidlist[] = {
{0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
{0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
{0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
{0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
{0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
/* Navi14 */
{0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},

10
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
View File

@ -596,6 +596,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
struct ww_acquire_ctx ticket;
struct list_head list, duplicates;
uint64_t va_flags;
uint64_t vm_size;
int r = 0;
if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
@ -616,6 +617,15 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
args->va_address &= AMDGPU_GMC_HOLE_MASK;
vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
vm_size -= AMDGPU_VA_RESERVED_SIZE;
if (args->va_address + args->map_size > vm_size) {
dev_dbg(&dev->pdev->dev,
"va_address 0x%llx is in top reserved area 0x%llx\n",
args->va_address + args->map_size, vm_size);
return -EINVAL;
}
if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n",
args->flags);

4
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
View File

@ -112,8 +112,8 @@ struct amdgpu_bo_list_entry;
#define AMDGPU_MMHUB_0 1
#define AMDGPU_MMHUB_1 2
/* hardcode that limit for now */
#define AMDGPU_VA_RESERVED_SIZE (1ULL << 20)
/* Reserve 2MB at top/bottom of address space for kernel use */
#define AMDGPU_VA_RESERVED_SIZE (2ULL << 20)
/* max vmids dedicated for process */
#define AMDGPU_VM_MAX_RESERVED_VMID 1

14
drivers/gpu/drm/amd/amdgpu/nv.c
View File

@ -455,6 +455,14 @@ void nv_set_virt_ops(struct amdgpu_device *adev)
adev->virt.ops = &xgpu_nv_virt_ops;
}
static bool nv_is_blockchain_sku(struct pci_dev *pdev)
{
if (pdev->device == 0x731E &&
(pdev->revision == 0xC6 || pdev->revision == 0xC7))
return true;
return false;
}
int nv_set_ip_blocks(struct amdgpu_device *adev)
{
int r;
@ -483,7 +491,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev))
else if (amdgpu_device_has_dc_support(adev) &&
!nv_is_blockchain_sku(adev->pdev))
amdgpu_device_ip_block_add(adev, &dm_ip_block);
#endif
amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
@ -491,7 +500,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
!amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
if (!nv_is_blockchain_sku(adev->pdev))
amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
if (adev->enable_mes)
amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);

1
drivers/gpu/drm/amd/display/Kconfig
View File

@ -42,6 +42,7 @@ config DRM_AMD_DC_SI
config DEBUG_KERNEL_DC
bool "Enable kgdb break in DC"
depends on DRM_AMD_DC
depends on KGDB
help
Choose this option if you want to hit kdgb_break in assert.

4
drivers/gpu/drm/amd/display/dc/core/dc.c
View File

@ -1571,8 +1571,8 @@ static void init_state(struct dc *dc, struct dc_state *context)
struct dc_state *dc_create_state(struct dc *dc)
{
struct dc_state *context = kzalloc(sizeof(struct dc_state),
GFP_KERNEL);
struct dc_state *context = kvzalloc(sizeof(struct dc_state),
GFP_KERNEL);
if (!context)
return NULL;

3
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
View File

@ -1149,7 +1149,8 @@ static uint32_t dcn3_get_pix_clk_dividers(
static const struct clock_source_funcs dcn3_clk_src_funcs = {
.cs_power_down = dce110_clock_source_power_down,
.program_pix_clk = dcn3_program_pix_clk,
.get_pix_clk_dividers = dcn3_get_pix_clk_dividers
.get_pix_clk_dividers = dcn3_get_pix_clk_dividers,
.get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
};
#endif
/*****************************************/

12
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
View File

@ -2105,12 +2105,12 @@ static bool dcn30_internal_validate_bw(
if (split[i]) {
if (odm) {
if (split[i] == 4 && old_pipe->next_odm_pipe->next_odm_pipe)
if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe)
old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
else if (old_pipe->next_odm_pipe)
old_index = old_pipe->next_odm_pipe->pipe_idx;
} else {
if (split[i] == 4 && old_pipe->bottom_pipe->bottom_pipe &&
if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx;
else if (old_pipe->bottom_pipe &&
@ -2150,10 +2150,12 @@ static bool dcn30_internal_validate_bw(
goto validate_fail;
newly_split[pipe_4to1->pipe_idx] = true;
if (odm && old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe)
if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe
&& old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe)
old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
else if (!odm && old_pipe->bottom_pipe->bottom_pipe->bottom_pipe &&
old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
old_pipe->bottom_pipe->bottom_pipe->bottom_pipe &&
old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx;
else
old_index = -1;

12
drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c
View File

@ -117,6 +117,12 @@ static const struct ddc_registers ddc_data_regs_dcn[] = {
ddc_data_regs_dcn2(4),
ddc_data_regs_dcn2(5),
ddc_data_regs_dcn2(6),
{
DDC_GPIO_VGA_REG_LIST(DATA),
.ddc_setup = 0,
.phy_aux_cntl = 0,
.dc_gpio_aux_ctrl_5 = 0
}
};
static const struct ddc_registers ddc_clk_regs_dcn[] = {
@ -126,6 +132,12 @@ static const struct ddc_registers ddc_clk_regs_dcn[] = {
ddc_clk_regs_dcn2(4),
ddc_clk_regs_dcn2(5),
ddc_clk_regs_dcn2(6),
{
DDC_GPIO_VGA_REG_LIST(CLK),
.ddc_setup = 0,
.phy_aux_cntl = 0,
.dc_gpio_aux_ctrl_5 = 0
}
};
static const struct ddc_sh_mask ddc_shift[] = {

4
drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c
View File

@ -63,13 +63,13 @@ enum gpio_result dal_gpio_open_ex(
enum gpio_mode mode)
{
if (gpio->pin) {
ASSERT_CRITICAL(false);
BREAK_TO_DEBUGGER();
return GPIO_RESULT_ALREADY_OPENED;
}
// No action if allocation failed during gpio construct
if (!gpio->hw_container.ddc) {
ASSERT_CRITICAL(false);
BREAK_TO_DEBUGGER();
return GPIO_RESULT_NON_SPECIFIC_ERROR;
}
gpio->mode = mode;

33
drivers/gpu/drm/amd/display/dc/os_types.h
View File

@ -94,36 +94,27 @@
* general debug capabilities
*
*/
#if defined(CONFIG_HAVE_KGDB) || defined(CONFIG_KGDB)
#define ASSERT_CRITICAL(expr) do { \
if (WARN_ON(!(expr))) { \
kgdb_breakpoint(); \
} \
} while (0)
#ifdef CONFIG_DEBUG_KERNEL_DC
#define dc_breakpoint() kgdb_breakpoint()
#else
#define ASSERT_CRITICAL(expr) do { \
if (WARN_ON(!(expr))) { \
; \
} \
} while (0)
#define dc_breakpoint() do {} while (0)
#endif
#if defined(CONFIG_DEBUG_KERNEL_DC)
#define ASSERT(expr) ASSERT_CRITICAL(expr)
#define ASSERT_CRITICAL(expr) do { \
if (WARN_ON(!(expr))) \
dc_breakpoint(); \
} while (0)
#else
#define ASSERT(expr) WARN_ON_ONCE(!(expr))
#endif
#define ASSERT(expr) do { \
if (WARN_ON_ONCE(!(expr))) \
dc_breakpoint(); \
} while (0)
#if defined(CONFIG_DEBUG_KERNEL_DC) && (defined(CONFIG_HAVE_KGDB) || defined(CONFIG_KGDB))
#define BREAK_TO_DEBUGGER() \
do { \
DRM_DEBUG_DRIVER("%s():%d\n", __func__, __LINE__); \
kgdb_breakpoint(); \
dc_breakpoint(); \
} while (0)
#else
#define BREAK_TO_DEBUGGER() DRM_DEBUG_DRIVER("%s():%d\n", __func__, __LINE__)
#endif
#define DC_ERR(...) do { \
dm_error(__VA_ARGS__); \

36
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
View File

@ -1361,14 +1361,9 @@ static int navi10_get_fan_speed_rpm(struct smu_context *smu,
if (!speed)
return -EINVAL;
switch (smu_v11_0_get_fan_control_mode(smu)) {
case AMD_FAN_CTRL_AUTO:
return navi10_get_smu_metrics_data(smu,
METRICS_CURR_FANSPEED,
speed);
default:
return smu_v11_0_get_fan_speed_rpm(smu, speed);
}
return navi10_get_smu_metrics_data(smu,
METRICS_CURR_FANSPEED,
speed);
}
static int navi10_get_fan_parameters(struct smu_context *smu)
@ -2534,29 +2529,6 @@ static const struct i2c_algorithm navi10_i2c_algo = {
.functionality = navi10_i2c_func,
};
static int navi10_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
{
struct amdgpu_device *adev = to_amdgpu_device(control);
int res;
control->owner = THIS_MODULE;
control->class = I2C_CLASS_SPD;
control->dev.parent = &adev->pdev->dev;
control->algo = &navi10_i2c_algo;
snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
res = i2c_add_adapter(control);
if (res)
DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
return res;
}
static void navi10_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
{
i2c_del_adapter(control);
}
static ssize_t navi10_get_gpu_metrics(struct smu_context *smu,
void **table)
{
@ -2687,8 +2659,6 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.set_default_dpm_table = navi10_set_default_dpm_table,
.dpm_set_vcn_enable = navi10_dpm_set_vcn_enable,
.dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
.i2c_init = navi10_i2c_control_init,
.i2c_fini = navi10_i2c_control_fini,
.print_clk_levels = navi10_print_clk_levels,
.force_clk_levels = navi10_force_clk_levels,
.populate_umd_state_clk = navi10_populate_umd_state_clk,

11
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
View File

@ -1177,14 +1177,9 @@ static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
if (!speed)
return -EINVAL;
switch (smu_v11_0_get_fan_control_mode(smu)) {
case AMD_FAN_CTRL_AUTO:
return sienna_cichlid_get_smu_metrics_data(smu,
METRICS_CURR_FANSPEED,
speed);
default:
return smu_v11_0_get_fan_speed_rpm(smu, speed);
}
return sienna_cichlid_get_smu_metrics_data(smu,
METRICS_CURR_FANSPEED,
speed);
}
static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)

12
drivers/gpu/drm/drm_dp_helper.c
View File

@ -374,6 +374,10 @@ static bool is_edid_digital_input_dp(const struct edid *edid)
* drm_dp_downstream_is_type() - is the downstream facing port of certain type?
* @dpcd: DisplayPort configuration data
* @port_cap: port capabilities
* @type: port type to be checked. Can be:
* %DP_DS_PORT_TYPE_DP, %DP_DS_PORT_TYPE_VGA, %DP_DS_PORT_TYPE_DVI,
* %DP_DS_PORT_TYPE_HDMI, %DP_DS_PORT_TYPE_NON_EDID,
* %DP_DS_PORT_TYPE_DP_DUALMODE or %DP_DS_PORT_TYPE_WIRELESS.
*
* Caveat: Only works with DPCD 1.1+ port caps.
*
@ -870,6 +874,7 @@ EXPORT_SYMBOL(drm_dp_downstream_444_to_420_conversion);
/**
* drm_dp_downstream_mode() - return a mode for downstream facing port
* @dev: DRM device
* @dpcd: DisplayPort configuration data
* @port_cap: port capabilities
*
@ -1028,7 +1033,8 @@ EXPORT_SYMBOL(drm_dp_downstream_debug);
/**
* drm_dp_subconnector_type() - get DP branch device type
*
* @dpcd: DisplayPort configuration data
* @port_cap: port capabilities
*/
enum drm_mode_subconnector
drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
@ -1079,6 +1085,10 @@ EXPORT_SYMBOL(drm_dp_subconnector_type);
/**
* drm_mode_set_dp_subconnector_property - set subconnector for DP connector
* @connector: connector to set property on
* @status: connector status
* @dpcd: DisplayPort configuration data
* @port_cap: port capabilities
*
* Called by a driver on every detect event.
*/

2
drivers/gpu/drm/drm_edid.c
View File

@ -3741,7 +3741,7 @@ drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
/**
* drm_display_mode_from_cea_vic() - return a mode for CEA VIC
* @dev: DRM device
* @vic: CEA VIC of the mode
* @video_code: CEA VIC of the mode
*
* Creates a new mode matching the specified CEA VIC.
*

4
drivers/gpu/drm/drm_gem.c
View File

@ -1085,6 +1085,8 @@ int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size,
*/
drm_gem_object_get(obj);
vma->vm_private_data = obj;
if (obj->funcs && obj->funcs->mmap) {
ret = obj->funcs->mmap(obj, vma);
if (ret) {
@ -1107,8 +1109,6 @@ int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size,
vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot);
}
vma->vm_private_data = obj;
return 0;
}
EXPORT_SYMBOL(drm_gem_mmap_obj);

7
drivers/gpu/drm/drm_gem_shmem_helper.c
View File

@ -593,8 +593,13 @@ int drm_gem_shmem_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
/* Remove the fake offset */
vma->vm_pgoff -= drm_vma_node_start(&obj->vma_node);
if (obj->import_attach)
if (obj->import_attach) {
/* Drop the reference drm_gem_mmap_obj() acquired.*/
drm_gem_object_put(obj);
vma->vm_private_data = NULL;
return dma_buf_mmap(obj->dma_buf, vma, 0);
}
shmem = to_drm_gem_shmem_obj(obj);

1
drivers/gpu/drm/drm_prime.c
View File

@ -817,6 +817,7 @@ static const struct dma_buf_ops drm_gem_prime_dmabuf_ops = {
/**
* drm_prime_pages_to_sg - converts a page array into an sg list
* @dev: DRM device
* @pages: pointer to the array of page pointers to convert
* @nr_pages: length of the page vector
*

4
drivers/gpu/drm/i915/display/intel_display.c
View File

@ -10636,6 +10636,10 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
val & PLANE_CTL_FLIP_HORIZONTAL)
plane_config->rotation |= DRM_MODE_REFLECT_X;
/* 90/270 degree rotation would require extra work */
if (drm_rotation_90_or_270(plane_config->rotation))
goto error;
base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000;
plane_config->base = base;

1
drivers/gpu/drm/i915/i915_pci.c
View File

@ -389,6 +389,7 @@ static const struct intel_device_info ilk_m_info = {
GEN5_FEATURES,
PLATFORM(INTEL_IRONLAKE),
.is_mobile = 1,
.has_rps = true,
.display.has_fbc = 1,
};

2
drivers/gpu/drm/i915/intel_memory_region.c
View File

@ -87,7 +87,7 @@ __intel_memory_region_get_pages_buddy(struct intel_memory_region *mem,
min_order = ilog2(size) - ilog2(mem->mm.chunk_size);
}
if (size > BIT(mem->mm.max_order) * mem->mm.chunk_size)
if (size > mem->mm.size)
return -E2BIG;
n_pages = size >> ilog2(mem->mm.chunk_size);

77
drivers/gpu/drm/i915/selftests/intel_memory_region.c
View File

@ -261,6 +261,82 @@ static int igt_mock_contiguous(void *arg)
return err;
}
static int igt_mock_splintered_region(void *arg)
{
struct intel_memory_region *mem = arg;
struct drm_i915_private *i915 = mem->i915;
struct drm_i915_gem_object *obj;
unsigned int expected_order;
LIST_HEAD(objects);
u64 size;
int err = 0;
/*
* Sanity check we can still allocate everything even if the
* mm.max_order != mm.size. i.e our starting address space size is not a
* power-of-two.
*/
size = (SZ_4G - 1) & PAGE_MASK;
mem = mock_region_create(i915, 0, size, PAGE_SIZE, 0);
if (IS_ERR(mem))
return PTR_ERR(mem);
if (mem->mm.size != size) {
pr_err("%s size mismatch(%llu != %llu)\n",
__func__, mem->mm.size, size);
err = -EINVAL;
goto out_put;
}
expected_order = get_order(rounddown_pow_of_two(size));
if (mem->mm.max_order != expected_order) {
pr_err("%s order mismatch(%u != %u)\n",
__func__, mem->mm.max_order, expected_order);
err = -EINVAL;
goto out_put;
}
obj = igt_object_create(mem, &objects, size, 0);
if (IS_ERR(obj)) {
err = PTR_ERR(obj);
goto out_close;
}
close_objects(mem, &objects);
/*
* While we should be able allocate everything without any flag
* restrictions, if we consider I915_BO_ALLOC_CONTIGUOUS then we are
* actually limited to the largest power-of-two for the region size i.e
* max_order, due to the inner workings of the buddy allocator. So make
* sure that does indeed hold true.
*/
obj = igt_object_create(mem, &objects, size, I915_BO_ALLOC_CONTIGUOUS);
if (!IS_ERR(obj)) {
pr_err("%s too large contiguous allocation was not rejected\n",
__func__);
err = -EINVAL;
goto out_close;
}
obj = igt_object_create(mem, &objects, rounddown_pow_of_two(size),
I915_BO_ALLOC_CONTIGUOUS);
if (IS_ERR(obj)) {
pr_err("%s largest possible contiguous allocation failed\n",
__func__);
err = PTR_ERR(obj);
goto out_close;
}
out_close:
close_objects(mem, &objects);
out_put:
intel_memory_region_put(mem);
return err;
}
static int igt_gpu_write_dw(struct intel_context *ce,
struct i915_vma *vma,
u32 dword,
@ -771,6 +847,7 @@ int intel_memory_region_mock_selftests(void)
static const struct i915_subtest tests[] = {
SUBTEST(igt_mock_fill),
SUBTEST(igt_mock_contiguous),
SUBTEST(igt_mock_splintered_region),
};
struct intel_memory_region *mem;
struct drm_i915_private *i915;

2
drivers/gpu/drm/i915/selftests/mock_region.c
View File

@ -24,7 +24,7 @@ mock_object_create(struct intel_memory_region *mem,
struct drm_i915_private *i915 = mem->i915;
struct drm_i915_gem_object *obj;
if (size > BIT(mem->mm.max_order) * mem->mm.chunk_size)
if (size > mem->mm.size)
return ERR_PTR(-E2BIG);
obj = i915_gem_object_alloc();

2
drivers/gpu/drm/nouveau/dispnv50/core.h
View File

@ -44,6 +44,7 @@ int core507d_new_(const struct nv50_core_func *, struct nouveau_drm *, s32,
struct nv50_core **);
int core507d_init(struct nv50_core *);
void core507d_ntfy_init(struct nouveau_bo *, u32);
int core507d_read_caps(struct nv50_disp *disp);
int core507d_caps_init(struct nouveau_drm *, struct nv50_disp *);
int core507d_ntfy_wait_done(struct nouveau_bo *, u32, struct nvif_device *);
int core507d_update(struct nv50_core *, u32 *, bool);
@ -55,6 +56,7 @@ extern const struct nv50_outp_func pior507d;
int core827d_new(struct nouveau_drm *, s32, struct nv50_core **);
int core907d_new(struct nouveau_drm *, s32, struct nv50_core **);
int core907d_caps_init(struct nouveau_drm *drm, struct nv50_disp *disp);
extern const struct nv50_outp_func dac907d;
extern const struct nv50_outp_func sor907d;

41
drivers/gpu/drm/nouveau/dispnv50/core507d.c
View File

@ -78,18 +78,55 @@ core507d_ntfy_init(struct nouveau_bo *bo, u32 offset)
}
int
core507d_caps_init(struct nouveau_drm *drm, struct nv50_disp *disp)
core507d_read_caps(struct nv50_disp *disp)
{
struct nvif_push *push = disp->core->chan.push;
int ret;
if ((ret = PUSH_WAIT(push, 2)))
ret = PUSH_WAIT(push, 6);
if (ret)
return ret;
PUSH_MTHD(push, NV507D, SET_NOTIFIER_CONTROL,
NVDEF(NV507D, SET_NOTIFIER_CONTROL, MODE, WRITE) |
NVVAL(NV507D, SET_NOTIFIER_CONTROL, OFFSET, NV50_DISP_CORE_NTFY >> 2) |
NVDEF(NV507D, SET_NOTIFIER_CONTROL, NOTIFY, ENABLE));
PUSH_MTHD(push, NV507D, GET_CAPABILITIES, 0x00000000);
PUSH_MTHD(push, NV507D, SET_NOTIFIER_CONTROL,
NVDEF(NV507D, SET_NOTIFIER_CONTROL, NOTIFY, DISABLE));
return PUSH_KICK(push);
}
int
core507d_caps_init(struct nouveau_drm *drm, struct nv50_disp *disp)
{
struct nv50_core *core = disp->core;
struct nouveau_bo *bo = disp->sync;
s64 time;
int ret;
NVBO_WR32(bo, NV50_DISP_CORE_NTFY, NV_DISP_CORE_NOTIFIER_1, CAPABILITIES_1,
NVDEF(NV_DISP_CORE_NOTIFIER_1, CAPABILITIES_1, DONE, FALSE));
ret = core507d_read_caps(disp);
if (ret < 0)
return ret;
time = nvif_msec(core->chan.base.device, 2000ULL,
if (NVBO_TD32(bo, NV50_DISP_CORE_NTFY,
NV_DISP_CORE_NOTIFIER_1, CAPABILITIES_1, DONE, ==, TRUE))
break;
usleep_range(1, 2);
);
if (time < 0)
NV_ERROR(drm, "core caps notifier timeout\n");
return 0;
}
int
core507d_init(struct nv50_core *core)
{

36
drivers/gpu/drm/nouveau/dispnv50/core907d.c
View File

@ -22,11 +22,45 @@
#include "core.h"
#include "head.h"
#include <nvif/push507c.h>
#include <nvif/timer.h>
#include <nvhw/class/cl907d.h>
#include "nouveau_bo.h"
int
core907d_caps_init(struct nouveau_drm *drm, struct nv50_disp *disp)
{
struct nv50_core *core = disp->core;
struct nouveau_bo *bo = disp->sync;
s64 time;
int ret;
NVBO_WR32(bo, NV50_DISP_CORE_NTFY, NV907D_CORE_NOTIFIER_3, CAPABILITIES_4,
NVDEF(NV907D_CORE_NOTIFIER_3, CAPABILITIES_4, DONE, FALSE));
ret = core507d_read_caps(disp);
if (ret < 0)
return ret;
time = nvif_msec(core->chan.base.device, 2000ULL,
if (NVBO_TD32(bo, NV50_DISP_CORE_NTFY,
NV907D_CORE_NOTIFIER_3, CAPABILITIES_4, DONE, ==, TRUE))
break;
usleep_range(1, 2);
);
if (time < 0)
NV_ERROR(drm, "core caps notifier timeout\n");
return 0;
}
static const struct nv50_core_func
core907d = {
.init = core507d_init,
.ntfy_init = core507d_ntfy_init,
.caps_init = core507d_caps_init,
.caps_init = core907d_caps_init,
.ntfy_wait_done = core507d_ntfy_wait_done,
.update = core507d_update,
.head = &head907d,

2
drivers/gpu/drm/nouveau/dispnv50/core917d.c
View File

@ -26,7 +26,7 @@ static const struct nv50_core_func
core917d = {
.init = core507d_init,
.ntfy_init = core507d_ntfy_init,
.caps_init = core507d_caps_init,
.caps_init = core907d_caps_init,
.ntfy_wait_done = core507d_ntfy_wait_done,
.update = core507d_update,
.head = &head917d,

5
drivers/gpu/drm/nouveau/include/nvhw/class/cl507d.h
View File

@ -32,7 +32,10 @@
#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE_TRUE 0x00000001
#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_R0 15:1
#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_TIMESTAMP 29:16
#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1 0x00000001
#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE 0:0
#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_FALSE 0x00000000
#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_TRUE 0x00000001
// class methods
#define NV507D_UPDATE (0x00000080)

4
drivers/gpu/drm/nouveau/include/nvhw/class/cl907d.h
View File

@ -24,6 +24,10 @@
#ifndef _cl907d_h_
#define _cl907d_h_
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0
#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000

36
drivers/gpu/drm/nouveau/nouveau_connector.c
View File

@ -1023,29 +1023,6 @@ get_tmds_link_bandwidth(struct drm_connector *connector)
return 112000 * duallink_scale;
}
enum drm_mode_status
nouveau_conn_mode_clock_valid(const struct drm_display_mode *mode,
const unsigned min_clock,
const unsigned max_clock,
unsigned int *clock_out)
{
unsigned int clock = mode->clock;
if ((mode->flags & DRM_MODE_FLAG_3D_MASK) ==
DRM_MODE_FLAG_3D_FRAME_PACKING)
clock *= 2;
if (clock < min_clock)
return MODE_CLOCK_LOW;
if (clock > max_clock)
return MODE_CLOCK_HIGH;
if (clock_out)
*clock_out = clock;
return MODE_OK;
}
static enum drm_mode_status
nouveau_connector_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
@ -1053,7 +1030,7 @@ nouveau_connector_mode_valid(struct drm_connector *connector,
struct nouveau_connector *nv_connector = nouveau_connector(connector);
struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder;
struct drm_encoder *encoder = to_drm_encoder(nv_encoder);
unsigned min_clock = 25000, max_clock = min_clock;
unsigned int min_clock = 25000, max_clock = min_clock, clock = mode->clock;
switch (nv_encoder->dcb->type) {
case DCB_OUTPUT_LVDS:
@ -1082,8 +1059,15 @@ nouveau_connector_mode_valid(struct drm_connector *connector,
return MODE_BAD;
}
return nouveau_conn_mode_clock_valid(mode, min_clock, max_clock,
NULL);
if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
clock *= 2;
if (clock < min_clock)
return MODE_CLOCK_LOW;
if (clock > max_clock)
return MODE_CLOCK_HIGH;
return MODE_OK;
}
static struct drm_encoder *

31
drivers/gpu/drm/nouveau/nouveau_dp.c
View File

@ -231,23 +231,30 @@ nv50_dp_mode_valid(struct drm_connector *connector,
const struct drm_display_mode *mode,
unsigned *out_clock)
{
const unsigned min_clock = 25000;
unsigned max_clock, ds_clock, clock;
enum drm_mode_status ret;
const unsigned int min_clock = 25000;
unsigned int max_rate, mode_rate, ds_max_dotclock, clock = mode->clock;
const u8 bpp = connector->display_info.bpc * 3;
if (mode->flags & DRM_MODE_FLAG_INTERLACE && !outp->caps.dp_interlace)
return MODE_NO_INTERLACE;
max_clock = outp->dp.link_nr * outp->dp.link_bw;
ds_clock = drm_dp_downstream_max_dotclock(outp->dp.dpcd,
outp->dp.downstream_ports);
if (ds_clock)
max_clock = min(max_clock, ds_clock);
if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
clock *= 2;
max_rate = outp->dp.link_nr * outp->dp.link_bw;
mode_rate = DIV_ROUND_UP(clock * bpp, 8);
if (mode_rate > max_rate)
return MODE_CLOCK_HIGH;
ds_max_dotclock = drm_dp_downstream_max_dotclock(outp->dp.dpcd, outp->dp.downstream_ports);
if (ds_max_dotclock && clock > ds_max_dotclock)
return MODE_CLOCK_HIGH;
if (clock < min_clock)
return MODE_CLOCK_LOW;
clock = mode->clock * (connector->display_info.bpc * 3) / 10;
ret = nouveau_conn_mode_clock_valid(mode, min_clock, max_clock,
&clock);
if (out_clock)
*out_clock = clock;
return ret;
return MODE_OK;
}

3
drivers/gpu/drm/nouveau/nouveau_gem.c
View File

@ -190,7 +190,8 @@ nouveau_gem_new(struct nouveau_cli *cli, u64 size, int align, uint32_t domain,
* to the caller, instead of a normal nouveau_bo ttm reference. */
ret = drm_gem_object_init(drm->dev, &nvbo->bo.base, size);
if (ret) {
nouveau_bo_ref(NULL, &nvbo);
drm_gem_object_release(&nvbo->bo.base);
kfree(nvbo);
return ret;
}

14
drivers/gpu/drm/nouveau/nouveau_svm.c
View File

@ -105,11 +105,11 @@ nouveau_svmm_bind(struct drm_device *dev, void *data,
struct nouveau_cli *cli = nouveau_cli(file_priv);
struct drm_nouveau_svm_bind *args = data;
unsigned target, cmd, priority;
unsigned long addr, end, size;
unsigned long addr, end;
struct mm_struct *mm;
args->va_start &= PAGE_MASK;
args->va_end &= PAGE_MASK;
args->va_end = ALIGN(args->va_end, PAGE_SIZE);
/* Sanity check arguments */
if (args->reserved0 || args->reserved1)
@ -118,8 +118,6 @@ nouveau_svmm_bind(struct drm_device *dev, void *data,
return -EINVAL;
if (args->va_start >= args->va_end)
return -EINVAL;
if (!args->npages)
return -EINVAL;
cmd = args->header >> NOUVEAU_SVM_BIND_COMMAND_SHIFT;
cmd &= NOUVEAU_SVM_BIND_COMMAND_MASK;
@ -151,12 +149,6 @@ nouveau_svmm_bind(struct drm_device *dev, void *data,
if (args->stride)
return -EINVAL;
size = ((unsigned long)args->npages) << PAGE_SHIFT;
if ((args->va_start + size) <= args->va_start)
return -EINVAL;
if ((args->va_start + size) > args->va_end)
return -EINVAL;
/*
* Ok we are ask to do something sane, for now we only support migrate
* commands but we will add things like memory policy (what to do on
@ -171,7 +163,7 @@ nouveau_svmm_bind(struct drm_device *dev, void *data,
return -EINVAL;
}
for (addr = args->va_start, end = args->va_start + size; addr < end;) {
for (addr = args->va_start, end = args->va_end; addr < end;) {
struct vm_area_struct *vma;
unsigned long next;

39
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@ -2924,17 +2924,34 @@ nvkm_device_del(struct nvkm_device **pdevice)
}
}
/* returns true if the GPU is in the CPU native byte order */
static inline bool
nvkm_device_endianness(struct nvkm_device *device)
{
u32 boot1 = nvkm_rd32(device, 0x000004) & 0x01000001;
#ifdef __BIG_ENDIAN
if (!boot1)
return false;
const bool big_endian = true;
#else
if (boot1)
return false;
const bool big_endian = false;
#endif
/* Read NV_PMC_BOOT_1, and assume non-functional endian switch if it
* doesn't contain the expected values.
*/
u32 pmc_boot_1 = nvkm_rd32(device, 0x000004);
if (pmc_boot_1 && pmc_boot_1 != 0x01000001)
return !big_endian; /* Assume GPU is LE in this case. */
/* 0 means LE and 0x01000001 means BE GPU. Condition is true when
* GPU/CPU endianness don't match.
*/
if (big_endian == !pmc_boot_1) {
nvkm_wr32(device, 0x000004, 0x01000001);
nvkm_rd32(device, 0x000000);
if (nvkm_rd32(device, 0x000004) != (big_endian ? 0x01000001 : 0x00000000))
return !big_endian; /* Assume GPU is LE on any unexpected read-back. */
}
/* CPU/GPU endianness should (hopefully) match. */
return true;
}
@ -2987,14 +3004,10 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
if (detect) {
/* switch mmio to cpu's native endianness */
if (!nvkm_device_endianness(device)) {
nvkm_wr32(device, 0x000004, 0x01000001);
nvkm_rd32(device, 0x000000);
if (!nvkm_device_endianness(device)) {
nvdev_error(device,
"GPU not supported on big-endian\n");
ret = -ENOSYS;
goto done;
}
nvdev_error(device,
"Couldn't switch GPU to CPUs endianess\n");
ret = -ENOSYS;
goto done;
}
boot0 = nvkm_rd32(device, 0x000000);

25
drivers/gpu/drm/panel/panel-mantix-mlaf057we51.c
View File

@ -26,7 +26,9 @@
struct mantix {
struct device *dev;
struct drm_panel panel;
struct gpio_desc *reset_gpio;
struct gpio_desc *tp_rstn_gpio;
struct regulator *avdd;
struct regulator *avee;
@ -124,6 +126,10 @@ static int mantix_unprepare(struct drm_panel *panel)
{
struct mantix *ctx = panel_to_mantix(panel);
gpiod_set_value_cansleep(ctx->tp_rstn_gpio, 1);
usleep_range(5000, 6000);
gpiod_set_value_cansleep(ctx->reset_gpio, 1);
regulator_disable(ctx->avee);
regulator_disable(ctx->avdd);
/* T11 */
@ -165,13 +171,10 @@ static int mantix_prepare(struct drm_panel *panel)
return ret;
}
/* T3+T5 */
usleep_range(10000, 12000);
gpiod_set_value_cansleep(ctx->reset_gpio, 1);
usleep_range(5150, 7000);
/* T3 + T4 + time for voltage to become stable: */
usleep_range(6000, 7000);
gpiod_set_value_cansleep(ctx->reset_gpio, 0);
gpiod_set_value_cansleep(ctx->tp_rstn_gpio, 0);
/* T6 */
msleep(50);
@ -204,7 +207,7 @@ static int mantix_get_modes(struct drm_panel *panel,
if (!mode) {
dev_err(ctx->dev, "Failed to add mode %ux%u@%u\n",
default_mode.hdisplay, default_mode.vdisplay,
drm_mode_vrefresh(mode));
drm_mode_vrefresh(&default_mode));
return -ENOMEM;
}
@ -236,12 +239,18 @@ static int mantix_probe(struct mipi_dsi_device *dsi)
if (!ctx)
return -ENOMEM;
ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
if (IS_ERR(ctx->reset_gpio)) {
dev_err(dev, "cannot get reset gpio\n");
return PTR_ERR(ctx->reset_gpio);
}
ctx->tp_rstn_gpio = devm_gpiod_get(dev, "mantix,tp-rstn", GPIOD_OUT_HIGH);
if (IS_ERR(ctx->tp_rstn_gpio)) {
dev_err(dev, "cannot get tp-rstn gpio\n");
return PTR_ERR(ctx->tp_rstn_gpio);
}
mipi_dsi_set_drvdata(dsi, ctx);
ctx->dev = dev;

36
drivers/gpu/drm/sun4i/sun4i_frontend.c
View File

@ -407,6 +407,7 @@ int sun4i_frontend_update_formats(struct sun4i_frontend *frontend,
struct drm_framebuffer *fb = state->fb;
const struct drm_format_info *format = fb->format;
uint64_t modifier = fb->modifier;
unsigned int ch1_phase_idx;
u32 out_fmt_val;
u32 in_fmt_val, in_mod_val, in_ps_val;
unsigned int i;
@ -442,18 +443,19 @@ int sun4i_frontend_update_formats(struct sun4i_frontend *frontend,
* I have no idea what this does exactly, but it seems to be
* related to the scaler FIR filter phase parameters.
*/
ch1_phase_idx = (format->num_planes > 1) ? 1 : 0;
regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_HORZPHASE_REG,
frontend->data->ch_phase[0].horzphase);
frontend->data->ch_phase[0]);
regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_HORZPHASE_REG,
frontend->data->ch_phase[1].horzphase);
frontend->data->ch_phase[ch1_phase_idx]);
regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTPHASE0_REG,
frontend->data->ch_phase[0].vertphase[0]);
frontend->data->ch_phase[0]);
regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTPHASE0_REG,
frontend->data->ch_phase[1].vertphase[0]);
frontend->data->ch_phase[ch1_phase_idx]);
regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTPHASE1_REG,
frontend->data->ch_phase[0].vertphase[1]);
frontend->data->ch_phase[0]);
regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTPHASE1_REG,
frontend->data->ch_phase[1].vertphase[1]);
frontend->data->ch_phase[ch1_phase_idx]);
/*
* Checking the input format is sufficient since we currently only
@ -687,30 +689,12 @@ static const struct dev_pm_ops sun4i_frontend_pm_ops = {
};
static const struct sun4i_frontend_data sun4i_a10_frontend = {
.ch_phase = {
{
.horzphase = 0,
.vertphase = { 0, 0 },
},
{
.horzphase = 0xfc000,
.vertphase = { 0xfc000, 0xfc000 },
},
},
.ch_phase = { 0x000, 0xfc000 },
.has_coef_rdy = true,
};
static const struct sun4i_frontend_data sun8i_a33_frontend = {
.ch_phase = {
{
.horzphase = 0x400,
.vertphase = { 0x400, 0x400 },
},
{
.horzphase = 0x400,
.vertphase = { 0x400, 0x400 },
},
},
.ch_phase = { 0x400, 0xfc400 },
.has_coef_access_ctrl = true,
};

6
drivers/gpu/drm/sun4i/sun4i_frontend.h
View File

@ -115,11 +115,7 @@ struct reset_control;
struct sun4i_frontend_data {
bool has_coef_access_ctrl;
bool has_coef_rdy;
struct {
u32 horzphase;
u32 vertphase[2];
} ch_phase[2];
u32 ch_phase[2];
};
struct sun4i_frontend {

1
drivers/gpu/drm/v3d/v3d_gem.c
View File

@ -568,7 +568,6 @@ v3d_submit_cl_ioctl(struct drm_device *dev, void *data,
ret = v3d_job_init(v3d, file_priv, &bin->base,
v3d_job_free, args->in_sync_bcl);
if (ret) {
kfree(bin);
v3d_job_put(&render->base);
kfree(bin);
return ret;

1
drivers/gpu/drm/vc4/vc4_drv.c
View File

@ -314,6 +314,7 @@ static int vc4_drm_bind(struct device *dev)
component_unbind_all(dev, drm);
gem_destroy:
vc4_gem_destroy(drm);
drm_mode_config_cleanup(drm);
vc4_bo_cache_destroy(drm);
dev_put:
drm_dev_put(drm);

12
drivers/gpu/drm/vc4/vc4_drv.h
View File

@ -287,7 +287,7 @@ struct vc4_bo {
static inline struct vc4_bo *
to_vc4_bo(struct drm_gem_object *bo)
{
return (struct vc4_bo *)bo;
return container_of(to_drm_gem_cma_obj(bo), struct vc4_bo, base);
}
struct vc4_fence {
@ -300,7 +300,7 @@ struct vc4_fence {
static inline struct vc4_fence *
to_vc4_fence(struct dma_fence *fence)
{
return (struct vc4_fence *)fence;
return container_of(fence, struct vc4_fence, base);
}
struct vc4_seqno_cb {
@ -347,7 +347,7 @@ struct vc4_plane {
static inline struct vc4_plane *
to_vc4_plane(struct drm_plane *plane)
{
return (struct vc4_plane *)plane;
return container_of(plane, struct vc4_plane, base);
}
enum vc4_scaling_mode {
@ -423,7 +423,7 @@ struct vc4_plane_state {
static inline struct vc4_plane_state *
to_vc4_plane_state(struct drm_plane_state *state)
{
return (struct vc4_plane_state *)state;
return container_of(state, struct vc4_plane_state, base);
}
enum vc4_encoder_type {
@ -499,7 +499,7 @@ struct vc4_crtc {
static inline struct vc4_crtc *
to_vc4_crtc(struct drm_crtc *crtc)
{
return (struct vc4_crtc *)crtc;
return container_of(crtc, struct vc4_crtc, base);
}
static inline const struct vc4_crtc_data *
@ -537,7 +537,7 @@ struct vc4_crtc_state {
static inline struct vc4_crtc_state *
to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
{
return (struct vc4_crtc_state *)crtc_state;
return container_of(crtc_state, struct vc4_crtc_state, base);
}
#define V3D_READ(offset) readl(vc4->v3d->regs + offset)

6
drivers/gpu/drm/vc4/vc4_hdmi.c
View File

@ -922,6 +922,7 @@ static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
struct device *dev = &vc4_hdmi->pdev->dev;
u32 audio_packet_config, channel_mask;
u32 channel_map;
@ -981,6 +982,8 @@ static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream,
HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
vc4_hdmi_set_n_cts(vc4_hdmi);
vc4_hdmi_set_audio_infoframe(encoder);
return 0;
}
@ -988,11 +991,9 @@ static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
vc4_hdmi_set_audio_infoframe(encoder);
vc4_hdmi->audio.streaming = true;
if (vc4_hdmi->variant->phy_rng_enable)
@ -1076,6 +1077,7 @@ static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = {
};
static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = {
.name = "vc4-hdmi-codec-dai-component",
.controls = vc4_hdmi_audio_controls,
.num_controls = ARRAY_SIZE(vc4_hdmi_audio_controls),
.dapm_widgets = vc4_hdmi_audio_widgets,

2
drivers/idle/intel_idle.c
View File

@ -1239,7 +1239,7 @@ static void __init intel_idle_init_cstates_acpi(struct cpuidle_driver *drv)
struct acpi_processor_cx *cx;
struct cpuidle_state *state;
if (intel_idle_max_cstate_reached(cstate))
if (intel_idle_max_cstate_reached(cstate - 1))
break;
cx = &acpi_state_table.states[cstate];

48
drivers/infiniband/core/cma.c
View File

@ -405,10 +405,10 @@ static int cma_comp_exch(struct rdma_id_private *id_priv,
/*
* The FSM uses a funny double locking where state is protected by both
* the handler_mutex and the spinlock. State is not allowed to change
* away from a handler_mutex protected value without also holding
* to/from a handler_mutex protected value without also holding
* handler_mutex.
*/
if (comp == RDMA_CM_CONNECT)
if (comp == RDMA_CM_CONNECT || exch == RDMA_CM_CONNECT)
lockdep_assert_held(&id_priv->handler_mutex);
spin_lock_irqsave(&id_priv->lock, flags);
@ -4038,17 +4038,23 @@ static int cma_connect_iw(struct rdma_id_private *id_priv,
return ret;
}
int rdma_connect(struct rdma_cm_id *id, struct rdma_conn_param *conn_param)
/**
* rdma_connect_locked - Initiate an active connection request.
* @id: Connection identifier to connect.
* @conn_param: Connection information used for connected QPs.
*
* Same as rdma_connect() but can only be called from the
* RDMA_CM_EVENT_ROUTE_RESOLVED handler callback.
*/
int rdma_connect_locked(struct rdma_cm_id *id,
struct rdma_conn_param *conn_param)
{
struct rdma_id_private *id_priv =
container_of(id, struct rdma_id_private, id);
int ret;
mutex_lock(&id_priv->handler_mutex);
if (!cma_comp_exch(id_priv, RDMA_CM_ROUTE_RESOLVED, RDMA_CM_CONNECT)) {
ret = -EINVAL;
goto err_unlock;
}
if (!cma_comp_exch(id_priv, RDMA_CM_ROUTE_RESOLVED, RDMA_CM_CONNECT))
return -EINVAL;
if (!id->qp) {
id_priv->qp_num = conn_param->qp_num;
@ -4066,11 +4072,33 @@ int rdma_connect(struct rdma_cm_id *id, struct rdma_conn_param *conn_param)
ret = -ENOSYS;
if (ret)
goto err_state;
mutex_unlock(&id_priv->handler_mutex);
return 0;
err_state:
cma_comp_exch(id_priv, RDMA_CM_CONNECT, RDMA_CM_ROUTE_RESOLVED);
err_unlock:
return ret;
}
EXPORT_SYMBOL(rdma_connect_locked);
/**
* rdma_connect - Initiate an active connection request.
* @id: Connection identifier to connect.
* @conn_param: Connection information used for connected QPs.
*
* Users must have resolved a route for the rdma_cm_id to connect with by having
* called rdma_resolve_route before calling this routine.
*
* This call will either connect to a remote QP or obtain remote QP information
* for unconnected rdma_cm_id's. The actual operation is based on the
* rdma_cm_id's port space.
*/
int rdma_connect(struct rdma_cm_id *id, struct rdma_conn_param *conn_param)
{
struct rdma_id_private *id_priv =
container_of(id, struct rdma_id_private, id);
int ret;
mutex_lock(&id_priv->handler_mutex);
ret = rdma_connect_locked(id, conn_param);
mutex_unlock(&id_priv->handler_mutex);
return ret;
}

3
drivers/infiniband/core/uverbs_std_types_device.c
View File

@ -401,9 +401,6 @@ static int UVERBS_HANDLER(UVERBS_METHOD_QUERY_GID_ENTRY)(
if (!rdma_is_port_valid(ib_dev, port_num))
return -EINVAL;
if (!rdma_ib_or_roce(ib_dev, port_num))
return -EOPNOTSUPP;
gid_attr = rdma_get_gid_attr(ib_dev, port_num, gid_index);
if (IS_ERR(gid_attr))
return PTR_ERR(gid_attr);

6
drivers/infiniband/hw/mlx5/main.c
View File

@ -3305,7 +3305,8 @@ static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
int err;
dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event;
err = register_netdevice_notifier(&dev->port[port_num].roce.nb);
err = register_netdevice_notifier_net(mlx5_core_net(dev->mdev),
&dev->port[port_num].roce.nb);
if (err) {
dev->port[port_num].roce.nb.notifier_call = NULL;
return err;
@ -3317,7 +3318,8 @@ static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
{
if (dev->port[port_num].roce.nb.notifier_call) {
unregister_netdevice_notifier(&dev->port[port_num].roce.nb);
unregister_netdevice_notifier_net(mlx5_core_net(dev->mdev),
&dev->port[port_num].roce.nb);
dev->port[port_num].roce.nb.notifier_call = NULL;
}
}

1
drivers/infiniband/hw/qedr/qedr_iw_cm.c
View File

@ -727,6 +727,7 @@ int qedr_iw_destroy_listen(struct iw_cm_id *cm_id)
listener->qed_handle);
cm_id->rem_ref(cm_id);
kfree(listener);
return rc;
}

35
drivers/infiniband/sw/rxe/rxe_av.c
View File

@ -16,15 +16,24 @@ void rxe_init_av(struct rdma_ah_attr *attr, struct rxe_av *av)
int rxe_av_chk_attr(struct rxe_dev *rxe, struct rdma_ah_attr *attr)
{
const struct ib_global_route *grh = rdma_ah_read_grh(attr);
struct rxe_port *port;
int type;
port = &rxe->port;
if (rdma_ah_get_ah_flags(attr) & IB_AH_GRH) {
u8 sgid_index = rdma_ah_read_grh(attr)->sgid_index;
if (grh->sgid_index > port->attr.gid_tbl_len) {
pr_warn("invalid sgid index = %d\n",
grh->sgid_index);
return -EINVAL;
}
if (sgid_index > port->attr.gid_tbl_len) {
pr_warn("invalid sgid index = %d\n", sgid_index);
type = rdma_gid_attr_network_type(grh->sgid_attr);
if (type < RDMA_NETWORK_IPV4 ||
type > RDMA_NETWORK_IPV6) {
pr_warn("invalid network type for rdma_rxe = %d\n",
type);
return -EINVAL;
}
}
@ -65,11 +74,29 @@ void rxe_av_to_attr(struct rxe_av *av, struct rdma_ah_attr *attr)
void rxe_av_fill_ip_info(struct rxe_av *av, struct rdma_ah_attr *attr)
{
const struct ib_gid_attr *sgid_attr = attr->grh.sgid_attr;
int ibtype;
int type;
rdma_gid2ip((struct sockaddr *)&av->sgid_addr, &sgid_attr->gid);
rdma_gid2ip((struct sockaddr *)&av->dgid_addr,
&rdma_ah_read_grh(attr)->dgid);
av->network_type = rdma_gid_attr_network_type(sgid_attr);
ibtype = rdma_gid_attr_network_type(sgid_attr);
switch (ibtype) {
case RDMA_NETWORK_IPV4:
type = RXE_NETWORK_TYPE_IPV4;
break;
case RDMA_NETWORK_IPV6:
type = RXE_NETWORK_TYPE_IPV4;
break;
default:
/* not reached - checked in rxe_av_chk_attr */
type = 0;
break;
}
av->network_type = type;
}
struct rxe_av *rxe_get_av(struct rxe_pkt_info *pkt)

2
drivers/infiniband/sw/rxe/rxe_net.c
View File

@ -442,7 +442,7 @@ struct sk_buff *rxe_init_packet(struct rxe_dev *rxe, struct rxe_av *av,
if (IS_ERR(attr))
return NULL;
if (av->network_type == RXE_NETWORK_TYPE_IPV6)
if (av->network_type == RXE_NETWORK_TYPE_IPV4)
hdr_len = ETH_HLEN + sizeof(struct udphdr) +
sizeof(struct iphdr);
else

2
drivers/infiniband/ulp/iser/iser_verbs.c
View File

@ -620,7 +620,7 @@ static void iser_route_handler(struct rdma_cm_id *cma_id)
conn_param.private_data = (void *)&req_hdr;
conn_param.private_data_len = sizeof(struct iser_cm_hdr);
ret = rdma_connect(cma_id, &conn_param);
ret = rdma_connect_locked(cma_id, &conn_param);
if (ret) {
iser_err("failure connecting: %d\n", ret);
goto failure;

4
drivers/infiniband/ulp/rtrs/rtrs-clt.c
View File

@ -1674,9 +1674,9 @@ static int rtrs_rdma_route_resolved(struct rtrs_clt_con *con)
uuid_copy(&msg.sess_uuid, &sess->s.uuid);
uuid_copy(&msg.paths_uuid, &clt->paths_uuid);
err = rdma_connect(con->c.cm_id, &param);
err = rdma_connect_locked(con->c.cm_id, &param);
if (err)
rtrs_err(clt, "rdma_connect(): %d\n", err);
rtrs_err(clt, "rdma_connect_locked(): %d\n", err);
return err;
}

2
drivers/mmc/host/sdhci-esdhc.h
View File

@ -5,6 +5,7 @@
* Copyright (c) 2007 Freescale Semiconductor, Inc.
* Copyright (c) 2009 MontaVista Software, Inc.
* Copyright (c) 2010 Pengutronix e.K.
* Copyright 2020 NXP
* Author: Wolfram Sang <kernel@pengutronix.de>
*/
@ -88,6 +89,7 @@
/* DLL Config 0 Register */
#define ESDHC_DLLCFG0 0x160
#define ESDHC_DLL_ENABLE 0x80000000
#define ESDHC_DLL_RESET 0x40000000
#define ESDHC_DLL_FREQ_SEL 0x08000000
/* DLL Config 1 Register */

28
drivers/mmc/host/sdhci-of-esdhc.c
View File

@ -4,6 +4,7 @@
*
* Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc.
* Copyright (c) 2009 MontaVista Software, Inc.
* Copyright 2020 NXP
*
* Authors: Xiaobo Xie <X.Xie@freescale.com>
* Anton Vorontsov <avorontsov@ru.mvista.com>
@ -19,6 +20,7 @@
#include <linux/clk.h>
#include <linux/ktime.h>
#include <linux/dma-mapping.h>
#include <linux/iopoll.h>
#include <linux/mmc/host.h>
#include <linux/mmc/mmc.h>
#include "sdhci-pltfm.h"
@ -743,6 +745,21 @@ static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
if (host->mmc->actual_clock == MMC_HS200_MAX_DTR)
temp |= ESDHC_DLL_FREQ_SEL;
sdhci_writel(host, temp, ESDHC_DLLCFG0);
temp |= ESDHC_DLL_RESET;
sdhci_writel(host, temp, ESDHC_DLLCFG0);
udelay(1);
temp &= ~ESDHC_DLL_RESET;
sdhci_writel(host, temp, ESDHC_DLLCFG0);
/* Wait max 20 ms */
if (read_poll_timeout(sdhci_readl, temp,
temp & ESDHC_DLL_STS_SLV_LOCK,
10, 20000, false,
host, ESDHC_DLLSTAT0))
pr_err("%s: timeout for delay chain lock.\n",
mmc_hostname(host->mmc));
temp = sdhci_readl(host, ESDHC_TBCTL);
sdhci_writel(host, temp | ESDHC_HS400_WNDW_ADJUST, ESDHC_TBCTL);
@ -1052,6 +1069,17 @@ static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
esdhc_tuning_block_enable(host, true);
/*
* The eSDHC controller takes the data timeout value into account
* during tuning. If the SD card is too slow sending the response, the
* timer will expire and a "Buffer Read Ready" interrupt without data
* is triggered. This leads to tuning errors.
*
* Just set the timeout to the maximum value because the core will
* already take care of it in sdhci_send_tuning().
*/
sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
hs400_tuning = host->flags & SDHCI_HS400_TUNING;
do {

6
drivers/mmc/host/sdhci.c
View File

@ -1384,9 +1384,11 @@ static inline void sdhci_auto_cmd_select(struct sdhci_host *host,
/*
* In case of Version 4.10 or later, use of 'Auto CMD Auto
* Select' is recommended rather than use of 'Auto CMD12
* Enable' or 'Auto CMD23 Enable'.
* Enable' or 'Auto CMD23 Enable'. We require Version 4 Mode
* here because some controllers (e.g sdhci-of-dwmshc) expect it.
*/
if (host->version >= SDHCI_SPEC_410 && (use_cmd12 || use_cmd23)) {
if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
(use_cmd12 || use_cmd23)) {
*mode |= SDHCI_TRNS_AUTO_SEL;
ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);

49
drivers/net/ethernet/broadcom/bnxt/bnxt.c
View File

@ -1160,16 +1160,6 @@ static void bnxt_queue_sp_work(struct bnxt *bp)
schedule_work(&bp->sp_task);
}
static void bnxt_cancel_sp_work(struct bnxt *bp)
{
if (BNXT_PF(bp)) {
flush_workqueue(bnxt_pf_wq);
} else {
cancel_work_sync(&bp->sp_task);
cancel_delayed_work_sync(&bp->fw_reset_task);
}
}
static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
{
if (!rxr->bnapi->in_reset) {
@ -4362,7 +4352,8 @@ static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
u32 bar_offset = BNXT_GRCPF_REG_CHIMP_COMM;
u16 dst = BNXT_HWRM_CHNL_CHIMP;
if (BNXT_NO_FW_ACCESS(bp))
if (BNXT_NO_FW_ACCESS(bp) &&
le16_to_cpu(req->req_type) != HWRM_FUNC_RESET)
return -EBUSY;
if (msg_len > BNXT_HWRM_MAX_REQ_LEN) {
@ -9789,7 +9780,10 @@ int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
{
int rc = 0;
rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state))
rc = -EIO;
if (!rc)
rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
if (rc) {
netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
dev_close(bp->dev);
@ -12108,15 +12102,17 @@ static void bnxt_remove_one(struct pci_dev *pdev)
if (BNXT_PF(bp))
bnxt_sriov_disable(bp);
clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
bnxt_cancel_sp_work(bp);
bp->sp_event = 0;
bnxt_dl_fw_reporters_destroy(bp, true);
if (BNXT_PF(bp))
devlink_port_type_clear(&bp->dl_port);
pci_disable_pcie_error_reporting(pdev);
unregister_netdev(dev);
clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
/* Flush any pending tasks */
cancel_work_sync(&bp->sp_task);
cancel_delayed_work_sync(&bp->fw_reset_task);
bp->sp_event = 0;
bnxt_dl_fw_reporters_destroy(bp, true);
bnxt_dl_unregister(bp);
bnxt_shutdown_tc(bp);
@ -12860,6 +12856,9 @@ static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
return PCI_ERS_RESULT_DISCONNECT;
}
if (state == pci_channel_io_frozen)
set_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN, &bp->state);
if (netif_running(netdev))
bnxt_close(netdev);
@ -12886,7 +12885,7 @@ static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
{
struct net_device *netdev = pci_get_drvdata(pdev);
struct bnxt *bp = netdev_priv(netdev);
int err = 0;
int err = 0, off;
pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
netdev_info(bp->dev, "PCI Slot Reset\n");
@ -12898,6 +12897,20 @@ static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
"Cannot re-enable PCI device after reset.\n");
} else {
pci_set_master(pdev);
/* Upon fatal error, our device internal logic that latches to
* BAR value is getting reset and will restore only upon
* rewritting the BARs.
*
* As pci_restore_state() does not re-write the BARs if the
* value is same as saved value earlier, driver needs to
* write the BARs to 0 to force restore, in case of fatal error.
*/
if (test_and_clear_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN,
&bp->state)) {
for (off = PCI_BASE_ADDRESS_0;
off <= PCI_BASE_ADDRESS_5; off += 4)
pci_write_config_dword(bp->pdev, off, 0);
}
pci_restore_state(pdev);
pci_save_state(pdev);

1
drivers/net/ethernet/broadcom/bnxt/bnxt.h
View File

@ -1781,6 +1781,7 @@ struct bnxt {
#define BNXT_STATE_ABORT_ERR 5
#define BNXT_STATE_FW_FATAL_COND 6
#define BNXT_STATE_DRV_REGISTERED 7
#define BNXT_STATE_PCI_CHANNEL_IO_FROZEN 8
#define BNXT_NO_FW_ACCESS(bp) \
(test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) || \

56
drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c
View File

@ -145,13 +145,13 @@ static int configure_filter_smac(struct adapter *adap, struct filter_entry *f)
int err;
/* do a set-tcb for smac-sel and CWR bit.. */
err = set_tcb_tflag(adap, f, f->tid, TF_CCTRL_CWR_S, 1, 1);
if (err)
goto smac_err;
err = set_tcb_field(adap, f, f->tid, TCB_SMAC_SEL_W,
TCB_SMAC_SEL_V(TCB_SMAC_SEL_M),
TCB_SMAC_SEL_V(f->smt->idx), 1);
if (err)
goto smac_err;
err = set_tcb_tflag(adap, f, f->tid, TF_CCTRL_CWR_S, 1, 1);
if (!err)
return 0;
@ -862,6 +862,7 @@ int set_filter_wr(struct adapter *adapter, int fidx)
FW_FILTER_WR_DIRSTEERHASH_V(f->fs.dirsteerhash) |
FW_FILTER_WR_LPBK_V(f->fs.action == FILTER_SWITCH) |
FW_FILTER_WR_DMAC_V(f->fs.newdmac) |
FW_FILTER_WR_SMAC_V(f->fs.newsmac) |
FW_FILTER_WR_INSVLAN_V(f->fs.newvlan == VLAN_INSERT ||
f->fs.newvlan == VLAN_REWRITE) |
FW_FILTER_WR_RMVLAN_V(f->fs.newvlan == VLAN_REMOVE ||
@ -879,7 +880,7 @@ int set_filter_wr(struct adapter *adapter, int fidx)
FW_FILTER_WR_OVLAN_VLD_V(f->fs.val.ovlan_vld) |
FW_FILTER_WR_IVLAN_VLDM_V(f->fs.mask.ivlan_vld) |
FW_FILTER_WR_OVLAN_VLDM_V(f->fs.mask.ovlan_vld));
fwr->smac_sel = 0;
fwr->smac_sel = f->smt->idx;
fwr->rx_chan_rx_rpl_iq =
htons(FW_FILTER_WR_RX_CHAN_V(0) |
FW_FILTER_WR_RX_RPL_IQ_V(adapter->sge.fw_evtq.abs_id));
@ -1323,11 +1324,8 @@ static void mk_act_open_req6(struct filter_entry *f, struct sk_buff *skb,
TX_QUEUE_V(f->fs.nat_mode) |
T5_OPT_2_VALID_F |
RX_CHANNEL_V(cxgb4_port_e2cchan(f->dev)) |
CONG_CNTRL_V((f->fs.action == FILTER_DROP) |
(f->fs.dirsteer << 1)) |
PACE_V((f->fs.maskhash) |
((f->fs.dirsteerhash) << 1)) |
CCTRL_ECN_V(f->fs.action == FILTER_SWITCH));
((f->fs.dirsteerhash) << 1)));
}
static void mk_act_open_req(struct filter_entry *f, struct sk_buff *skb,
@ -1363,11 +1361,8 @@ static void mk_act_open_req(struct filter_entry *f, struct sk_buff *skb,
TX_QUEUE_V(f->fs.nat_mode) |
T5_OPT_2_VALID_F |
RX_CHANNEL_V(cxgb4_port_e2cchan(f->dev)) |
CONG_CNTRL_V((f->fs.action == FILTER_DROP) |
(f->fs.dirsteer << 1)) |
PACE_V((f->fs.maskhash) |
((f->fs.dirsteerhash) << 1)) |
CCTRL_ECN_V(f->fs.action == FILTER_SWITCH));
((f->fs.dirsteerhash) << 1)));
}
static int cxgb4_set_hash_filter(struct net_device *dev,
@ -2039,6 +2034,20 @@ void hash_filter_rpl(struct adapter *adap, const struct cpl_act_open_rpl *rpl)
}
return;
}
switch (f->fs.action) {
case FILTER_PASS:
if (f->fs.dirsteer)
set_tcb_tflag(adap, f, tid,
TF_DIRECT_STEER_S, 1, 1);
break;
case FILTER_DROP:
set_tcb_tflag(adap, f, tid, TF_DROP_S, 1, 1);
break;
case FILTER_SWITCH:
set_tcb_tflag(adap, f, tid, TF_LPBK_S, 1, 1);
break;
}
break;
default:
@ -2106,22 +2115,11 @@ void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
if (ctx)
ctx->result = 0;
} else if (ret == FW_FILTER_WR_FLT_ADDED) {
int err = 0;
if (f->fs.newsmac)
err = configure_filter_smac(adap, f);
if (!err) {
f->pending = 0; /* async setup completed */
f->valid = 1;
if (ctx) {
ctx->result = 0;
ctx->tid = idx;
}
} else {
clear_filter(adap, f);
if (ctx)
ctx->result = err;
f->pending = 0; /* async setup completed */
f->valid = 1;
if (ctx) {
ctx->result = 0;
ctx->tid = idx;
}
} else {
/* Something went wrong. Issue a warning about the

4
drivers/net/ethernet/chelsio/cxgb4/t4_tcb.h
View File

@ -50,6 +50,10 @@
#define TCB_T_FLAGS_M 0xffffffffffffffffULL
#define TCB_T_FLAGS_V(x) ((__u64)(x) << TCB_T_FLAGS_S)
#define TF_DROP_S 22
#define TF_DIRECT_STEER_S 23
#define TF_LPBK_S 59
#define TF_CCTRL_ECE_S 60
#define TF_CCTRL_CWR_S 61
#define TF_CCTRL_RFR_S 62

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