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arm: dts: mt7623: move display nodes to separate mt7623n.dtsi
mt7623a has no graphics support so move nodes from generic mt7623.dtsi
to mt7623n.dtsi
Fixes: 1f6ed22459 ("arm: dts: mt7623: add Mali-450 device node")
Suggested-by: David Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Link: https://lore.kernel.org/r/20200904110002.88966-3-linux@fw-web.de
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Frank Wunderlich
Matthias Brugger
parent
27831102b8
commit
c0d66c560e
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@ -14,7 +14,6 @@
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#include <dt-bindings/power/mt2701-power.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/memory/mt2701-larb-port.h>
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#include <dt-bindings/reset/mt2701-resets.h>
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#include <dt-bindings/thermal/thermal.h>
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@ -297,17 +296,6 @@ timer: timer@10008000 {
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clock-names = "system-clk", "rtc-clk";
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};
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smi_common: smi@1000c000 {
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compatible = "mediatek,mt7623-smi-common",
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"mediatek,mt2701-smi-common";
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reg = <0 0x1000c000 0 0x1000>;
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clocks = <&infracfg CLK_INFRA_SMI>,
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<&mmsys CLK_MM_SMI_COMMON>,
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<&infracfg CLK_INFRA_SMI>;
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clock-names = "apb", "smi", "async";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
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};
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pwrap: pwrap@1000d000 {
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compatible = "mediatek,mt7623-pwrap",
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"mediatek,mt2701-pwrap";
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@ -339,17 +327,6 @@ sysirq: interrupt-controller@10200100 {
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reg = <0 0x10200100 0 0x1c>;
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};
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iommu: mmsys_iommu@10205000 {
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compatible = "mediatek,mt7623-m4u",
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"mediatek,mt2701-m4u";
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reg = <0 0x10205000 0 0x1000>;
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interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infracfg CLK_INFRA_M4U>;
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clock-names = "bclk";
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mediatek,larbs = <&larb0 &larb1 &larb2>;
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#iommu-cells = <1>;
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};
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efuse: efuse@10206000 {
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compatible = "mediatek,mt7623-efuse",
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"mediatek,mt8173-efuse";
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@ -725,94 +702,6 @@ mmc1: mmc@11240000 {
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status = "disabled";
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};
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g3dsys: syscon@13000000 {
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compatible = "mediatek,mt7623-g3dsys",
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"mediatek,mt2701-g3dsys",
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"syscon";
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reg = <0 0x13000000 0 0x200>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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mali: gpu@13040000 {
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compatible = "mediatek,mt7623-mali", "arm,mali-450";
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reg = <0 0x13040000 0 0x30000>;
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interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 172 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 173 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 178 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 179 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
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"ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3",
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"pp";
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clocks = <&topckgen CLK_TOP_MMPLL>,
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<&g3dsys CLK_G3DSYS_CORE>;
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clock-names = "bus", "core";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>;
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resets = <&g3dsys MT2701_G3DSYS_CORE_RST>;
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};
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mmsys: syscon@14000000 {
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compatible = "mediatek,mt7623-mmsys",
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"mediatek,mt2701-mmsys",
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"syscon";
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reg = <0 0x14000000 0 0x1000>;
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#clock-cells = <1>;
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};
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larb0: larb@14010000 {
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compatible = "mediatek,mt7623-smi-larb",
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"mediatek,mt2701-smi-larb";
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reg = <0 0x14010000 0 0x1000>;
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mediatek,smi = <&smi_common>;
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mediatek,larb-id = <0>;
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clocks = <&mmsys CLK_MM_SMI_LARB0>,
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<&mmsys CLK_MM_SMI_LARB0>;
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clock-names = "apb", "smi";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
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};
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imgsys: syscon@15000000 {
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compatible = "mediatek,mt7623-imgsys",
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"mediatek,mt2701-imgsys",
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"syscon";
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reg = <0 0x15000000 0 0x1000>;
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#clock-cells = <1>;
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};
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larb2: larb@15001000 {
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compatible = "mediatek,mt7623-smi-larb",
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"mediatek,mt2701-smi-larb";
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reg = <0 0x15001000 0 0x1000>;
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mediatek,smi = <&smi_common>;
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mediatek,larb-id = <2>;
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clocks = <&imgsys CLK_IMG_SMI_COMM>,
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<&imgsys CLK_IMG_SMI_COMM>;
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clock-names = "apb", "smi";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
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};
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jpegdec: jpegdec@15004000 {
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compatible = "mediatek,mt7623-jpgdec",
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"mediatek,mt2701-jpgdec";
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reg = <0 0x15004000 0 0x1000>;
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interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
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<&imgsys CLK_IMG_JPGDEC>;
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clock-names = "jpgdec-smi",
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"jpgdec";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
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mediatek,larb = <&larb2>;
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iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
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<&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
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};
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vdecsys: syscon@16000000 {
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compatible = "mediatek,mt7623-vdecsys",
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"mediatek,mt2701-vdecsys",
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@ -821,18 +710,6 @@ vdecsys: syscon@16000000 {
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#clock-cells = <1>;
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};
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larb1: larb@16010000 {
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compatible = "mediatek,mt7623-smi-larb",
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"mediatek,mt2701-smi-larb";
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reg = <0 0x16010000 0 0x1000>;
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mediatek,smi = <&smi_common>;
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mediatek,larb-id = <1>;
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clocks = <&vdecsys CLK_VDEC_CKGEN>,
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<&vdecsys CLK_VDEC_LARB>;
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clock-names = "apb", "smi";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
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};
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hifsys: syscon@1a000000 {
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compatible = "mediatek,mt7623-hifsys",
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"mediatek,mt2701-hifsys",
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@ -6,7 +6,7 @@
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include "mt7623.dtsi"
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#include "mt7623n.dtsi"
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#include "mt6323.dtsi"
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/ {
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@ -7,7 +7,7 @@
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include "mt7623.dtsi"
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#include "mt7623n.dtsi"
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#include "mt6323.dtsi"
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/ {
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134
arch/arm/boot/dts/mt7623n.dtsi
Normal file
134
arch/arm/boot/dts/mt7623n.dtsi
Normal file
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@ -0,0 +1,134 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright © 2017-2020 MediaTek Inc.
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* Author: Sean Wang <sean.wang@mediatek.com>
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* Ryder Lee <ryder.lee@mediatek.com>
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*
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*/
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#include "mt7623.dtsi"
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#include <dt-bindings/memory/mt2701-larb-port.h>
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/ {
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g3dsys: syscon@13000000 {
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compatible = "mediatek,mt7623-g3dsys",
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"mediatek,mt2701-g3dsys",
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"syscon";
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reg = <0 0x13000000 0 0x200>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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mali: gpu@13040000 {
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compatible = "mediatek,mt7623-mali", "arm,mali-450";
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reg = <0 0x13040000 0 0x30000>;
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interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 172 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 173 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 178 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 179 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
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"ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3",
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"pp";
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clocks = <&topckgen CLK_TOP_MMPLL>,
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<&g3dsys CLK_G3DSYS_CORE>;
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clock-names = "bus", "core";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>;
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resets = <&g3dsys MT2701_G3DSYS_CORE_RST>;
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};
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mmsys: syscon@14000000 {
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compatible = "mediatek,mt7623-mmsys",
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"mediatek,mt2701-mmsys",
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"syscon";
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reg = <0 0x14000000 0 0x1000>;
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#clock-cells = <1>;
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};
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larb0: larb@14010000 {
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compatible = "mediatek,mt7623-smi-larb",
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"mediatek,mt2701-smi-larb";
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reg = <0 0x14010000 0 0x1000>;
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mediatek,smi = <&smi_common>;
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mediatek,larb-id = <0>;
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clocks = <&mmsys CLK_MM_SMI_LARB0>,
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<&mmsys CLK_MM_SMI_LARB0>;
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clock-names = "apb", "smi";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
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};
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larb1: larb@16010000 {
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compatible = "mediatek,mt7623-smi-larb",
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"mediatek,mt2701-smi-larb";
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reg = <0 0x16010000 0 0x1000>;
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mediatek,smi = <&smi_common>;
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mediatek,larb-id = <1>;
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clocks = <&vdecsys CLK_VDEC_CKGEN>,
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<&vdecsys CLK_VDEC_LARB>;
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clock-names = "apb", "smi";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
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};
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larb2: larb@15001000 {
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compatible = "mediatek,mt7623-smi-larb",
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"mediatek,mt2701-smi-larb";
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reg = <0 0x15001000 0 0x1000>;
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mediatek,smi = <&smi_common>;
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mediatek,larb-id = <2>;
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clocks = <&imgsys CLK_IMG_SMI_COMM>,
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<&imgsys CLK_IMG_SMI_COMM>;
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clock-names = "apb", "smi";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
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};
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imgsys: syscon@15000000 {
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compatible = "mediatek,mt7623-imgsys",
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"mediatek,mt2701-imgsys",
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"syscon";
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reg = <0 0x15000000 0 0x1000>;
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#clock-cells = <1>;
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};
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iommu: mmsys_iommu@10205000 {
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compatible = "mediatek,mt7623-m4u",
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"mediatek,mt2701-m4u";
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reg = <0 0x10205000 0 0x1000>;
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interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infracfg CLK_INFRA_M4U>;
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clock-names = "bclk";
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mediatek,larbs = <&larb0 &larb1 &larb2>;
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#iommu-cells = <1>;
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};
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jpegdec: jpegdec@15004000 {
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compatible = "mediatek,mt7623-jpgdec",
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"mediatek,mt2701-jpgdec";
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reg = <0 0x15004000 0 0x1000>;
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interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
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<&imgsys CLK_IMG_JPGDEC>;
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clock-names = "jpgdec-smi",
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"jpgdec";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
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mediatek,larb = <&larb2>;
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iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
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<&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
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};
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smi_common: smi@1000c000 {
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compatible = "mediatek,mt7623-smi-common",
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"mediatek,mt2701-smi-common";
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reg = <0 0x1000c000 0 0x1000>;
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clocks = <&infracfg CLK_INFRA_SMI>,
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<&mmsys CLK_MM_SMI_COMMON>,
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<&infracfg CLK_INFRA_SMI>;
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clock-names = "apb", "smi", "async";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
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};
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};
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