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dt-bindings: display: rockchip: Add schema for RK3588 HDMI TX Controller
Rockchip RK3588 SoC integrates the Synopsys DesignWare HDMI 2.1 Quad-Pixel (QP) TX controller IP. Since this is a new IP block, quite different from those used in the previous generations of Rockchip SoCs, add a dedicated binding file. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241016-b4-rk3588-bridge-upstream-v10-2-87ef92a6d14e@collabora.com Signed-off-by: Maxime Ripard <mripard@kernel.org>
This commit is contained in:
Cristian Ciocaltea
Maxime Ripard
parent
5bd0d8e687
commit
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3588-dw-hdmi-qp.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip DW HDMI QP TX Encoder
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maintainers:
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- Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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description: |
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Rockchip RK3588 SoC integrates the Synopsys DesignWare HDMI QP TX controller
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IP and a HDMI/eDP TX Combo PHY based on a Samsung IP block, providing the
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following features, among others:
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* Fixed Rate Link (FRL)
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* Display Stream Compression (DSC)
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* 4K@120Hz and 8K@60Hz video modes
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* Variable Refresh Rate (VRR) including Quick Media Switching (QMS)
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* Fast Vactive (FVA)
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* SCDC I2C DDC access
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* Multi-stream audio
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* Enhanced Audio Return Channel (EARC)
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allOf:
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- $ref: /schemas/sound/dai-common.yaml#
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properties:
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compatible:
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enum:
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- rockchip,rk3588-dw-hdmi-qp
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Peripheral/APB bus clock
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- description: EARC RX biphase clock
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- description: Reference clock
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- description: Audio interface clock
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- description: TMDS/FRL link clock
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- description: Video datapath clock
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clock-names:
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items:
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- const: pclk
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- const: earc
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- const: ref
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- const: aud
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- const: hdp
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- const: hclk_vo1
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interrupts:
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items:
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- description: AVP Unit interrupt
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- description: CEC interrupt
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- description: eARC RX interrupt
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- description: Main Unit interrupt
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- description: HPD interrupt
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interrupt-names:
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items:
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- const: avp
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- const: cec
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- const: earc
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- const: main
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- const: hpd
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phys:
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maxItems: 1
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description: The HDMI/eDP PHY
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: Video port for RGB/YUV input.
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description: Video port for HDMI/eDP output.
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required:
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- port@0
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- port@1
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power-domains:
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maxItems: 1
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resets:
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maxItems: 2
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reset-names:
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items:
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- const: ref
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- const: hdp
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"#sound-dai-cells":
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const: 0
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rockchip,grf:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Some HDMI QP related data is accessed through SYS GRF regs.
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rockchip,vo-grf:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Additional HDMI QP related data is accessed through VO GRF regs.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- interrupts
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- interrupt-names
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- phys
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- ports
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- resets
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- reset-names
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- rockchip,grf
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- rockchip,vo-grf
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/rockchip,rk3588-cru.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/power/rk3588-power.h>
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#include <dt-bindings/reset/rockchip,rk3588-cru.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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hdmi@fde80000 {
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compatible = "rockchip,rk3588-dw-hdmi-qp";
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reg = <0x0 0xfde80000 0x0 0x20000>;
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clocks = <&cru PCLK_HDMITX0>,
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<&cru CLK_HDMITX0_EARC>,
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<&cru CLK_HDMITX0_REF>,
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<&cru MCLK_I2S5_8CH_TX>,
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<&cru CLK_HDMIHDP0>,
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<&cru HCLK_VO1>;
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clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
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interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "avp", "cec", "earc", "main", "hpd";
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phys = <&hdptxphy_hdmi0>;
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power-domains = <&power RK3588_PD_VO1>;
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resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>;
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reset-names = "ref", "hdp";
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rockchip,grf = <&sys_grf>;
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rockchip,vo-grf = <&vo1_grf>;
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#sound-dai-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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hdmi0_in_vp0: endpoint {
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remote-endpoint = <&vp0_out_hdmi0>;
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};
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};
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port@1 {
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reg = <1>;
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hdmi0_out_con0: endpoint {
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remote-endpoint = <&hdmi_con0_in>;
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};
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};
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};
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};
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};
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