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arm64: dts: qcom: sdm630/660: Add CDSP-related nodes

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In order to enable CDSP support for SDM660 SoC:
 * add shared memory p2p nodes for CDSP
 * add CDSP-specific smmu node
 * add CDSP peripheral image loader node

Memory region for CDSP in SDM660 occupies the same spot as
TZ buffer mem defined in sdm630.dtsi (which does not have CDSP).
In sdm660.dtsi replace buffer_mem inherited from SDM630 with
cdsp_region, which is also larger in size.

SDM636 also doesn't have CDSP, so remove inherited from sdm660.dtsi
related nodes and add buffer_mem back.

Signed-off-by: Nickolay Goppen <setotau@mainlining.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251110-qcom-sdm660-cdsp-adsp-dts-v3-1-d1f1c86e2e6d@mainlining.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Nickolay Goppen 2025-11-10 21:55:06 +03:00 committed by Bjorn Andersson
parent 512716f696
commit c0c32a9e34
3 changed files with 176 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm64/boot/dts/qcom/sdm630.dtsi
View File

@ -563,7 +563,7 @@ modem_smp2p_in: slave-kernel {
};
};
soc@0 {
soc: soc@0 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;

23
arch/arm64/boot/dts/qcom/sdm636.dtsi
View File

@ -7,15 +7,20 @@
#include "sdm660.dtsi"
/*
* According to the downstream DTS,
* 636 is basically a 660 except for
* different CPU frequencies, Adreno
* 509 instead of 512 and lack of
* turing IP. These differences will
* be addressed when the aforementioned
* peripherals will be enabled upstream.
*/
/delete-node/ &remoteproc_cdsp;
/delete-node/ &cdsp_smmu;
/delete-node/ &cdsp_region;
/ {
/delete-node/ smp2p-cdsp;
reserved-memory {
buffer_mem: tzbuffer@94a00000 {
reg = <0x0 0x94a00000 0x00 0x100000>;
no-map;
};
};
};
&adreno_gpu {
compatible = "qcom,adreno-509.0", "qcom,adreno";

161
arch/arm64/boot/dts/qcom/sdm660.dtsi
View File

@ -9,6 +9,37 @@
#include "sdm630.dtsi"
/delete-node/ &buffer_mem;
/ {
smp2p-cdsp {
compatible = "qcom,smp2p";
qcom,smem = <94>, <432>;
interrupts = <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apcs_glb 30>;
qcom,local-pid = <0>;
qcom,remote-pid = <5>;
cdsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
cdsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
reserved-memory {
cdsp_region: cdsp@94a00000 {
reg = <0x0 0x94a00000 0x00 0x600000>;
no-map;
};
};
};
&adreno_gpu {
compatible = "qcom,adreno-512.0", "qcom,adreno";
operating-points-v2 = <&gpu_sdm660_opp_table>;
@ -247,6 +278,136 @@ &mmcc {
<0>;
};
&soc {
cdsp_smmu: iommu@5180000 {
compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
reg = <0x5180000 0x40000>;
#iommu-cells = <1>;
#global-interrupts = <2>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_HLOS1_VOTE_TURING_ADSP_SMMU_CLK>;
clock-names = "bus";
power-domains = <&gcc HLOS1_VOTE_TURING_ADSP_GDSC>;
};
remoteproc_cdsp: remoteproc@1a300000 {
compatible = "qcom,sdm660-cdsp-pas";
reg = <0x1a300000 0x00100>;
interrupts-extended = <&intc GIC_SPI 518 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog",
"fatal",
"ready",
"handover",
"stop-ack";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "xo";
memory-region = <&cdsp_region>;
power-domains = <&rpmpd SDM660_VDDCX>;
power-domain-names = "cx";
qcom,smem-states = <&cdsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
glink-edge {
interrupts = <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>;
label = "cdsp";
mboxes = <&apcs_glb 29>;
qcom,remote-pid = <5>;
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "cdsp";
#address-cells = <1>;
#size-cells = <0>;
compute-cb@5 {
compatible = "qcom,fastrpc-compute-cb";
reg = <5>;
iommus = <&cdsp_smmu 3>;
};
compute-cb@6 {
compatible = "qcom,fastrpc-compute-cb";
reg = <6>;
iommus = <&cdsp_smmu 4>;
};
compute-cb@7 {
compatible = "qcom,fastrpc-compute-cb";
reg = <7>;
iommus = <&cdsp_smmu 5>;
};
compute-cb@8 {
compatible = "qcom,fastrpc-compute-cb";
reg = <8>;
iommus = <&cdsp_smmu 6>;
};
compute-cb@9 {
compatible = "qcom,fastrpc-compute-cb";
reg = <9>;
iommus = <&cdsp_smmu 7>;
};
compute-cb@10 {
compatible = "qcom,fastrpc-compute-cb";
reg = <10>;
iommus = <&cdsp_smmu 8>;
};
compute-cb@11 {
compatible = "qcom,fastrpc-compute-cb";
reg = <11>;
iommus = <&cdsp_smmu 9>;
};
compute-cb@12 {
compatible = "qcom,fastrpc-compute-cb";
reg = <12>;
iommus = <&cdsp_smmu 10>;
};
compute-cb@13 {
compatible = "qcom,fastrpc-compute-cb";
reg = <13>;
iommus = <&cdsp_smmu 11>;
};
};
};
};
};
&tlmm {
compatible = "qcom,sdm660-pinctrl";
};