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wifi: ath12k: Move srng config and hal_ops to hw specific hal files

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Move srng config and hal_ops from common hal file to
hw specific hal files, since these implementations are
specific and configurable for each hardware

Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.4.1-00199-QCAHKSWPL_SILICONZ-1
Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.0.c5-00481-QCAHMTSWPL_V1.0_V2.0_SILICONZ-3

Signed-off-by: Pavankumar Nandeshwar <quic_pnandesh@quicinc.com>
Signed-off-by: Ripan Deuri <quic_rdeuri@quicinc.com>
Reviewed-by: Baochen Qiang <baochen.qiang@oss.qualcomm.com>
Reviewed-by: Vasanthakumar Thiagarajan <vasanthakumar.thiagarajan@oss.qualcomm.com>
Link: https://patch.msgid.link/20251009111045.1763001-2-quic_rdeuri@quicinc.com
Signed-off-by: Jeff Johnson <jeff.johnson@oss.qualcomm.com>
This commit is contained in:
Pavankumar Nandeshwar 2025-10-09 16:40:28 +05:30 committed by Jeff Johnson
parent c57176c0da
commit c0600b35e0
5 changed files with 681 additions and 472 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

474
drivers/net/wireless/ath/ath12k/hal.c
View File

@ -12,210 +12,7 @@
#include "wifi7/hal_qcn9274.h"
#include "wifi7/hal_wcn7850.h"
static const struct hal_srng_config hw_srng_config_template[] = {
/* TODO: max_rings can populated by querying HW capabilities */
[HAL_REO_DST] = {
.start_ring_id = HAL_SRNG_RING_ID_REO2SW1,
.max_rings = 8,
.entry_size = sizeof(struct hal_reo_dest_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_DST,
.max_size = HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE,
},
[HAL_REO_EXCEPTION] = {
/* Designating REO2SW0 ring as exception ring.
* Any of theREO2SW rings can be used as exception ring.
*/
.start_ring_id = HAL_SRNG_RING_ID_REO2SW0,
.max_rings = 1,
.entry_size = sizeof(struct hal_reo_dest_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_DST,
.max_size = HAL_REO_REO2SW0_RING_BASE_MSB_RING_SIZE,
},
[HAL_REO_REINJECT] = {
.start_ring_id = HAL_SRNG_RING_ID_SW2REO,
.max_rings = 4,
.entry_size = sizeof(struct hal_reo_entrance_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE,
},
[HAL_REO_CMD] = {
.start_ring_id = HAL_SRNG_RING_ID_REO_CMD,
.max_rings = 1,
.entry_size = (sizeof(struct hal_tlv_64_hdr) +
sizeof(struct hal_reo_get_queue_stats)) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_REO_CMD_RING_BASE_MSB_RING_SIZE,
},
[HAL_REO_STATUS] = {
.start_ring_id = HAL_SRNG_RING_ID_REO_STATUS,
.max_rings = 1,
.entry_size = (sizeof(struct hal_tlv_64_hdr) +
sizeof(struct hal_reo_get_queue_stats_status)) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_DST,
.max_size = HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE,
},
[HAL_TCL_DATA] = {
.start_ring_id = HAL_SRNG_RING_ID_SW2TCL1,
.max_rings = 6,
.entry_size = sizeof(struct hal_tcl_data_cmd) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE,
},
[HAL_TCL_CMD] = {
.start_ring_id = HAL_SRNG_RING_ID_SW2TCL_CMD,
.max_rings = 1,
.entry_size = sizeof(struct hal_tcl_gse_cmd) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE,
},
[HAL_TCL_STATUS] = {
.start_ring_id = HAL_SRNG_RING_ID_TCL_STATUS,
.max_rings = 1,
.entry_size = (sizeof(struct hal_tlv_hdr) +
sizeof(struct hal_tcl_status_ring)) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_DST,
.max_size = HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE,
},
[HAL_CE_SRC] = {
.start_ring_id = HAL_SRNG_RING_ID_CE0_SRC,
.max_rings = 16,
.entry_size = sizeof(struct hal_ce_srng_src_desc) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_CE_SRC_RING_BASE_MSB_RING_SIZE,
},
[HAL_CE_DST] = {
.start_ring_id = HAL_SRNG_RING_ID_CE0_DST,
.max_rings = 16,
.entry_size = sizeof(struct hal_ce_srng_dest_desc) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_CE_DST_RING_BASE_MSB_RING_SIZE,
},
[HAL_CE_DST_STATUS] = {
.start_ring_id = HAL_SRNG_RING_ID_CE0_DST_STATUS,
.max_rings = 16,
.entry_size = sizeof(struct hal_ce_srng_dst_status_desc) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_DST,
.max_size = HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE,
},
[HAL_WBM_IDLE_LINK] = {
.start_ring_id = HAL_SRNG_RING_ID_WBM_IDLE_LINK,
.max_rings = 1,
.entry_size = sizeof(struct hal_wbm_link_desc) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE,
},
[HAL_SW2WBM_RELEASE] = {
.start_ring_id = HAL_SRNG_RING_ID_WBM_SW0_RELEASE,
.max_rings = 2,
.entry_size = sizeof(struct hal_wbm_release_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE,
},
[HAL_WBM2SW_RELEASE] = {
.start_ring_id = HAL_SRNG_RING_ID_WBM2SW0_RELEASE,
.max_rings = 8,
.entry_size = sizeof(struct hal_wbm_release_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_DST,
.max_size = HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE,
},
[HAL_RXDMA_BUF] = {
.start_ring_id = HAL_SRNG_SW2RXDMA_BUF0,
.max_rings = 1,
.entry_size = sizeof(struct hal_wbm_buffer_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_DMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
},
[HAL_RXDMA_DST] = {
.start_ring_id = HAL_SRNG_RING_ID_WMAC1_RXDMA2SW0,
.max_rings = 0,
.entry_size = 0,
.mac_type = ATH12K_HAL_SRNG_PMAC,
.ring_dir = HAL_SRNG_DIR_DST,
.max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
},
[HAL_RXDMA_MONITOR_BUF] = {
.start_ring_id = HAL_SRNG_SW2RXMON_BUF0,
.max_rings = 1,
.entry_size = sizeof(struct hal_mon_buf_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_PMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
},
[HAL_RXDMA_MONITOR_STATUS] = {
.start_ring_id = HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_STATBUF,
.max_rings = 1,
.entry_size = sizeof(struct hal_wbm_buffer_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_PMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
},
[HAL_RXDMA_MONITOR_DESC] = { 0, },
[HAL_RXDMA_DIR_BUF] = {
.start_ring_id = HAL_SRNG_RING_ID_RXDMA_DIR_BUF,
.max_rings = 2,
.entry_size = 8 >> 2, /* TODO: Define the struct */
.mac_type = ATH12K_HAL_SRNG_PMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
},
[HAL_PPE2TCL] = {
.start_ring_id = HAL_SRNG_RING_ID_PPE2TCL1,
.max_rings = 1,
.entry_size = sizeof(struct hal_tcl_entrance_from_ppe_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_PMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE,
},
[HAL_PPE_RELEASE] = {
.start_ring_id = HAL_SRNG_RING_ID_WBM_PPE_RELEASE,
.max_rings = 1,
.entry_size = sizeof(struct hal_wbm_release_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_PMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_WBM2PPE_RELEASE_RING_BASE_MSB_RING_SIZE,
},
[HAL_TX_MONITOR_BUF] = {
.start_ring_id = HAL_SRNG_RING_ID_WMAC1_SW2TXMON_BUF0,
.max_rings = 1,
.entry_size = sizeof(struct hal_mon_buf_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_PMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
},
[HAL_RXDMA_MONITOR_DST] = {
.start_ring_id = HAL_SRNG_RING_ID_WMAC1_SW2RXMON_BUF0,
.max_rings = 1,
.entry_size = sizeof(struct hal_mon_dest_desc) >> 2,
.mac_type = ATH12K_HAL_SRNG_PMAC,
.ring_dir = HAL_SRNG_DIR_DST,
.max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
},
[HAL_TX_MONITOR_DST] = {
.start_ring_id = HAL_SRNG_RING_ID_WMAC1_TXMON2SW0_BUF0,
.max_rings = 1,
.entry_size = sizeof(struct hal_mon_dest_desc) >> 2,
.mac_type = ATH12K_HAL_SRNG_PMAC,
.ring_dir = HAL_SRNG_DIR_DST,
.max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
}
};
static const struct ath12k_hal_tcl_to_wbm_rbm_map
const struct ath12k_hal_tcl_to_wbm_rbm_map
ath12k_hal_qcn9274_tcl_to_wbm_rbm_map[DP_TCL_NUM_RING_MAX] = {
{
.wbm_ring_num = 0,
@ -235,7 +32,7 @@ ath12k_hal_qcn9274_tcl_to_wbm_rbm_map[DP_TCL_NUM_RING_MAX] = {
}
};
static const struct ath12k_hal_tcl_to_wbm_rbm_map
const struct ath12k_hal_tcl_to_wbm_rbm_map
ath12k_hal_wcn7850_tcl_to_wbm_rbm_map[DP_TCL_NUM_RING_MAX] = {
{
.wbm_ring_num = 0,
@ -296,273 +93,6 @@ static unsigned int ath12k_hal_reo1_ring_misc_offset(struct ath12k_base *ab)
return HAL_REO1_RING_MISC(ab) - HAL_REO1_RING_BASE_LSB(ab);
}
static int ath12k_hal_srng_create_config_qcn9274(struct ath12k_base *ab)
{
struct ath12k_hal *hal = &ab->hal;
struct hal_srng_config *s;
hal->srng_config = kmemdup(hw_srng_config_template,
sizeof(hw_srng_config_template),
GFP_KERNEL);
if (!hal->srng_config)
return -ENOMEM;
s = &hal->srng_config[HAL_REO_DST];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_HP;
s->reg_size[0] = HAL_REO2_RING_BASE_LSB(ab) - HAL_REO1_RING_BASE_LSB(ab);
s->reg_size[1] = HAL_REO2_RING_HP - HAL_REO1_RING_HP;
s = &hal->srng_config[HAL_REO_EXCEPTION];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_SW0_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_SW0_RING_HP;
s = &hal->srng_config[HAL_REO_REINJECT];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_HP;
s->reg_size[0] = HAL_SW2REO1_RING_BASE_LSB(ab) - HAL_SW2REO_RING_BASE_LSB(ab);
s->reg_size[1] = HAL_SW2REO1_RING_HP - HAL_SW2REO_RING_HP;
s = &hal->srng_config[HAL_REO_CMD];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_HP;
s = &hal->srng_config[HAL_REO_STATUS];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_HP;
s = &hal->srng_config[HAL_TCL_DATA];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_HP;
s->reg_size[0] = HAL_TCL2_RING_BASE_LSB(ab) - HAL_TCL1_RING_BASE_LSB(ab);
s->reg_size[1] = HAL_TCL2_RING_HP - HAL_TCL1_RING_HP;
s = &hal->srng_config[HAL_TCL_CMD];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_HP;
s = &hal->srng_config[HAL_TCL_STATUS];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_HP;
s = &hal->srng_config[HAL_CE_SRC];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) + HAL_CE_DST_RING_BASE_LSB;
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) + HAL_CE_DST_RING_HP;
s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(ab) -
HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab);
s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(ab) -
HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab);
s = &hal->srng_config[HAL_CE_DST];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_RING_BASE_LSB;
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_RING_HP;
s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) -
HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab);
s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) -
HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab);
s = &hal->srng_config[HAL_CE_DST_STATUS];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) +
HAL_CE_DST_STATUS_RING_BASE_LSB;
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_STATUS_RING_HP;
s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) -
HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab);
s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) -
HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab);
s = &hal->srng_config[HAL_WBM_IDLE_LINK];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_HP;
s = &hal->srng_config[HAL_SW2WBM_RELEASE];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG +
HAL_WBM_SW_RELEASE_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SW_RELEASE_RING_HP;
s->reg_size[0] = HAL_WBM_SW1_RELEASE_RING_BASE_LSB(ab) -
HAL_WBM_SW_RELEASE_RING_BASE_LSB(ab);
s->reg_size[1] = HAL_WBM_SW1_RELEASE_RING_HP - HAL_WBM_SW_RELEASE_RING_HP;
s = &hal->srng_config[HAL_WBM2SW_RELEASE];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_HP;
s->reg_size[0] = HAL_WBM1_RELEASE_RING_BASE_LSB(ab) -
HAL_WBM0_RELEASE_RING_BASE_LSB(ab);
s->reg_size[1] = HAL_WBM1_RELEASE_RING_HP - HAL_WBM0_RELEASE_RING_HP;
/* Some LMAC rings are not accessed from the host:
* RXDMA_BUG, RXDMA_DST, RXDMA_MONITOR_BUF, RXDMA_MONITOR_STATUS,
* RXDMA_MONITOR_DST, RXDMA_MONITOR_DESC, RXDMA_DIR_BUF_SRC,
* RXDMA_RX_MONITOR_BUF, TX_MONITOR_BUF, TX_MONITOR_DST, SW2RXDMA
*/
s = &hal->srng_config[HAL_PPE2TCL];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_PPE2TCL1_RING_BASE_LSB;
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_PPE2TCL1_RING_HP;
s = &hal->srng_config[HAL_PPE_RELEASE];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG +
HAL_WBM_PPE_RELEASE_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_PPE_RELEASE_RING_HP;
return 0;
}
const struct hal_ops hal_qcn9274_ops = {
.create_srng_config = ath12k_hal_srng_create_config_qcn9274,
.tcl_to_wbm_rbm_map = ath12k_hal_qcn9274_tcl_to_wbm_rbm_map,
.rx_desc_set_msdu_len = ath12k_hal_rx_desc_set_msdu_len_qcn9274,
.rx_desc_get_dot11_hdr = ath12k_hal_rx_desc_get_dot11_hdr_qcn9274,
.rx_desc_get_crypto_header = ath12k_hal_rx_desc_get_crypto_hdr_qcn9274,
.rx_desc_copy_end_tlv = ath12k_hal_rx_desc_copy_end_tlv_qcn9274,
.rx_desc_get_msdu_src_link_id = ath12k_hal_rx_desc_get_msdu_src_link_qcn9274,
.extract_rx_desc_data = ath12k_hal_extract_rx_desc_data_qcn9274,
.rx_desc_get_desc_size = ath12k_hal_get_rx_desc_size_qcn9274,
.rx_desc_get_l3_pad_bytes = ath12k_hal_rx_desc_get_l3_pad_bytes_qcn9274,
.rx_desc_get_mpdu_ppdu_id = ath12k_hal_rx_desc_get_mpdu_ppdu_id_qcn9274,
.rx_desc_get_msdu_payload = ath12k_hal_rx_desc_get_msdu_payload_qcn9274,
};
EXPORT_SYMBOL(hal_qcn9274_ops);
static int ath12k_hal_srng_create_config_wcn7850(struct ath12k_base *ab)
{
struct ath12k_hal *hal = &ab->hal;
struct hal_srng_config *s;
hal->srng_config = kmemdup(hw_srng_config_template,
sizeof(hw_srng_config_template),
GFP_KERNEL);
if (!hal->srng_config)
return -ENOMEM;
s = &hal->srng_config[HAL_REO_DST];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_HP;
s->reg_size[0] = HAL_REO2_RING_BASE_LSB(ab) - HAL_REO1_RING_BASE_LSB(ab);
s->reg_size[1] = HAL_REO2_RING_HP - HAL_REO1_RING_HP;
s = &hal->srng_config[HAL_REO_EXCEPTION];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_SW0_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_SW0_RING_HP;
s = &hal->srng_config[HAL_REO_REINJECT];
s->max_rings = 1;
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_HP;
s = &hal->srng_config[HAL_REO_CMD];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_HP;
s = &hal->srng_config[HAL_REO_STATUS];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_HP;
s = &hal->srng_config[HAL_TCL_DATA];
s->max_rings = 5;
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_HP;
s->reg_size[0] = HAL_TCL2_RING_BASE_LSB(ab) - HAL_TCL1_RING_BASE_LSB(ab);
s->reg_size[1] = HAL_TCL2_RING_HP - HAL_TCL1_RING_HP;
s = &hal->srng_config[HAL_TCL_CMD];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_HP;
s = &hal->srng_config[HAL_TCL_STATUS];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_HP;
s = &hal->srng_config[HAL_CE_SRC];
s->max_rings = 12;
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) + HAL_CE_DST_RING_BASE_LSB;
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) + HAL_CE_DST_RING_HP;
s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(ab) -
HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab);
s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(ab) -
HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab);
s = &hal->srng_config[HAL_CE_DST];
s->max_rings = 12;
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_RING_BASE_LSB;
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_RING_HP;
s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) -
HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab);
s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) -
HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab);
s = &hal->srng_config[HAL_CE_DST_STATUS];
s->max_rings = 12;
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) +
HAL_CE_DST_STATUS_RING_BASE_LSB;
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_STATUS_RING_HP;
s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) -
HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab);
s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) -
HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab);
s = &hal->srng_config[HAL_WBM_IDLE_LINK];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_HP;
s = &hal->srng_config[HAL_SW2WBM_RELEASE];
s->max_rings = 1;
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG +
HAL_WBM_SW_RELEASE_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SW_RELEASE_RING_HP;
s = &hal->srng_config[HAL_WBM2SW_RELEASE];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_HP;
s->reg_size[0] = HAL_WBM1_RELEASE_RING_BASE_LSB(ab) -
HAL_WBM0_RELEASE_RING_BASE_LSB(ab);
s->reg_size[1] = HAL_WBM1_RELEASE_RING_HP - HAL_WBM0_RELEASE_RING_HP;
s = &hal->srng_config[HAL_RXDMA_BUF];
s->max_rings = 2;
s->mac_type = ATH12K_HAL_SRNG_PMAC;
s = &hal->srng_config[HAL_RXDMA_DST];
s->max_rings = 1;
s->entry_size = sizeof(struct hal_reo_entrance_ring) >> 2;
/* below rings are not used */
s = &hal->srng_config[HAL_RXDMA_DIR_BUF];
s->max_rings = 0;
s = &hal->srng_config[HAL_PPE2TCL];
s->max_rings = 0;
s = &hal->srng_config[HAL_PPE_RELEASE];
s->max_rings = 0;
s = &hal->srng_config[HAL_TX_MONITOR_BUF];
s->max_rings = 0;
s = &hal->srng_config[HAL_TX_MONITOR_DST];
s->max_rings = 0;
s = &hal->srng_config[HAL_PPE2TCL];
s->max_rings = 0;
return 0;
}
const struct hal_ops hal_wcn7850_ops = {
.create_srng_config = ath12k_hal_srng_create_config_wcn7850,
.tcl_to_wbm_rbm_map = ath12k_hal_wcn7850_tcl_to_wbm_rbm_map,
.rx_desc_set_msdu_len = ath12k_hal_rx_desc_set_msdu_len_wcn7850,
.rx_desc_get_dot11_hdr = ath12k_hal_rx_desc_get_dot11_hdr_wcn7850,
.rx_desc_get_crypto_header = ath12k_hal_rx_desc_get_crypto_hdr_wcn7850,
.rx_desc_copy_end_tlv = ath12k_hal_rx_desc_copy_end_tlv_wcn7850,
.rx_desc_get_msdu_src_link_id = ath12k_hal_rx_desc_get_msdu_src_link_wcn7850,
.extract_rx_desc_data = ath12k_hal_extract_rx_desc_data_wcn7850,
.rx_desc_get_desc_size = ath12k_hal_get_rx_desc_size_wcn7850,
.rx_desc_get_l3_pad_bytes = ath12k_hal_rx_desc_get_l3_pad_bytes_wcn7850,
.rx_desc_get_mpdu_start_tag = ath12k_hal_rx_desc_get_mpdu_start_tag_wcn7850,
.rx_desc_get_mpdu_ppdu_id = ath12k_hal_rx_desc_get_mpdu_ppdu_id_wcn7850,
.rx_desc_get_msdu_payload = ath12k_hal_rx_desc_get_msdu_payload_wcn7850,
};
EXPORT_SYMBOL(hal_wcn7850_ops);
static int ath12k_hal_alloc_cont_rdp(struct ath12k_base *ab)
{
struct ath12k_hal *hal = &ab->hal;

329
drivers/net/wireless/ath/ath12k/wifi7/hal_qcn9274.c
View File

@ -6,6 +6,209 @@
#include "hal_desc.h"
#include "hal_qcn9274.h"
static const struct hal_srng_config hw_srng_config_template[] = {
/* TODO: max_rings can populated by querying HW capabilities */
[HAL_REO_DST] = {
.start_ring_id = HAL_SRNG_RING_ID_REO2SW1,
.max_rings = 8,
.entry_size = sizeof(struct hal_reo_dest_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_DST,
.max_size = HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE,
},
[HAL_REO_EXCEPTION] = {
/* Designating REO2SW0 ring as exception ring.
* Any of theREO2SW rings can be used as exception ring.
*/
.start_ring_id = HAL_SRNG_RING_ID_REO2SW0,
.max_rings = 1,
.entry_size = sizeof(struct hal_reo_dest_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_DST,
.max_size = HAL_REO_REO2SW0_RING_BASE_MSB_RING_SIZE,
},
[HAL_REO_REINJECT] = {
.start_ring_id = HAL_SRNG_RING_ID_SW2REO,
.max_rings = 4,
.entry_size = sizeof(struct hal_reo_entrance_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE,
},
[HAL_REO_CMD] = {
.start_ring_id = HAL_SRNG_RING_ID_REO_CMD,
.max_rings = 1,
.entry_size = (sizeof(struct hal_tlv_64_hdr) +
sizeof(struct hal_reo_get_queue_stats)) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_REO_CMD_RING_BASE_MSB_RING_SIZE,
},
[HAL_REO_STATUS] = {
.start_ring_id = HAL_SRNG_RING_ID_REO_STATUS,
.max_rings = 1,
.entry_size = (sizeof(struct hal_tlv_64_hdr) +
sizeof(struct hal_reo_get_queue_stats_status)) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_DST,
.max_size = HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE,
},
[HAL_TCL_DATA] = {
.start_ring_id = HAL_SRNG_RING_ID_SW2TCL1,
.max_rings = 6,
.entry_size = sizeof(struct hal_tcl_data_cmd) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE,
},
[HAL_TCL_CMD] = {
.start_ring_id = HAL_SRNG_RING_ID_SW2TCL_CMD,
.max_rings = 1,
.entry_size = sizeof(struct hal_tcl_gse_cmd) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE,
},
[HAL_TCL_STATUS] = {
.start_ring_id = HAL_SRNG_RING_ID_TCL_STATUS,
.max_rings = 1,
.entry_size = (sizeof(struct hal_tlv_hdr) +
sizeof(struct hal_tcl_status_ring)) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_DST,
.max_size = HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE,
},
[HAL_CE_SRC] = {
.start_ring_id = HAL_SRNG_RING_ID_CE0_SRC,
.max_rings = 16,
.entry_size = sizeof(struct hal_ce_srng_src_desc) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_CE_SRC_RING_BASE_MSB_RING_SIZE,
},
[HAL_CE_DST] = {
.start_ring_id = HAL_SRNG_RING_ID_CE0_DST,
.max_rings = 16,
.entry_size = sizeof(struct hal_ce_srng_dest_desc) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_CE_DST_RING_BASE_MSB_RING_SIZE,
},
[HAL_CE_DST_STATUS] = {
.start_ring_id = HAL_SRNG_RING_ID_CE0_DST_STATUS,
.max_rings = 16,
.entry_size = sizeof(struct hal_ce_srng_dst_status_desc) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_DST,
.max_size = HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE,
},
[HAL_WBM_IDLE_LINK] = {
.start_ring_id = HAL_SRNG_RING_ID_WBM_IDLE_LINK,
.max_rings = 1,
.entry_size = sizeof(struct hal_wbm_link_desc) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE,
},
[HAL_SW2WBM_RELEASE] = {
.start_ring_id = HAL_SRNG_RING_ID_WBM_SW0_RELEASE,
.max_rings = 2,
.entry_size = sizeof(struct hal_wbm_release_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE,
},
[HAL_WBM2SW_RELEASE] = {
.start_ring_id = HAL_SRNG_RING_ID_WBM2SW0_RELEASE,
.max_rings = 8,
.entry_size = sizeof(struct hal_wbm_release_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_DST,
.max_size = HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE,
},
[HAL_RXDMA_BUF] = {
.start_ring_id = HAL_SRNG_SW2RXDMA_BUF0,
.max_rings = 1,
.entry_size = sizeof(struct hal_wbm_buffer_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_DMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
},
[HAL_RXDMA_DST] = {
.start_ring_id = HAL_SRNG_RING_ID_WMAC1_RXDMA2SW0,
.max_rings = 0,
.entry_size = 0,
.mac_type = ATH12K_HAL_SRNG_PMAC,
.ring_dir = HAL_SRNG_DIR_DST,
.max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
},
[HAL_RXDMA_MONITOR_BUF] = {
.start_ring_id = HAL_SRNG_SW2RXMON_BUF0,
.max_rings = 1,
.entry_size = sizeof(struct hal_mon_buf_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_PMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
},
[HAL_RXDMA_MONITOR_STATUS] = {
.start_ring_id = HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_STATBUF,
.max_rings = 1,
.entry_size = sizeof(struct hal_wbm_buffer_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_PMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
},
[HAL_RXDMA_MONITOR_DESC] = { 0, },
[HAL_RXDMA_DIR_BUF] = {
.start_ring_id = HAL_SRNG_RING_ID_RXDMA_DIR_BUF,
.max_rings = 2,
.entry_size = 8 >> 2, /* TODO: Define the struct */
.mac_type = ATH12K_HAL_SRNG_PMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
},
[HAL_PPE2TCL] = {
.start_ring_id = HAL_SRNG_RING_ID_PPE2TCL1,
.max_rings = 1,
.entry_size = sizeof(struct hal_tcl_entrance_from_ppe_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_PMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE,
},
[HAL_PPE_RELEASE] = {
.start_ring_id = HAL_SRNG_RING_ID_WBM_PPE_RELEASE,
.max_rings = 1,
.entry_size = sizeof(struct hal_wbm_release_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_PMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_WBM2PPE_RELEASE_RING_BASE_MSB_RING_SIZE,
},
[HAL_TX_MONITOR_BUF] = {
.start_ring_id = HAL_SRNG_RING_ID_WMAC1_SW2TXMON_BUF0,
.max_rings = 1,
.entry_size = sizeof(struct hal_mon_buf_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_PMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
},
[HAL_RXDMA_MONITOR_DST] = {
.start_ring_id = HAL_SRNG_RING_ID_WMAC1_SW2RXMON_BUF0,
.max_rings = 1,
.entry_size = sizeof(struct hal_mon_dest_desc) >> 2,
.mac_type = ATH12K_HAL_SRNG_PMAC,
.ring_dir = HAL_SRNG_DIR_DST,
.max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
},
[HAL_TX_MONITOR_DST] = {
.start_ring_id = HAL_SRNG_RING_ID_WMAC1_TXMON2SW0_BUF0,
.max_rings = 1,
.entry_size = sizeof(struct hal_mon_dest_desc) >> 2,
.mac_type = ATH12K_HAL_SRNG_PMAC,
.ring_dir = HAL_SRNG_DIR_DST,
.max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
}
};
static inline
bool ath12k_hal_rx_desc_get_first_msdu_qcn9274(struct hal_rx_desc *desc)
{
@ -367,3 +570,129 @@ void ath12k_hal_extract_rx_desc_data_qcn9274(struct hal_rx_desc_data *rx_desc_da
rx_desc_data->is_decrypted = ath12k_hal_rx_h_is_decrypted_qcn9274(rx_desc);
rx_desc_data->err_bitmap = ath12k_hal_rx_h_mpdu_err_qcn9274(rx_desc);
}
static int ath12k_hal_srng_create_config_qcn9274(struct ath12k_base *ab)
{
struct ath12k_hal *hal = &ab->hal;
struct hal_srng_config *s;
hal->srng_config = kmemdup(hw_srng_config_template,
sizeof(hw_srng_config_template),
GFP_KERNEL);
if (!hal->srng_config)
return -ENOMEM;
s = &hal->srng_config[HAL_REO_DST];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_HP;
s->reg_size[0] = HAL_REO2_RING_BASE_LSB(ab) - HAL_REO1_RING_BASE_LSB(ab);
s->reg_size[1] = HAL_REO2_RING_HP - HAL_REO1_RING_HP;
s = &hal->srng_config[HAL_REO_EXCEPTION];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_SW0_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_SW0_RING_HP;
s = &hal->srng_config[HAL_REO_REINJECT];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_HP;
s->reg_size[0] = HAL_SW2REO1_RING_BASE_LSB(ab) - HAL_SW2REO_RING_BASE_LSB(ab);
s->reg_size[1] = HAL_SW2REO1_RING_HP - HAL_SW2REO_RING_HP;
s = &hal->srng_config[HAL_REO_CMD];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_HP;
s = &hal->srng_config[HAL_REO_STATUS];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_HP;
s = &hal->srng_config[HAL_TCL_DATA];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_HP;
s->reg_size[0] = HAL_TCL2_RING_BASE_LSB(ab) - HAL_TCL1_RING_BASE_LSB(ab);
s->reg_size[1] = HAL_TCL2_RING_HP - HAL_TCL1_RING_HP;
s = &hal->srng_config[HAL_TCL_CMD];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_HP;
s = &hal->srng_config[HAL_TCL_STATUS];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_HP;
s = &hal->srng_config[HAL_CE_SRC];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) + HAL_CE_DST_RING_BASE_LSB;
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) + HAL_CE_DST_RING_HP;
s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(ab) -
HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab);
s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(ab) -
HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab);
s = &hal->srng_config[HAL_CE_DST];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_RING_BASE_LSB;
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_RING_HP;
s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) -
HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab);
s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) -
HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab);
s = &hal->srng_config[HAL_CE_DST_STATUS];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) +
HAL_CE_DST_STATUS_RING_BASE_LSB;
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_STATUS_RING_HP;
s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) -
HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab);
s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) -
HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab);
s = &hal->srng_config[HAL_WBM_IDLE_LINK];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_HP;
s = &hal->srng_config[HAL_SW2WBM_RELEASE];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG +
HAL_WBM_SW_RELEASE_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SW_RELEASE_RING_HP;
s->reg_size[0] = HAL_WBM_SW1_RELEASE_RING_BASE_LSB(ab) -
HAL_WBM_SW_RELEASE_RING_BASE_LSB(ab);
s->reg_size[1] = HAL_WBM_SW1_RELEASE_RING_HP - HAL_WBM_SW_RELEASE_RING_HP;
s = &hal->srng_config[HAL_WBM2SW_RELEASE];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_HP;
s->reg_size[0] = HAL_WBM1_RELEASE_RING_BASE_LSB(ab) -
HAL_WBM0_RELEASE_RING_BASE_LSB(ab);
s->reg_size[1] = HAL_WBM1_RELEASE_RING_HP - HAL_WBM0_RELEASE_RING_HP;
/* Some LMAC rings are not accessed from the host:
* RXDMA_BUG, RXDMA_DST, RXDMA_MONITOR_BUF, RXDMA_MONITOR_STATUS,
* RXDMA_MONITOR_DST, RXDMA_MONITOR_DESC, RXDMA_DIR_BUF_SRC,
* RXDMA_RX_MONITOR_BUF, TX_MONITOR_BUF, TX_MONITOR_DST, SW2RXDMA
*/
s = &hal->srng_config[HAL_PPE2TCL];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_PPE2TCL1_RING_BASE_LSB;
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_PPE2TCL1_RING_HP;
s = &hal->srng_config[HAL_PPE_RELEASE];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG +
HAL_WBM_PPE_RELEASE_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_PPE_RELEASE_RING_HP;
return 0;
}
const struct hal_ops hal_qcn9274_ops = {
.create_srng_config = ath12k_hal_srng_create_config_qcn9274,
.tcl_to_wbm_rbm_map = ath12k_hal_qcn9274_tcl_to_wbm_rbm_map,
.rx_desc_set_msdu_len = ath12k_hal_rx_desc_set_msdu_len_qcn9274,
.rx_desc_get_dot11_hdr = ath12k_hal_rx_desc_get_dot11_hdr_qcn9274,
.rx_desc_get_crypto_header = ath12k_hal_rx_desc_get_crypto_hdr_qcn9274,
.rx_desc_copy_end_tlv = ath12k_hal_rx_desc_copy_end_tlv_qcn9274,
.rx_desc_get_msdu_src_link_id = ath12k_hal_rx_desc_get_msdu_src_link_qcn9274,
.extract_rx_desc_data = ath12k_hal_extract_rx_desc_data_qcn9274,
.rx_desc_get_desc_size = ath12k_hal_get_rx_desc_size_qcn9274,
.rx_desc_get_l3_pad_bytes = ath12k_hal_rx_desc_get_l3_pad_bytes_qcn9274,
.rx_desc_get_mpdu_ppdu_id = ath12k_hal_rx_desc_get_mpdu_ppdu_id_qcn9274,
.rx_desc_get_msdu_payload = ath12k_hal_rx_desc_get_msdu_payload_qcn9274,
};
EXPORT_SYMBOL(hal_qcn9274_ops);

3
drivers/net/wireless/ath/ath12k/wifi7/hal_qcn9274.h
View File

@ -12,6 +12,9 @@
#include "../hal.h"
#include "hal_rx.h"
extern const struct ath12k_hal_tcl_to_wbm_rbm_map
ath12k_hal_qcn9274_tcl_to_wbm_rbm_map[DP_TCL_NUM_RING_MAX];
u8 ath12k_hal_rx_desc_get_l3_pad_bytes_qcn9274(struct hal_rx_desc *desc);
void ath12k_hal_rx_desc_copy_end_tlv_qcn9274(struct hal_rx_desc *fdesc,
struct hal_rx_desc *ldesc);

344
drivers/net/wireless/ath/ath12k/wifi7/hal_wcn7850.c
View File

@ -7,6 +7,209 @@
#include "hal_desc.h"
#include "hal_wcn7850.h"
static const struct hal_srng_config hw_srng_config_template[] = {
/* TODO: max_rings can populated by querying HW capabilities */
[HAL_REO_DST] = {
.start_ring_id = HAL_SRNG_RING_ID_REO2SW1,
.max_rings = 8,
.entry_size = sizeof(struct hal_reo_dest_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_DST,
.max_size = HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE,
},
[HAL_REO_EXCEPTION] = {
/* Designating REO2SW0 ring as exception ring.
* Any of theREO2SW rings can be used as exception ring.
*/
.start_ring_id = HAL_SRNG_RING_ID_REO2SW0,
.max_rings = 1,
.entry_size = sizeof(struct hal_reo_dest_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_DST,
.max_size = HAL_REO_REO2SW0_RING_BASE_MSB_RING_SIZE,
},
[HAL_REO_REINJECT] = {
.start_ring_id = HAL_SRNG_RING_ID_SW2REO,
.max_rings = 4,
.entry_size = sizeof(struct hal_reo_entrance_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE,
},
[HAL_REO_CMD] = {
.start_ring_id = HAL_SRNG_RING_ID_REO_CMD,
.max_rings = 1,
.entry_size = (sizeof(struct hal_tlv_64_hdr) +
sizeof(struct hal_reo_get_queue_stats)) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_REO_CMD_RING_BASE_MSB_RING_SIZE,
},
[HAL_REO_STATUS] = {
.start_ring_id = HAL_SRNG_RING_ID_REO_STATUS,
.max_rings = 1,
.entry_size = (sizeof(struct hal_tlv_64_hdr) +
sizeof(struct hal_reo_get_queue_stats_status)) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_DST,
.max_size = HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE,
},
[HAL_TCL_DATA] = {
.start_ring_id = HAL_SRNG_RING_ID_SW2TCL1,
.max_rings = 6,
.entry_size = sizeof(struct hal_tcl_data_cmd) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE,
},
[HAL_TCL_CMD] = {
.start_ring_id = HAL_SRNG_RING_ID_SW2TCL_CMD,
.max_rings = 1,
.entry_size = sizeof(struct hal_tcl_gse_cmd) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE,
},
[HAL_TCL_STATUS] = {
.start_ring_id = HAL_SRNG_RING_ID_TCL_STATUS,
.max_rings = 1,
.entry_size = (sizeof(struct hal_tlv_hdr) +
sizeof(struct hal_tcl_status_ring)) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_DST,
.max_size = HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE,
},
[HAL_CE_SRC] = {
.start_ring_id = HAL_SRNG_RING_ID_CE0_SRC,
.max_rings = 16,
.entry_size = sizeof(struct hal_ce_srng_src_desc) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_CE_SRC_RING_BASE_MSB_RING_SIZE,
},
[HAL_CE_DST] = {
.start_ring_id = HAL_SRNG_RING_ID_CE0_DST,
.max_rings = 16,
.entry_size = sizeof(struct hal_ce_srng_dest_desc) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_CE_DST_RING_BASE_MSB_RING_SIZE,
},
[HAL_CE_DST_STATUS] = {
.start_ring_id = HAL_SRNG_RING_ID_CE0_DST_STATUS,
.max_rings = 16,
.entry_size = sizeof(struct hal_ce_srng_dst_status_desc) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_DST,
.max_size = HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE,
},
[HAL_WBM_IDLE_LINK] = {
.start_ring_id = HAL_SRNG_RING_ID_WBM_IDLE_LINK,
.max_rings = 1,
.entry_size = sizeof(struct hal_wbm_link_desc) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE,
},
[HAL_SW2WBM_RELEASE] = {
.start_ring_id = HAL_SRNG_RING_ID_WBM_SW0_RELEASE,
.max_rings = 2,
.entry_size = sizeof(struct hal_wbm_release_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE,
},
[HAL_WBM2SW_RELEASE] = {
.start_ring_id = HAL_SRNG_RING_ID_WBM2SW0_RELEASE,
.max_rings = 8,
.entry_size = sizeof(struct hal_wbm_release_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_UMAC,
.ring_dir = HAL_SRNG_DIR_DST,
.max_size = HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE,
},
[HAL_RXDMA_BUF] = {
.start_ring_id = HAL_SRNG_SW2RXDMA_BUF0,
.max_rings = 1,
.entry_size = sizeof(struct hal_wbm_buffer_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_DMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
},
[HAL_RXDMA_DST] = {
.start_ring_id = HAL_SRNG_RING_ID_WMAC1_RXDMA2SW0,
.max_rings = 0,
.entry_size = 0,
.mac_type = ATH12K_HAL_SRNG_PMAC,
.ring_dir = HAL_SRNG_DIR_DST,
.max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
},
[HAL_RXDMA_MONITOR_BUF] = {
.start_ring_id = HAL_SRNG_SW2RXMON_BUF0,
.max_rings = 1,
.entry_size = sizeof(struct hal_mon_buf_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_PMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
},
[HAL_RXDMA_MONITOR_STATUS] = {
.start_ring_id = HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_STATBUF,
.max_rings = 1,
.entry_size = sizeof(struct hal_wbm_buffer_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_PMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
},
[HAL_RXDMA_MONITOR_DESC] = { 0, },
[HAL_RXDMA_DIR_BUF] = {
.start_ring_id = HAL_SRNG_RING_ID_RXDMA_DIR_BUF,
.max_rings = 2,
.entry_size = 8 >> 2, /* TODO: Define the struct */
.mac_type = ATH12K_HAL_SRNG_PMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
},
[HAL_PPE2TCL] = {
.start_ring_id = HAL_SRNG_RING_ID_PPE2TCL1,
.max_rings = 1,
.entry_size = sizeof(struct hal_tcl_entrance_from_ppe_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_PMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE,
},
[HAL_PPE_RELEASE] = {
.start_ring_id = HAL_SRNG_RING_ID_WBM_PPE_RELEASE,
.max_rings = 1,
.entry_size = sizeof(struct hal_wbm_release_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_PMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_WBM2PPE_RELEASE_RING_BASE_MSB_RING_SIZE,
},
[HAL_TX_MONITOR_BUF] = {
.start_ring_id = HAL_SRNG_RING_ID_WMAC1_SW2TXMON_BUF0,
.max_rings = 1,
.entry_size = sizeof(struct hal_mon_buf_ring) >> 2,
.mac_type = ATH12K_HAL_SRNG_PMAC,
.ring_dir = HAL_SRNG_DIR_SRC,
.max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
},
[HAL_RXDMA_MONITOR_DST] = {
.start_ring_id = HAL_SRNG_RING_ID_WMAC1_SW2RXMON_BUF0,
.max_rings = 1,
.entry_size = sizeof(struct hal_mon_dest_desc) >> 2,
.mac_type = ATH12K_HAL_SRNG_PMAC,
.ring_dir = HAL_SRNG_DIR_DST,
.max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
},
[HAL_TX_MONITOR_DST] = {
.start_ring_id = HAL_SRNG_RING_ID_WMAC1_TXMON2SW0_BUF0,
.max_rings = 1,
.entry_size = sizeof(struct hal_mon_dest_desc) >> 2,
.mac_type = ATH12K_HAL_SRNG_PMAC,
.ring_dir = HAL_SRNG_DIR_DST,
.max_size = HAL_RXDMA_RING_MAX_SIZE_BE,
}
};
static inline
bool ath12k_hal_rx_desc_get_first_msdu_wcn7850(struct hal_rx_desc *desc)
{
@ -362,3 +565,144 @@ void ath12k_hal_extract_rx_desc_data_wcn7850(struct hal_rx_desc_data *rx_desc_da
rx_desc_data->is_decrypted = ath12k_hal_rx_h_is_decrypted_wcn7850(rx_desc);
rx_desc_data->err_bitmap = ath12k_hal_rx_h_mpdu_err_wcn7850(rx_desc);
}
static int ath12k_hal_srng_create_config_wcn7850(struct ath12k_base *ab)
{
struct ath12k_hal *hal = &ab->hal;
struct hal_srng_config *s;
hal->srng_config = kmemdup(hw_srng_config_template,
sizeof(hw_srng_config_template),
GFP_KERNEL);
if (!hal->srng_config)
return -ENOMEM;
s = &hal->srng_config[HAL_REO_DST];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_HP;
s->reg_size[0] = HAL_REO2_RING_BASE_LSB(ab) - HAL_REO1_RING_BASE_LSB(ab);
s->reg_size[1] = HAL_REO2_RING_HP - HAL_REO1_RING_HP;
s = &hal->srng_config[HAL_REO_EXCEPTION];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_SW0_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_SW0_RING_HP;
s = &hal->srng_config[HAL_REO_REINJECT];
s->max_rings = 1;
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_HP;
s = &hal->srng_config[HAL_REO_CMD];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_HP;
s = &hal->srng_config[HAL_REO_STATUS];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_HP;
s = &hal->srng_config[HAL_TCL_DATA];
s->max_rings = 5;
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_HP;
s->reg_size[0] = HAL_TCL2_RING_BASE_LSB(ab) - HAL_TCL1_RING_BASE_LSB(ab);
s->reg_size[1] = HAL_TCL2_RING_HP - HAL_TCL1_RING_HP;
s = &hal->srng_config[HAL_TCL_CMD];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_HP;
s = &hal->srng_config[HAL_TCL_STATUS];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_HP;
s = &hal->srng_config[HAL_CE_SRC];
s->max_rings = 12;
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) + HAL_CE_DST_RING_BASE_LSB;
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) + HAL_CE_DST_RING_HP;
s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(ab) -
HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab);
s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(ab) -
HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab);
s = &hal->srng_config[HAL_CE_DST];
s->max_rings = 12;
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_RING_BASE_LSB;
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_RING_HP;
s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) -
HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab);
s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) -
HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab);
s = &hal->srng_config[HAL_CE_DST_STATUS];
s->max_rings = 12;
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) +
HAL_CE_DST_STATUS_RING_BASE_LSB;
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_STATUS_RING_HP;
s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) -
HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab);
s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) -
HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab);
s = &hal->srng_config[HAL_WBM_IDLE_LINK];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_HP;
s = &hal->srng_config[HAL_SW2WBM_RELEASE];
s->max_rings = 1;
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG +
HAL_WBM_SW_RELEASE_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SW_RELEASE_RING_HP;
s = &hal->srng_config[HAL_WBM2SW_RELEASE];
s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_BASE_LSB(ab);
s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_HP;
s->reg_size[0] = HAL_WBM1_RELEASE_RING_BASE_LSB(ab) -
HAL_WBM0_RELEASE_RING_BASE_LSB(ab);
s->reg_size[1] = HAL_WBM1_RELEASE_RING_HP - HAL_WBM0_RELEASE_RING_HP;
s = &hal->srng_config[HAL_RXDMA_BUF];
s->max_rings = 2;
s->mac_type = ATH12K_HAL_SRNG_PMAC;
s = &hal->srng_config[HAL_RXDMA_DST];
s->max_rings = 1;
s->entry_size = sizeof(struct hal_reo_entrance_ring) >> 2;
/* below rings are not used */
s = &hal->srng_config[HAL_RXDMA_DIR_BUF];
s->max_rings = 0;
s = &hal->srng_config[HAL_PPE2TCL];
s->max_rings = 0;
s = &hal->srng_config[HAL_PPE_RELEASE];
s->max_rings = 0;
s = &hal->srng_config[HAL_TX_MONITOR_BUF];
s->max_rings = 0;
s = &hal->srng_config[HAL_TX_MONITOR_DST];
s->max_rings = 0;
s = &hal->srng_config[HAL_PPE2TCL];
s->max_rings = 0;
return 0;
}
const struct hal_ops hal_wcn7850_ops = {
.create_srng_config = ath12k_hal_srng_create_config_wcn7850,
.tcl_to_wbm_rbm_map = ath12k_hal_wcn7850_tcl_to_wbm_rbm_map,
.rx_desc_set_msdu_len = ath12k_hal_rx_desc_set_msdu_len_wcn7850,
.rx_desc_get_dot11_hdr = ath12k_hal_rx_desc_get_dot11_hdr_wcn7850,
.rx_desc_get_crypto_header = ath12k_hal_rx_desc_get_crypto_hdr_wcn7850,
.rx_desc_copy_end_tlv = ath12k_hal_rx_desc_copy_end_tlv_wcn7850,
.rx_desc_get_msdu_src_link_id = ath12k_hal_rx_desc_get_msdu_src_link_wcn7850,
.extract_rx_desc_data = ath12k_hal_extract_rx_desc_data_wcn7850,
.rx_desc_get_desc_size = ath12k_hal_get_rx_desc_size_wcn7850,
.rx_desc_get_l3_pad_bytes = ath12k_hal_rx_desc_get_l3_pad_bytes_wcn7850,
.rx_desc_get_mpdu_start_tag = ath12k_hal_rx_desc_get_mpdu_start_tag_wcn7850,
.rx_desc_get_mpdu_ppdu_id = ath12k_hal_rx_desc_get_mpdu_ppdu_id_wcn7850,
.rx_desc_get_msdu_payload = ath12k_hal_rx_desc_get_msdu_payload_wcn7850,
};
EXPORT_SYMBOL(hal_wcn7850_ops);

3
drivers/net/wireless/ath/ath12k/wifi7/hal_wcn7850.h
View File

@ -10,6 +10,9 @@
#include "../hal.h"
#include "hal_rx.h"
extern const struct ath12k_hal_tcl_to_wbm_rbm_map
ath12k_hal_wcn7850_tcl_to_wbm_rbm_map[DP_TCL_NUM_RING_MAX];
u8 ath12k_hal_rx_desc_get_l3_pad_bytes_wcn7850(struct hal_rx_desc *desc);
void ath12k_hal_rx_desc_copy_end_tlv_wcn7850(struct hal_rx_desc *fdesc,
struct hal_rx_desc *ldesc);