i.MX fixes for 6.5:

- A couple of ARM DTS fixes for i.MX6SLL usbphy and supported CPU
   frequency of sk-imx53 board
 - Add missing pull-up for imx8mn-var-som onboard PHY reset pinmux
 - A couple of imx8mm-venice fixes from Tim Harvey to diable disp_blk_ctrl
 - A couple of phycore-imx8mm fixes from Yashwanth Varakala to correct
   VPU label and gpio-line-names
 - Fix imx8mp-blk-ctrl driver to register HSIO PLL clock as bus_power_dev
   child, so that runtime PM can translate into the necessary GPC power
   domain action
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Merge tag 'imx-fixes-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes

i.MX fixes for 6.5:

- A couple of ARM DTS fixes for i.MX6SLL usbphy and supported CPU
  frequency of sk-imx53 board
- Add missing pull-up for imx8mn-var-som onboard PHY reset pinmux
- A couple of imx8mm-venice fixes from Tim Harvey to diable disp_blk_ctrl
- A couple of phycore-imx8mm fixes from Yashwanth Varakala to correct
  VPU label and gpio-line-names
- Fix imx8mp-blk-ctrl driver to register HSIO PLL clock as bus_power_dev
  child, so that runtime PM can translate into the necessary GPC power
  domain action

* tag 'imx-fixes-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  soc: imx: imx8mp-blk-ctrl: register HSIO PLL clock as bus_power_dev child
  ARM: dts: nxp/imx: limit sk-imx53 supported frequencies
  arm64: dts: freescale: Fix VPU G2 clock
  arm64: dts: imx8mn-var-som: add missing pull-up for onboard PHY reset pinmux
  arm64: dts: phycore-imx8mm: Correction in gpio-line-names
  arm64: dts: phycore-imx8mm: Label typo-fix of VPU
  ARM: dts: nxp/imx6sll: fix wrong property name in usbphy node
  arm64: dts: imx8mm-venice-gw7904: disable disp_blk_ctrl
  arm64: dts: imx8mm-venice-gw7903: disable disp_blk_ctrl

Link: https://lore.kernel.org/r/20230725075837.GR151430@dragon
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-07-27 15:40:33 +02:00
commit c05cfd71df
9 changed files with 25 additions and 7 deletions

View File

@ -60,6 +60,16 @@ &can1 {
status = "okay";
};
&cpu0 {
/* CPU rated to 800 MHz, not the default 1.2GHz. */
operating-points = <
/* kHz uV */
166666 850000
400000 900000
800000 1050000
>;
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;

View File

@ -552,7 +552,7 @@ usbphy2: usb-phy@20ca000 {
reg = <0x020ca000 0x1000>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_USBPHY2>;
phy-reg_3p0-supply = <&reg_3p0>;
phy-3p0-supply = <&reg_3p0>;
fsl,anatop = <&anatop>;
};

View File

@ -141,7 +141,7 @@ can0: can@0 {
};
&gpio1 {
gpio-line-names = "nINT_ETHPHY", "LED_RED", "WDOG_INT", "X_RTC_INT",
gpio-line-names = "", "LED_RED", "WDOG_INT", "X_RTC_INT",
"", "", "", "RESET_ETHPHY",
"CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "",
"USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE";

View File

@ -111,7 +111,7 @@ som_flash: flash@0 {
};
&gpio1 {
gpio-line-names = "nINT_ETHPHY", "", "WDOG_INT", "X_RTC_INT",
gpio-line-names = "", "", "WDOG_INT", "X_RTC_INT",
"", "", "", "RESET_ETHPHY",
"", "", "nENABLE_FLATLINK";
};
@ -210,7 +210,7 @@ regulator-state-mem {
};
};
reg_vdd_gpu: buck3 {
reg_vdd_vpu: buck3 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1000000>;

View File

@ -567,6 +567,10 @@ &pcie0 {
status = "okay";
};
&disp_blk_ctrl {
status = "disabled";
};
&pgc_mipi {
status = "disabled";
};

View File

@ -628,6 +628,10 @@ &pcie0 {
status = "okay";
};
&disp_blk_ctrl {
status = "disabled";
};
&pgc_mipi {
status = "disabled";
};

View File

@ -358,7 +358,7 @@ MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x159
>;
};

View File

@ -772,7 +772,7 @@ pgc_vpu: power-domain@6 {
<&clk IMX8MQ_SYS1_PLL_800M>,
<&clk IMX8MQ_VPU_PLL>;
assigned-clock-rates = <600000000>,
<600000000>,
<300000000>,
<800000000>,
<0>;
};

View File

@ -164,7 +164,7 @@ static int imx8mp_hsio_blk_ctrl_probe(struct imx8mp_blk_ctrl *bc)
clk_hsio_pll->hw.init = &init;
hw = &clk_hsio_pll->hw;
ret = devm_clk_hw_register(bc->dev, hw);
ret = devm_clk_hw_register(bc->bus_power_dev, hw);
if (ret)
return ret;