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pwm: Changes for v6.18-rc1

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The core highlights for this cycle are:
 
  - The pca9586 driver was converted to the waveform API.
  - Waveform drivers automatically provide a gpio chip to make PWMs
    usable as GPIOs. (The pca9586 driver did that in a driver specific
    implementation before.)
 
 Otherwise it's the usual mix of fixes and device tree and driver changes
 to support new hardware variants.
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Merge tag 'pwm/for-6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux

Pull pwm updates from Uwe Kleine-König:
 "The core highlights for this cycle are:

   - The pca9586 driver was converted to the waveform API

   - Waveform drivers automatically provide a gpio chip to make PWMs
     usable as GPIOs (The pca9586 driver did that in a driver specific
     implementation before)

  Otherwise it's the usual mix of fixes and device tree and driver
  changes to support new hardware variants"

* tag 'pwm/for-6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux: (30 commits)
  pwm: cros-ec: Avoid -Wflex-array-member-not-at-end warnings
  dt-bindings: pwm: samsung: add exynos8890 compatible
  dt-bindings: pwm: apple,s5l-fpwm: Add t6020-fpwm compatible
  dt-bindings: pwm: nxp,lpc1850-sct-pwm: Minor whitespace cleanup in example
  pwm: pca9586: Convert to waveform API
  pwm: pca9685: Drop GPIO support
  pwm: pca9685: Make use of register caching in regmap
  pwm: pca9685: Use bulk write to atomicially update registers
  pwm: pca9685: Don't disable hardware in .free()
  pwm: Add the S32G support in the Freescale FTM driver
  dt-bindings: pwm: fsl,vf610-ftm-pwm: Add compatible for s32g2 and s32g3
  pwm: mediatek: Lock and cache clock rate
  pwm: mediatek: Fix various issues in the .apply() callback
  pwm: mediatek: Implement .get_state() callback
  pwm: mediatek: Initialize clks when the hardware is enabled at probe time
  pwm: mediatek: Rework parameters for clk helper function
  pwm: mediatek: Introduce and use a few more register defines
  pwm: mediatek: Simplify representation of channel offsets
  pwm: tiecap: Document behaviour of hardware disable
  pwm: Provide a gpio device for waveform drivers
  ...
This commit is contained in:
Linus Torvalds 2025-10-01 10:33:17 -07:00
commit c050daf69f
16 changed files with 683 additions and 537 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml
View File

@ -17,8 +17,9 @@ properties:
items:
- enum:
- apple,t8103-fpwm
- apple,t6000-fpwm
- apple,t8112-fpwm
- apple,t6000-fpwm
- apple,t6020-fpwm
- const: apple,s5l-fpwm
reg:

11
Documentation/devicetree/bindings/pwm/fsl,vf610-ftm-pwm.yaml
View File

@ -26,9 +26,14 @@ maintainers:
properties:
compatible:
enum:
- fsl,vf610-ftm-pwm
- fsl,imx8qm-ftm-pwm
oneOf:
- enum:
- fsl,vf610-ftm-pwm
- fsl,imx8qm-ftm-pwm
- nxp,s32g2-ftm-pwm
- items:
- const: nxp,s32g3-ftm-pwm
- const: nxp,s32g2-ftm-pwm
reg:
maxItems: 1

2
Documentation/devicetree/bindings/pwm/nxp,lpc1850-sct-pwm.yaml
View File

@ -48,7 +48,7 @@ examples:
pwm@40000000 {
compatible = "nxp,lpc1850-sct-pwm";
reg = <0x40000000 0x1000>;
clocks =<&ccu1 CLK_CPU_SCT>;
clocks = <&ccu1 CLK_CPU_SCT>;
clock-names = "pwm";
#pwm-cells = <3>;
};

1
Documentation/devicetree/bindings/pwm/pwm-samsung.yaml
View File

@ -31,6 +31,7 @@ properties:
- enum:
- samsung,exynos5433-pwm
- samsung,exynos7-pwm
- samsung,exynos8890-pwm
- samsung,exynosautov9-pwm
- samsung,exynosautov920-pwm
- tesla,fsd-pwm

7
Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
View File

@ -221,7 +221,10 @@ properties:
maxItems: 1
"#pwm-cells":
const: 2
oneOf:
- const: 2
deprecated: true
- const: 3
required:
- compatible
@ -299,5 +302,5 @@ examples:
clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
power-domains = <&cpg>;
resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
#pwm-cells = <2>;
#pwm-cells = <3>;
};

9
drivers/pwm/Kconfig
View File

@ -38,6 +38,15 @@ config PWM_DEBUG
It is expected to introduce some runtime overhead and diagnostic
output to the kernel log, so only enable while working on a driver.
config PWM_PROVIDE_GPIO
bool "Provide a GPIO chip for each PWM chip"
depends on GPIOLIB
help
Most PWMs can emit both a constant active high and a constant active
low signal and so they can be used as GPIO. Say Y here to let each
PWM chip provide a GPIO chip and so be easily plugged into consumers
that know how to handle GPIOs but not PWMs.
config PWM_AB8500
tristate "AB8500 PWM support"
depends on AB8500_CORE && ARCH_U8500

108
drivers/pwm/core.c
View File

@ -276,7 +276,7 @@ int pwm_round_waveform_might_sleep(struct pwm_device *pwm, struct pwm_waveform *
if (IS_ENABLED(CONFIG_PWM_DEBUG) && ret_fromhw > 0)
dev_err(&chip->dev, "Unexpected return value from __pwm_round_waveform_fromhw: requested %llu/%llu [+%llu], return value %d\n",
wf_req.duty_length_ns, wf_req.period_length_ns, wf_req.duty_offset_ns, ret_tohw);
wf_req.duty_length_ns, wf_req.period_length_ns, wf_req.duty_offset_ns, ret_fromhw);
if (IS_ENABLED(CONFIG_PWM_DEBUG) &&
(ret_tohw == 0) != pwm_check_rounding(&wf_req, wf))
@ -496,6 +496,13 @@ static void pwm_apply_debug(struct pwm_device *pwm,
if (!chip->ops->get_state)
return;
/*
* If a disabled PWM was requested the result is unspecified, so nothing
* to check.
*/
if (!state->enabled)
return;
/*
* *state was just applied. Read out the hardware state and do some
* checks.
@ -507,26 +514,32 @@ static void pwm_apply_debug(struct pwm_device *pwm,
/* If that failed there isn't much to debug */
return;
/*
* If the PWM was disabled that's maybe strange but there is nothing
* that can be sensibly checked then. So return early.
*/
if (!s1.enabled)
return;
/*
* The lowlevel driver either ignored .polarity (which is a bug) or as
* best effort inverted .polarity and fixed .duty_cycle respectively.
* Undo this inversion and fixup for further tests.
*/
if (s1.enabled && s1.polarity != state->polarity) {
if (s1.polarity != state->polarity) {
s2.polarity = state->polarity;
s2.duty_cycle = s1.period - s1.duty_cycle;
s2.period = s1.period;
s2.enabled = s1.enabled;
s2.enabled = true;
} else {
s2 = s1;
}
if (s2.polarity != state->polarity &&
state->duty_cycle < state->period)
s2.duty_cycle < s2.period)
dev_warn(pwmchip_parent(chip), ".apply ignored .polarity\n");
if (state->enabled && s2.enabled &&
last->polarity == state->polarity &&
if (last->polarity == state->polarity &&
last->period > s2.period &&
last->period <= state->period)
dev_warn(pwmchip_parent(chip),
@ -537,13 +550,12 @@ static void pwm_apply_debug(struct pwm_device *pwm,
* Rounding period up is fine only if duty_cycle is 0 then, because a
* flat line doesn't have a characteristic period.
*/
if (state->enabled && s2.enabled && state->period < s2.period && s2.duty_cycle)
if (state->period < s2.period && s2.duty_cycle)
dev_warn(pwmchip_parent(chip),
".apply is supposed to round down period (requested: %llu, applied: %llu)\n",
state->period, s2.period);
if (state->enabled &&
last->polarity == state->polarity &&
if (last->polarity == state->polarity &&
last->period == s2.period &&
last->duty_cycle > s2.duty_cycle &&
last->duty_cycle <= state->duty_cycle)
@ -553,16 +565,12 @@ static void pwm_apply_debug(struct pwm_device *pwm,
s2.duty_cycle, s2.period,
last->duty_cycle, last->period);
if (state->enabled && s2.enabled && state->duty_cycle < s2.duty_cycle)
if (state->duty_cycle < s2.duty_cycle)
dev_warn(pwmchip_parent(chip),
".apply is supposed to round down duty_cycle (requested: %llu/%llu, applied: %llu/%llu)\n",
state->duty_cycle, state->period,
s2.duty_cycle, s2.period);
if (!state->enabled && s2.enabled && s2.duty_cycle > 0)
dev_warn(pwmchip_parent(chip),
"requested disabled, but yielded enabled with duty > 0\n");
/* reapply the state that the driver reported being configured. */
err = chip->ops->apply(chip, pwm, &s1);
trace_pwm_apply(pwm, &s1, err);
@ -2383,6 +2391,51 @@ static const struct file_operations pwm_cdev_fileops = {
static dev_t pwm_devt;
static int pwm_gpio_request(struct gpio_chip *gc, unsigned int offset)
{
struct pwm_chip *chip = gpiochip_get_data(gc);
struct pwm_device *pwm;
pwm = pwm_request_from_chip(chip, offset, "pwm-gpio");
if (IS_ERR(pwm))
return PTR_ERR(pwm);
return 0;
}
static void pwm_gpio_free(struct gpio_chip *gc, unsigned int offset)
{
struct pwm_chip *chip = gpiochip_get_data(gc);
pwm_put(&chip->pwms[offset]);
}
static int pwm_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
{
return GPIO_LINE_DIRECTION_OUT;
}
static int pwm_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
{
struct pwm_chip *chip = gpiochip_get_data(gc);
struct pwm_device *pwm = &chip->pwms[offset];
int ret;
struct pwm_waveform wf = {
.period_length_ns = 1,
};
ret = pwm_round_waveform_might_sleep(pwm, &wf);
if (ret < 0)
return ret;
if (value)
wf.duty_length_ns = wf.period_length_ns;
else
wf.duty_length_ns = 0;
return pwm_set_waveform_might_sleep(pwm, &wf, true);
}
/**
* __pwmchip_add() - register a new PWM chip
* @chip: the PWM chip to add
@ -2449,9 +2502,33 @@ int __pwmchip_add(struct pwm_chip *chip, struct module *owner)
if (ret)
goto err_device_add;
if (IS_ENABLED(CONFIG_PWM_PROVIDE_GPIO) && chip->ops->write_waveform) {
struct device *parent = pwmchip_parent(chip);
chip->gpio = (typeof(chip->gpio)){
.label = dev_name(parent),
.parent = parent,
.request = pwm_gpio_request,
.free = pwm_gpio_free,
.get_direction = pwm_gpio_get_direction,
.set = pwm_gpio_set,
.base = -1,
.ngpio = chip->npwm,
.can_sleep = true,
};
ret = gpiochip_add_data(&chip->gpio, chip);
if (ret)
goto err_gpiochip_add;
}
return 0;
err_gpiochip_add:
cdev_device_del(&chip->cdev, &chip->dev);
err_device_add:
scoped_guard(pwmchip, chip)
chip->operational = false;
@ -2472,6 +2549,9 @@ EXPORT_SYMBOL_GPL(__pwmchip_add);
*/
void pwmchip_remove(struct pwm_chip *chip)
{
if (IS_ENABLED(CONFIG_PWM_PROVIDE_GPIO) && chip->ops->write_waveform)
gpiochip_remove(&chip->gpio);
pwmchip_sysfs_unexport(chip);
scoped_guard(mutex, &pwm_lock) {

4
drivers/pwm/pwm-berlin.c
View File

@ -234,7 +234,7 @@ static int berlin_pwm_suspend(struct device *dev)
for (i = 0; i < chip->npwm; i++) {
struct berlin_pwm_channel *channel = &bpc->channel[i];
channel->enable = berlin_pwm_readl(bpc, i, BERLIN_PWM_ENABLE);
channel->enable = berlin_pwm_readl(bpc, i, BERLIN_PWM_EN);
channel->ctrl = berlin_pwm_readl(bpc, i, BERLIN_PWM_CONTROL);
channel->duty = berlin_pwm_readl(bpc, i, BERLIN_PWM_DUTY);
channel->tcnt = berlin_pwm_readl(bpc, i, BERLIN_PWM_TCNT);
@ -262,7 +262,7 @@ static int berlin_pwm_resume(struct device *dev)
berlin_pwm_writel(bpc, i, channel->ctrl, BERLIN_PWM_CONTROL);
berlin_pwm_writel(bpc, i, channel->duty, BERLIN_PWM_DUTY);
berlin_pwm_writel(bpc, i, channel->tcnt, BERLIN_PWM_TCNT);
berlin_pwm_writel(bpc, i, channel->enable, BERLIN_PWM_ENABLE);
berlin_pwm_writel(bpc, i, channel->enable, BERLIN_PWM_EN);
}
return 0;

10
drivers/pwm/pwm-cros-ec.c
View File

@ -49,10 +49,9 @@ static int cros_ec_pwm_set_duty(struct cros_ec_pwm_device *ec_pwm, u8 index,
u16 duty)
{
struct cros_ec_device *ec = ec_pwm->ec;
struct {
struct cros_ec_command msg;
TRAILING_OVERLAP(struct cros_ec_command, msg, data,
struct ec_params_pwm_set_duty params;
} __packed buf;
) __packed buf;
struct ec_params_pwm_set_duty *params = &buf.params;
struct cros_ec_command *msg = &buf.msg;
int ret;
@ -83,13 +82,12 @@ static int cros_ec_pwm_set_duty(struct cros_ec_pwm_device *ec_pwm, u8 index,
static int cros_ec_pwm_get_duty(struct cros_ec_device *ec, bool use_pwm_type, u8 index)
{
struct {
struct cros_ec_command msg;
TRAILING_OVERLAP(struct cros_ec_command, msg, data,
union {
struct ec_params_pwm_get_duty params;
struct ec_response_pwm_get_duty resp;
};
} __packed buf;
) __packed buf;
struct ec_params_pwm_get_duty *params = &buf.params;
struct ec_response_pwm_get_duty *resp = &buf.resp;
struct cros_ec_command *msg = &buf.msg;

35
drivers/pwm/pwm-fsl-ftm.c
View File

@ -3,6 +3,7 @@
* Freescale FlexTimer Module (FTM) PWM Driver
*
* Copyright 2012-2013 Freescale Semiconductor, Inc.
* Copyright 2020-2025 NXP
*/
#include <linux/clk.h>
@ -30,6 +31,8 @@ enum fsl_pwm_clk {
struct fsl_ftm_soc {
bool has_enable_bits;
bool has_flt_reg;
unsigned int npwm;
};
struct fsl_pwm_periodcfg {
@ -374,6 +377,20 @@ static bool fsl_pwm_volatile_reg(struct device *dev, unsigned int reg)
return false;
}
static bool fsl_pwm_is_reg(struct device *dev, unsigned int reg)
{
struct pwm_chip *chip = dev_get_drvdata(dev);
struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
if (reg >= FTM_CSC(fpc->soc->npwm) && reg < FTM_CNTIN)
return false;
if ((reg == FTM_FLTCTRL || reg == FTM_FLTPOL) && !fpc->soc->has_flt_reg)
return false;
return true;
}
static const struct regmap_config fsl_pwm_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@ -382,21 +399,24 @@ static const struct regmap_config fsl_pwm_regmap_config = {
.max_register = FTM_PWMLOAD,
.volatile_reg = fsl_pwm_volatile_reg,
.cache_type = REGCACHE_FLAT,
.writeable_reg = fsl_pwm_is_reg,
.readable_reg = fsl_pwm_is_reg,
};
static int fsl_pwm_probe(struct platform_device *pdev)
{
const struct fsl_ftm_soc *soc = of_device_get_match_data(&pdev->dev);
struct pwm_chip *chip;
struct fsl_pwm_chip *fpc;
void __iomem *base;
int ret;
chip = devm_pwmchip_alloc(&pdev->dev, 8, sizeof(*fpc));
chip = devm_pwmchip_alloc(&pdev->dev, soc->npwm, sizeof(*fpc));
if (IS_ERR(chip))
return PTR_ERR(chip);
fpc = to_fsl_chip(chip);
fpc->soc = of_device_get_match_data(&pdev->dev);
fpc->soc = soc;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
@ -512,15 +532,26 @@ static const struct dev_pm_ops fsl_pwm_pm_ops = {
static const struct fsl_ftm_soc vf610_ftm_pwm = {
.has_enable_bits = false,
.has_flt_reg = true,
.npwm = 8,
};
static const struct fsl_ftm_soc imx8qm_ftm_pwm = {
.has_enable_bits = true,
.has_flt_reg = true,
.npwm = 8,
};
static const struct fsl_ftm_soc s32g2_ftm_pwm = {
.has_enable_bits = true,
.has_flt_reg = false,
.npwm = 6,
};
static const struct of_device_id fsl_pwm_dt_ids[] = {
{ .compatible = "fsl,vf610-ftm-pwm", .data = &vf610_ftm_pwm },
{ .compatible = "fsl,imx8qm-ftm-pwm", .data = &imx8qm_ftm_pwm },
{ .compatible = "nxp,s32g2-ftm-pwm", .data = &s32g2_ftm_pwm },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids);

2
drivers/pwm/pwm-loongson.c
View File

@ -49,7 +49,7 @@
#define LOONGSON_PWM_CTRL_REG_DZONE BIT(10) /* Anti-dead Zone Enable Bit */
/* default input clk frequency for the ACPI case */
#define LOONGSON_PWM_FREQ_DEFAULT 50000 /* Hz */
#define LOONGSON_PWM_FREQ_DEFAULT 50000000 /* Hz */
struct pwm_loongson_ddata {
struct clk *clk;

312
drivers/pwm/pwm-mediatek.c
View File

@ -7,6 +7,7 @@
*
*/
#include <linux/bitfield.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/ioport.h>
@ -21,24 +22,26 @@
/* PWM registers and bits definitions */
#define PWMCON 0x00
#define PWMCON_CLKDIV GENMASK(2, 0)
#define PWMHDUR 0x04
#define PWMLDUR 0x08
#define PWMGDUR 0x0c
#define PWMWAVENUM 0x28
#define PWMDWIDTH 0x2c
#define PWMDWIDTH_PERIOD GENMASK(12, 0)
#define PWM45DWIDTH_FIXUP 0x30
#define PWMTHRES 0x30
#define PWMTHRES_DUTY GENMASK(12, 0)
#define PWM45THRES_FIXUP 0x34
#define PWM_CK_26M_SEL_V3 0x74
#define PWM_CK_26M_SEL 0x210
#define PWM_CLK_DIV_MAX 7
struct pwm_mediatek_of_data {
unsigned int num_pwms;
bool pwm45_fixup;
u16 pwm_ck_26m_sel_reg;
const unsigned int *reg_offset;
unsigned int chanreg_base;
unsigned int chanreg_width;
};
/**
@ -46,28 +49,18 @@ struct pwm_mediatek_of_data {
* @regs: base address of PWM chip
* @clk_top: the top clock generator
* @clk_main: the clock used by PWM core
* @clk_pwms: the clock used by each PWM channel
* @soc: pointer to chip's platform data
* @clk_pwms: the clock and clkrate used by each PWM channel
*/
struct pwm_mediatek_chip {
void __iomem *regs;
struct clk *clk_top;
struct clk *clk_main;
struct clk **clk_pwms;
const struct pwm_mediatek_of_data *soc;
};
static const unsigned int mtk_pwm_reg_offset_v1[] = {
0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
};
static const unsigned int mtk_pwm_reg_offset_v2[] = {
0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
};
/* PWM IP Version 3.0.2 */
static const unsigned int mtk_pwm_reg_offset_v3[] = {
0x0100, 0x0200, 0x0300, 0x0400, 0x0500, 0x0600, 0x0700, 0x0800
struct {
struct clk *clk;
unsigned long rate;
} clk_pwms[];
};
static inline struct pwm_mediatek_chip *
@ -76,10 +69,9 @@ to_pwm_mediatek_chip(struct pwm_chip *chip)
return pwmchip_get_drvdata(chip);
}
static int pwm_mediatek_clk_enable(struct pwm_chip *chip,
struct pwm_device *pwm)
static int pwm_mediatek_clk_enable(struct pwm_mediatek_chip *pc,
unsigned int hwpwm)
{
struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
int ret;
ret = clk_prepare_enable(pc->clk_top);
@ -90,12 +82,28 @@ static int pwm_mediatek_clk_enable(struct pwm_chip *chip,
if (ret < 0)
goto disable_clk_top;
ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]);
ret = clk_prepare_enable(pc->clk_pwms[hwpwm].clk);
if (ret < 0)
goto disable_clk_main;
if (!pc->clk_pwms[hwpwm].rate) {
pc->clk_pwms[hwpwm].rate = clk_get_rate(pc->clk_pwms[hwpwm].clk);
/*
* With the clk running with not more than 1 GHz the
* calculations in .apply() won't overflow.
*/
if (!pc->clk_pwms[hwpwm].rate ||
pc->clk_pwms[hwpwm].rate > 1000000000) {
ret = -EINVAL;
goto disable_clk_hwpwm;
}
}
return 0;
disable_clk_hwpwm:
clk_disable_unprepare(pc->clk_pwms[hwpwm].clk);
disable_clk_main:
clk_disable_unprepare(pc->clk_main);
disable_clk_top:
@ -104,12 +112,10 @@ static int pwm_mediatek_clk_enable(struct pwm_chip *chip,
return ret;
}
static void pwm_mediatek_clk_disable(struct pwm_chip *chip,
struct pwm_device *pwm)
static void pwm_mediatek_clk_disable(struct pwm_mediatek_chip *pc,
unsigned int hwpwm)
{
struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]);
clk_disable_unprepare(pc->clk_pwms[hwpwm].clk);
clk_disable_unprepare(pc->clk_main);
clk_disable_unprepare(pc->clk_top);
}
@ -118,7 +124,15 @@ static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip,
unsigned int num, unsigned int offset,
u32 value)
{
writel(value, chip->regs + chip->soc->reg_offset[num] + offset);
writel(value, chip->regs + chip->soc->chanreg_base +
num * chip->soc->chanreg_width + offset);
}
static inline u32 pwm_mediatek_readl(struct pwm_mediatek_chip *chip,
unsigned int num, unsigned int offset)
{
return readl(chip->regs + chip->soc->chanreg_base +
num * chip->soc->chanreg_width + offset);
}
static void pwm_mediatek_enable(struct pwm_chip *chip, struct pwm_device *pwm)
@ -142,50 +156,59 @@ static void pwm_mediatek_disable(struct pwm_chip *chip, struct pwm_device *pwm)
}
static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
int duty_ns, int period_ns)
u64 duty_ns, u64 period_ns)
{
struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH,
reg_thres = PWMTHRES;
u32 clkdiv, enable;
u32 reg_width = PWMDWIDTH, reg_thres = PWMTHRES;
u64 cnt_period, cnt_duty;
unsigned long clk_rate;
u64 resolution;
int ret;
ret = pwm_mediatek_clk_enable(chip, pwm);
ret = pwm_mediatek_clk_enable(pc, pwm->hwpwm);
if (ret < 0)
return ret;
clk_rate = clk_get_rate(pc->clk_pwms[pwm->hwpwm]);
if (!clk_rate) {
ret = -EINVAL;
goto out;
}
clk_rate = pc->clk_pwms[pwm->hwpwm].rate;
/* Make sure we use the bus clock and not the 26MHz clock */
if (pc->soc->pwm_ck_26m_sel_reg)
writel(0, pc->regs + pc->soc->pwm_ck_26m_sel_reg);
/* Using resolution in picosecond gets accuracy higher */
resolution = (u64)NSEC_PER_SEC * 1000;
do_div(resolution, clk_rate);
cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
if (!cnt_period)
return -EINVAL;
while (cnt_period > 8192) {
resolution *= 2;
clkdiv++;
cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000,
resolution);
}
if (clkdiv > PWM_CLK_DIV_MAX) {
dev_err(pwmchip_parent(chip), "period of %d ns not supported\n", period_ns);
ret = -EINVAL;
cnt_period = mul_u64_u64_div_u64(period_ns, clk_rate, NSEC_PER_SEC);
if (cnt_period == 0) {
ret = -ERANGE;
goto out;
}
if (cnt_period > FIELD_MAX(PWMDWIDTH_PERIOD) + 1) {
if (cnt_period >= ((FIELD_MAX(PWMDWIDTH_PERIOD) + 1) << FIELD_MAX(PWMCON_CLKDIV))) {
clkdiv = FIELD_MAX(PWMCON_CLKDIV);
cnt_period = FIELD_MAX(PWMDWIDTH_PERIOD) + 1;
} else {
clkdiv = ilog2(cnt_period) - ilog2(FIELD_MAX(PWMDWIDTH_PERIOD));
cnt_period >>= clkdiv;
}
} else {
clkdiv = 0;
}
cnt_duty = mul_u64_u64_div_u64(duty_ns, clk_rate, NSEC_PER_SEC) >> clkdiv;
if (cnt_duty > cnt_period)
cnt_duty = cnt_period;
if (cnt_duty) {
cnt_duty -= 1;
enable = BIT(pwm->hwpwm);
} else {
enable = 0;
}
cnt_period -= 1;
dev_dbg(&chip->dev, "pwm#%u: %lld/%lld @%lu -> CON: %x, PERIOD: %llx, DUTY: %llx\n",
pwm->hwpwm, duty_ns, period_ns, clk_rate, clkdiv, cnt_period, cnt_duty);
if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
/*
* PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
@ -195,20 +218,18 @@ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
reg_thres = PWM45THRES_FIXUP;
}
cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period - 1);
pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period);
if (cnt_duty) {
pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty - 1);
if (enable) {
pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty);
pwm_mediatek_enable(chip, pwm);
} else {
pwm_mediatek_disable(chip, pwm);
}
out:
pwm_mediatek_clk_disable(chip, pwm);
pwm_mediatek_clk_disable(pc, pwm->hwpwm);
return ret;
}
@ -216,6 +237,7 @@ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
static int pwm_mediatek_apply(struct pwm_chip *chip, struct pwm_device *pwm,
const struct pwm_state *state)
{
struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
int err;
if (state->polarity != PWM_POLARITY_NORMAL)
@ -224,7 +246,7 @@ static int pwm_mediatek_apply(struct pwm_chip *chip, struct pwm_device *pwm,
if (!state->enabled) {
if (pwm->state.enabled) {
pwm_mediatek_disable(chip, pwm);
pwm_mediatek_clk_disable(chip, pwm);
pwm_mediatek_clk_disable(pc, pwm->hwpwm);
}
return 0;
@ -235,15 +257,115 @@ static int pwm_mediatek_apply(struct pwm_chip *chip, struct pwm_device *pwm,
return err;
if (!pwm->state.enabled)
err = pwm_mediatek_clk_enable(chip, pwm);
err = pwm_mediatek_clk_enable(pc, pwm->hwpwm);
return err;
}
static int pwm_mediatek_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
struct pwm_state *state)
{
struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
int ret;
u32 enable;
u32 reg_width = PWMDWIDTH, reg_thres = PWMTHRES;
if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
/*
* PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
* from the other PWMs on MT7623.
*/
reg_width = PWM45DWIDTH_FIXUP;
reg_thres = PWM45THRES_FIXUP;
}
ret = pwm_mediatek_clk_enable(pc, pwm->hwpwm);
if (ret < 0)
return ret;
enable = readl(pc->regs);
if (enable & BIT(pwm->hwpwm)) {
u32 clkdiv, cnt_period, cnt_duty;
unsigned long clk_rate;
clk_rate = pc->clk_pwms[pwm->hwpwm].rate;
state->enabled = true;
state->polarity = PWM_POLARITY_NORMAL;
clkdiv = FIELD_GET(PWMCON_CLKDIV,
pwm_mediatek_readl(pc, pwm->hwpwm, PWMCON));
cnt_period = FIELD_GET(PWMDWIDTH_PERIOD,
pwm_mediatek_readl(pc, pwm->hwpwm, reg_width));
cnt_duty = FIELD_GET(PWMTHRES_DUTY,
pwm_mediatek_readl(pc, pwm->hwpwm, reg_thres));
/*
* cnt_period is a 13 bit value, NSEC_PER_SEC is 30 bits wide
* and clkdiv is less than 8, so the multiplication doesn't
* overflow an u64.
*/
state->period =
DIV_ROUND_UP_ULL((u64)cnt_period * NSEC_PER_SEC << clkdiv, clk_rate);
state->duty_cycle =
DIV_ROUND_UP_ULL((u64)cnt_duty * NSEC_PER_SEC << clkdiv, clk_rate);
} else {
state->enabled = false;
}
pwm_mediatek_clk_disable(pc, pwm->hwpwm);
return ret;
}
static const struct pwm_ops pwm_mediatek_ops = {
.apply = pwm_mediatek_apply,
.get_state = pwm_mediatek_get_state,
};
static int pwm_mediatek_init_used_clks(struct pwm_mediatek_chip *pc)
{
const struct pwm_mediatek_of_data *soc = pc->soc;
unsigned int hwpwm;
u32 enabled, handled = 0;
int ret;
ret = clk_prepare_enable(pc->clk_top);
if (ret)
return ret;
ret = clk_prepare_enable(pc->clk_main);
if (ret)
goto err_enable_main;
enabled = readl(pc->regs) & GENMASK(soc->num_pwms - 1, 0);
while (enabled & ~handled) {
hwpwm = ilog2(enabled & ~handled);
ret = pwm_mediatek_clk_enable(pc, hwpwm);
if (ret) {
while (handled) {
hwpwm = ilog2(handled);
pwm_mediatek_clk_disable(pc, hwpwm);
handled &= ~BIT(hwpwm);
}
break;
}
handled |= BIT(hwpwm);
}
clk_disable_unprepare(pc->clk_main);
err_enable_main:
clk_disable_unprepare(pc->clk_top);
return ret;
}
static int pwm_mediatek_probe(struct platform_device *pdev)
{
struct pwm_chip *chip;
@ -254,7 +376,8 @@ static int pwm_mediatek_probe(struct platform_device *pdev)
soc = of_device_get_match_data(&pdev->dev);
chip = devm_pwmchip_alloc(&pdev->dev, soc->num_pwms, sizeof(*pc));
chip = devm_pwmchip_alloc(&pdev->dev, soc->num_pwms,
sizeof(*pc) + soc->num_pwms * sizeof(*pc->clk_pwms));
if (IS_ERR(chip))
return PTR_ERR(chip);
pc = to_pwm_mediatek_chip(chip);
@ -265,11 +388,6 @@ static int pwm_mediatek_probe(struct platform_device *pdev)
if (IS_ERR(pc->regs))
return PTR_ERR(pc->regs);
pc->clk_pwms = devm_kmalloc_array(&pdev->dev, soc->num_pwms,
sizeof(*pc->clk_pwms), GFP_KERNEL);
if (!pc->clk_pwms)
return -ENOMEM;
pc->clk_top = devm_clk_get(&pdev->dev, "top");
if (IS_ERR(pc->clk_top))
return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_top),
@ -285,12 +403,21 @@ static int pwm_mediatek_probe(struct platform_device *pdev)
snprintf(name, sizeof(name), "pwm%d", i + 1);
pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name);
if (IS_ERR(pc->clk_pwms[i]))
return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_pwms[i]),
pc->clk_pwms[i].clk = devm_clk_get(&pdev->dev, name);
if (IS_ERR(pc->clk_pwms[i].clk))
return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_pwms[i].clk),
"Failed to get %s clock\n", name);
ret = devm_clk_rate_exclusive_get(&pdev->dev, pc->clk_pwms[i].clk);
if (ret)
return dev_err_probe(&pdev->dev, ret,
"Failed to lock clock rate for %s\n", name);
}
ret = pwm_mediatek_init_used_clks(pc);
if (ret)
return dev_err_probe(&pdev->dev, ret, "Failed to initialize used clocks\n");
chip->ops = &pwm_mediatek_ops;
ret = devm_pwmchip_add(&pdev->dev, chip);
@ -303,86 +430,99 @@ static int pwm_mediatek_probe(struct platform_device *pdev)
static const struct pwm_mediatek_of_data mt2712_pwm_data = {
.num_pwms = 8,
.pwm45_fixup = false,
.reg_offset = mtk_pwm_reg_offset_v1,
.chanreg_base = 0x10,
.chanreg_width = 0x40,
};
static const struct pwm_mediatek_of_data mt6795_pwm_data = {
.num_pwms = 7,
.pwm45_fixup = false,
.reg_offset = mtk_pwm_reg_offset_v1,
.chanreg_base = 0x10,
.chanreg_width = 0x40,
};
static const struct pwm_mediatek_of_data mt7622_pwm_data = {
.num_pwms = 6,
.pwm45_fixup = false,
.pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
.reg_offset = mtk_pwm_reg_offset_v1,
.chanreg_base = 0x10,
.chanreg_width = 0x40,
};
static const struct pwm_mediatek_of_data mt7623_pwm_data = {
.num_pwms = 5,
.pwm45_fixup = true,
.reg_offset = mtk_pwm_reg_offset_v1,
.chanreg_base = 0x10,
.chanreg_width = 0x40,
};
static const struct pwm_mediatek_of_data mt7628_pwm_data = {
.num_pwms = 4,
.pwm45_fixup = true,
.reg_offset = mtk_pwm_reg_offset_v1,
.chanreg_base = 0x10,
.chanreg_width = 0x40,
};
static const struct pwm_mediatek_of_data mt7629_pwm_data = {
.num_pwms = 1,
.pwm45_fixup = false,
.reg_offset = mtk_pwm_reg_offset_v1,
.chanreg_base = 0x10,
.chanreg_width = 0x40,
};
static const struct pwm_mediatek_of_data mt7981_pwm_data = {
.num_pwms = 3,
.pwm45_fixup = false,
.pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
.reg_offset = mtk_pwm_reg_offset_v2,
.chanreg_base = 0x80,
.chanreg_width = 0x40,
};
static const struct pwm_mediatek_of_data mt7986_pwm_data = {
.num_pwms = 2,
.pwm45_fixup = false,
.pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
.reg_offset = mtk_pwm_reg_offset_v1,
.chanreg_base = 0x10,
.chanreg_width = 0x40,
};
static const struct pwm_mediatek_of_data mt7988_pwm_data = {
.num_pwms = 8,
.pwm45_fixup = false,
.reg_offset = mtk_pwm_reg_offset_v2,
.chanreg_base = 0x80,
.chanreg_width = 0x40,
};
static const struct pwm_mediatek_of_data mt8183_pwm_data = {
.num_pwms = 4,
.pwm45_fixup = false,
.pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
.reg_offset = mtk_pwm_reg_offset_v1,
.chanreg_base = 0x10,
.chanreg_width = 0x40,
};
static const struct pwm_mediatek_of_data mt8365_pwm_data = {
.num_pwms = 3,
.pwm45_fixup = false,
.pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
.reg_offset = mtk_pwm_reg_offset_v1,
.chanreg_base = 0x10,
.chanreg_width = 0x40,
};
static const struct pwm_mediatek_of_data mt8516_pwm_data = {
.num_pwms = 5,
.pwm45_fixup = false,
.pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
.reg_offset = mtk_pwm_reg_offset_v1,
.chanreg_base = 0x10,
.chanreg_width = 0x40,
};
static const struct pwm_mediatek_of_data mt6991_pwm_data = {
.num_pwms = 4,
.pwm45_fixup = false,
.pwm_ck_26m_sel_reg = PWM_CK_26M_SEL_V3,
.reg_offset = mtk_pwm_reg_offset_v3,
.chanreg_base = 0x100,
.chanreg_width = 0x100,
};
static const struct of_device_id pwm_mediatek_of_match[] = {

555
drivers/pwm/pwm-pca9685.c
View File

@ -26,7 +26,6 @@
* that is enabled is allowed to change the prescale register.
* PWM channels requested afterwards must use a period that results in the same
* prescale setting as the one set by the first requested channel.
* GPIOs do not count as enabled PWMs as they are not using the prescaler.
*/
#define PCA9685_MODE1 0x00
@ -50,7 +49,14 @@
#define PCA9685_PRESCALE_MAX 0xFF /* => min. frequency of 24 Hz */
#define PCA9685_COUNTER_RANGE 4096
#define PCA9685_OSC_CLOCK_MHZ 25 /* Internal oscillator with 25 MHz */
#define PCA9685_OSC_CLOCK_HZ 25000000 /* Internal oscillator with 25 MHz */
/*
* The time value of one counter tick. Note that NSEC_PER_SEC is an integer
* multiple of PCA9685_OSC_CLOCK_HZ, so there is no rounding involved and we're
* not loosing precision due to the early division.
*/
#define PCA9685_QUANTUM_NS(_prescale) ((NSEC_PER_SEC / PCA9685_OSC_CLOCK_HZ) * (_prescale + 1))
#define PCA9685_NUMREGS 0xFF
#define PCA9685_MAXCHAN 0x10
@ -61,6 +67,8 @@
#define MODE1_SUB2 BIT(2)
#define MODE1_SUB1 BIT(3)
#define MODE1_SLEEP BIT(4)
#define MODE1_AI BIT(5)
#define MODE2_INVRT BIT(4)
#define MODE2_OUTDRV BIT(2)
@ -78,10 +86,6 @@ struct pca9685 {
struct regmap *regmap;
struct mutex lock;
DECLARE_BITMAP(pwms_enabled, PCA9685_MAXCHAN + 1);
#if IS_ENABLED(CONFIG_GPIOLIB)
struct gpio_chip gpio;
DECLARE_BITMAP(pwms_inuse, PCA9685_MAXCHAN + 1);
#endif
};
static inline struct pca9685 *to_pca(struct pwm_chip *chip)
@ -131,355 +135,232 @@ static int pca9685_write_reg(struct pwm_chip *chip, unsigned int reg, unsigned i
return err;
}
/* Helper function to set the duty cycle ratio to duty/4096 (e.g. duty=2048 -> 50%) */
static void pca9685_pwm_set_duty(struct pwm_chip *chip, int channel, unsigned int duty)
{
struct pwm_device *pwm = &chip->pwms[channel];
unsigned int on, off;
if (duty == 0) {
/* Set the full OFF bit, which has the highest precedence */
pca9685_write_reg(chip, REG_OFF_H(channel), LED_FULL);
return;
} else if (duty >= PCA9685_COUNTER_RANGE) {
/* Set the full ON bit and clear the full OFF bit */
pca9685_write_reg(chip, REG_ON_H(channel), LED_FULL);
pca9685_write_reg(chip, REG_OFF_H(channel), 0);
return;
}
if (pwm->state.usage_power && channel < PCA9685_MAXCHAN) {
/*
* If usage_power is set, the pca9685 driver will phase shift
* the individual channels relative to their channel number.
* This improves EMI because the enabled channels no longer
* turn on at the same time, while still maintaining the
* configured duty cycle / power output.
*/
on = channel * PCA9685_COUNTER_RANGE / PCA9685_MAXCHAN;
} else
on = 0;
off = (on + duty) % PCA9685_COUNTER_RANGE;
/* Set ON time (clears full ON bit) */
pca9685_write_reg(chip, REG_ON_L(channel), on & 0xff);
pca9685_write_reg(chip, REG_ON_H(channel), (on >> 8) & 0xf);
/* Set OFF time (clears full OFF bit) */
pca9685_write_reg(chip, REG_OFF_L(channel), off & 0xff);
pca9685_write_reg(chip, REG_OFF_H(channel), (off >> 8) & 0xf);
}
static unsigned int pca9685_pwm_get_duty(struct pwm_chip *chip, int channel)
{
struct pwm_device *pwm = &chip->pwms[channel];
unsigned int off = 0, on = 0, val = 0;
if (WARN_ON(channel >= PCA9685_MAXCHAN)) {
/* HW does not support reading state of "all LEDs" channel */
return 0;
}
pca9685_read_reg(chip, LED_N_OFF_H(channel), &off);
if (off & LED_FULL) {
/* Full OFF bit is set */
return 0;
}
pca9685_read_reg(chip, LED_N_ON_H(channel), &on);
if (on & LED_FULL) {
/* Full ON bit is set */
return PCA9685_COUNTER_RANGE;
}
pca9685_read_reg(chip, LED_N_OFF_L(channel), &val);
off = ((off & 0xf) << 8) | (val & 0xff);
if (!pwm->state.usage_power)
return off;
/* Read ON register to calculate duty cycle of staggered output */
if (pca9685_read_reg(chip, LED_N_ON_L(channel), &val)) {
/* Reset val to 0 in case reading LED_N_ON_L failed */
val = 0;
}
on = ((on & 0xf) << 8) | (val & 0xff);
return (off - on) & (PCA9685_COUNTER_RANGE - 1);
}
#if IS_ENABLED(CONFIG_GPIOLIB)
static bool pca9685_pwm_test_and_set_inuse(struct pca9685 *pca, int pwm_idx)
{
bool is_inuse;
mutex_lock(&pca->lock);
if (pwm_idx >= PCA9685_MAXCHAN) {
/*
* "All LEDs" channel:
* pretend already in use if any of the PWMs are requested
*/
if (!bitmap_empty(pca->pwms_inuse, PCA9685_MAXCHAN)) {
is_inuse = true;
goto out;
}
} else {
/*
* Regular channel:
* pretend already in use if the "all LEDs" channel is requested
*/
if (test_bit(PCA9685_MAXCHAN, pca->pwms_inuse)) {
is_inuse = true;
goto out;
}
}
is_inuse = test_and_set_bit(pwm_idx, pca->pwms_inuse);
out:
mutex_unlock(&pca->lock);
return is_inuse;
}
static void pca9685_pwm_clear_inuse(struct pca9685 *pca, int pwm_idx)
{
mutex_lock(&pca->lock);
clear_bit(pwm_idx, pca->pwms_inuse);
mutex_unlock(&pca->lock);
}
static int pca9685_pwm_gpio_request(struct gpio_chip *gpio, unsigned int offset)
{
struct pwm_chip *chip = gpiochip_get_data(gpio);
struct pca9685 *pca = to_pca(chip);
if (pca9685_pwm_test_and_set_inuse(pca, offset))
return -EBUSY;
pm_runtime_get_sync(pwmchip_parent(chip));
return 0;
}
static int pca9685_pwm_gpio_get(struct gpio_chip *gpio, unsigned int offset)
{
struct pwm_chip *chip = gpiochip_get_data(gpio);
return pca9685_pwm_get_duty(chip, offset) != 0;
}
static int pca9685_pwm_gpio_set(struct gpio_chip *gpio, unsigned int offset,
int value)
{
struct pwm_chip *chip = gpiochip_get_data(gpio);
pca9685_pwm_set_duty(chip, offset, value ? PCA9685_COUNTER_RANGE : 0);
return 0;
}
static void pca9685_pwm_gpio_free(struct gpio_chip *gpio, unsigned int offset)
{
struct pwm_chip *chip = gpiochip_get_data(gpio);
struct pca9685 *pca = to_pca(chip);
pca9685_pwm_set_duty(chip, offset, 0);
pm_runtime_put(pwmchip_parent(chip));
pca9685_pwm_clear_inuse(pca, offset);
}
static int pca9685_pwm_gpio_get_direction(struct gpio_chip *chip,
unsigned int offset)
{
/* Always out */
return GPIO_LINE_DIRECTION_OUT;
}
static int pca9685_pwm_gpio_direction_input(struct gpio_chip *gpio,
unsigned int offset)
{
return -EINVAL;
}
static int pca9685_pwm_gpio_direction_output(struct gpio_chip *gpio,
unsigned int offset, int value)
{
pca9685_pwm_gpio_set(gpio, offset, value);
return 0;
}
/*
* The PCA9685 has a bit for turning the PWM output full off or on. Some
* boards like Intel Galileo actually uses these as normal GPIOs so we
* expose a GPIO chip here which can exclusively take over the underlying
* PWM channel.
*/
static int pca9685_pwm_gpio_probe(struct pwm_chip *chip)
static int pca9685_write_4reg(struct pwm_chip *chip, unsigned int reg, u8 val[4])
{
struct pca9685 *pca = to_pca(chip);
struct device *dev = pwmchip_parent(chip);
int err;
pca->gpio.label = dev_name(dev);
pca->gpio.parent = dev;
pca->gpio.request = pca9685_pwm_gpio_request;
pca->gpio.free = pca9685_pwm_gpio_free;
pca->gpio.get_direction = pca9685_pwm_gpio_get_direction;
pca->gpio.direction_input = pca9685_pwm_gpio_direction_input;
pca->gpio.direction_output = pca9685_pwm_gpio_direction_output;
pca->gpio.get = pca9685_pwm_gpio_get;
pca->gpio.set = pca9685_pwm_gpio_set;
pca->gpio.base = -1;
pca->gpio.ngpio = PCA9685_MAXCHAN;
pca->gpio.can_sleep = true;
err = regmap_bulk_write(pca->regmap, reg, val, 4);
if (err)
dev_err(dev, "regmap_write to register 0x%x failed: %pe\n", reg, ERR_PTR(err));
return devm_gpiochip_add_data(dev, &pca->gpio, chip);
}
#else
static inline bool pca9685_pwm_test_and_set_inuse(struct pca9685 *pca,
int pwm_idx)
{
return false;
return err;
}
static inline void
pca9685_pwm_clear_inuse(struct pca9685 *pca, int pwm_idx)
static int pca9685_set_sleep_mode(struct pwm_chip *chip, bool enable)
{
}
static inline int pca9685_pwm_gpio_probe(struct pwm_chip *chip)
{
return 0;
}
#endif
static void pca9685_set_sleep_mode(struct pwm_chip *chip, bool enable)
{
struct device *dev = pwmchip_parent(chip);
struct pca9685 *pca = to_pca(chip);
int err = regmap_update_bits(pca->regmap, PCA9685_MODE1,
MODE1_SLEEP, enable ? MODE1_SLEEP : 0);
if (err) {
dev_err(dev, "regmap_update_bits of register 0x%x failed: %pe\n",
PCA9685_MODE1, ERR_PTR(err));
return;
}
int err;
err = regmap_update_bits(pca->regmap, PCA9685_MODE1,
MODE1_SLEEP, enable ? MODE1_SLEEP : 0);
if (err)
return err;
if (!enable) {
/* Wait 500us for the oscillator to be back up */
udelay(500);
}
return 0;
}
static int __pca9685_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
const struct pwm_state *state)
struct pca9685_waveform {
u8 onoff[4];
u8 prescale;
};
static int pca9685_round_waveform_tohw(struct pwm_chip *chip, struct pwm_device *pwm, const struct pwm_waveform *wf, void *_wfhw)
{
struct pca9685_waveform *wfhw = _wfhw;
struct pca9685 *pca = to_pca(chip);
unsigned long long duty, prescale;
unsigned int val = 0;
unsigned int best_prescale;
u8 prescale;
unsigned int period_ns, duty;
int ret_tohw = 0;
if (state->polarity != PWM_POLARITY_NORMAL)
return -EINVAL;
if (!wf->period_length_ns) {
*wfhw = (typeof(*wfhw)){
.onoff = { 0, 0, 0, LED_FULL, },
.prescale = 0,
};
prescale = DIV_ROUND_CLOSEST_ULL(PCA9685_OSC_CLOCK_MHZ * state->period,
PCA9685_COUNTER_RANGE * 1000) - 1;
if (prescale < PCA9685_PRESCALE_MIN || prescale > PCA9685_PRESCALE_MAX) {
dev_err(pwmchip_parent(chip), "pwm not changed: period out of bounds!\n");
return -EINVAL;
}
dev_dbg(&chip->dev, "pwm#%u: %lld/%lld [+%lld] -> [%hhx %hhx %hhx %hhx] PSC:%hhx\n",
pwm->hwpwm, wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns,
wfhw->onoff[0], wfhw->onoff[1], wfhw->onoff[2], wfhw->onoff[3], wfhw->prescale);
if (!state->enabled) {
pca9685_pwm_set_duty(chip, pwm->hwpwm, 0);
return 0;
}
pca9685_read_reg(chip, PCA9685_PRESCALE, &val);
if (prescale != val) {
if (!pca9685_prescaler_can_change(pca, pwm->hwpwm)) {
dev_err(pwmchip_parent(chip),
"pwm not changed: periods of enabled pwms must match!\n");
return -EBUSY;
if (wf->period_length_ns >= PCA9685_COUNTER_RANGE * PCA9685_QUANTUM_NS(255)) {
best_prescale = 255;
} else if (wf->period_length_ns < PCA9685_COUNTER_RANGE * PCA9685_QUANTUM_NS(3)) {
best_prescale = 3;
ret_tohw = 1;
} else {
best_prescale = (unsigned int)wf->period_length_ns / (PCA9685_COUNTER_RANGE * (NSEC_PER_SEC / PCA9685_OSC_CLOCK_HZ)) - 1;
}
guard(mutex)(&pca->lock);
if (!pca9685_prescaler_can_change(pca, pwm->hwpwm)) {
unsigned int current_prescale;
int ret;
ret = regmap_read(pca->regmap, PCA9685_PRESCALE, &current_prescale);
if (ret)
return ret;
if (current_prescale > best_prescale)
ret_tohw = 1;
prescale = current_prescale;
} else {
prescale = best_prescale;
}
period_ns = PCA9685_COUNTER_RANGE * PCA9685_QUANTUM_NS(prescale);
duty = (unsigned)min_t(u64, wf->duty_length_ns, period_ns) / PCA9685_QUANTUM_NS(prescale);
if (duty < PCA9685_COUNTER_RANGE) {
unsigned int on, off;
on = (unsigned)min_t(u64, wf->duty_offset_ns, period_ns) / PCA9685_QUANTUM_NS(prescale);
off = (on + duty) % PCA9685_COUNTER_RANGE;
/*
* With a zero duty cycle, it doesn't matter if period was
* rounded up
*/
if (!duty)
ret_tohw = 0;
*wfhw = (typeof(*wfhw)){
.onoff = { on & 0xff, (on >> 8) & 0xf, off & 0xff, (off >> 8) & 0xf },
.prescale = prescale,
};
} else {
*wfhw = (typeof(*wfhw)){
.onoff = { 0, LED_FULL, 0, 0, },
.prescale = prescale,
};
}
dev_dbg(&chip->dev, "pwm#%u: %lld/%lld [+%lld] -> %s[%hhx %hhx %hhx %hhx] PSC:%hhx\n",
pwm->hwpwm, wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns,
ret_tohw ? "#" : "", wfhw->onoff[0], wfhw->onoff[1], wfhw->onoff[2], wfhw->onoff[3], wfhw->prescale);
return ret_tohw;
}
static int pca9685_round_waveform_fromhw(struct pwm_chip *chip, struct pwm_device *pwm,
const void *_wfhw, struct pwm_waveform *wf)
{
const struct pca9685_waveform *wfhw = _wfhw;
struct pca9685 *pca = to_pca(chip);
unsigned int prescale;
if (wfhw->prescale)
prescale = wfhw->prescale;
else
scoped_guard(mutex, &pca->lock) {
int ret;
ret = regmap_read(pca->regmap, PCA9685_PRESCALE, &prescale);
if (ret)
return ret;
}
/*
* Putting the chip briefly into SLEEP mode
* at this point won't interfere with the
* pm_runtime framework, because the pm_runtime
* state is guaranteed active here.
*/
/* Put chip into sleep mode */
pca9685_set_sleep_mode(chip, true);
wf->period_length_ns = PCA9685_COUNTER_RANGE * PCA9685_QUANTUM_NS(prescale);
/* Change the chip-wide output frequency */
pca9685_write_reg(chip, PCA9685_PRESCALE, prescale);
if (wfhw->onoff[3] & LED_FULL) {
wf->duty_length_ns = 0;
wf->duty_offset_ns = 0;
} else if (wfhw->onoff[1] & LED_FULL) {
wf->duty_length_ns = wf->period_length_ns;
wf->duty_offset_ns = 0;
} else {
unsigned int on = wfhw->onoff[0] | (wfhw->onoff[1] & 0xf) << 8;
unsigned int off = wfhw->onoff[2] | (wfhw->onoff[3] & 0xf) << 8;
/* Wake the chip up */
pca9685_set_sleep_mode(chip, false);
wf->duty_length_ns = (off - on) % PCA9685_COUNTER_RANGE * PCA9685_QUANTUM_NS(prescale);
wf->duty_offset_ns = on * PCA9685_QUANTUM_NS(prescale);
}
duty = PCA9685_COUNTER_RANGE * state->duty_cycle;
duty = DIV_ROUND_UP_ULL(duty, state->period);
pca9685_pwm_set_duty(chip, pwm->hwpwm, duty);
dev_dbg(&chip->dev, "pwm#%u: [%hhx %hhx %hhx %hhx] PSC:%hhx -> %lld/%lld [+%lld]\n",
pwm->hwpwm,
wfhw->onoff[0], wfhw->onoff[1], wfhw->onoff[2], wfhw->onoff[3], wfhw->prescale,
wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns);
return 0;
}
static int pca9685_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
const struct pwm_state *state)
static int pca9685_read_waveform(struct pwm_chip *chip, struct pwm_device *pwm, void *_wfhw)
{
struct pca9685_waveform *wfhw = _wfhw;
struct pca9685 *pca = to_pca(chip);
unsigned int prescale;
int ret;
mutex_lock(&pca->lock);
ret = __pca9685_pwm_apply(chip, pwm, state);
if (ret == 0) {
if (state->enabled)
set_bit(pwm->hwpwm, pca->pwms_enabled);
else
clear_bit(pwm->hwpwm, pca->pwms_enabled);
}
mutex_unlock(&pca->lock);
guard(mutex)(&pca->lock);
return ret;
}
ret = regmap_bulk_read(pca->regmap, REG_ON_L(pwm->hwpwm), &wfhw->onoff, 4);
if (ret)
return ret;
static int pca9685_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
struct pwm_state *state)
{
unsigned long long duty;
unsigned int val = 0;
ret = regmap_read(pca->regmap, PCA9685_PRESCALE, &prescale);
if (ret)
return ret;
/* Calculate (chip-wide) period from prescale value */
pca9685_read_reg(chip, PCA9685_PRESCALE, &val);
/*
* PCA9685_OSC_CLOCK_MHZ is 25, i.e. an integer divider of 1000.
* The following calculation is therefore only a multiplication
* and we are not losing precision.
*/
state->period = (PCA9685_COUNTER_RANGE * 1000 / PCA9685_OSC_CLOCK_MHZ) *
(val + 1);
/* The (per-channel) polarity is fixed */
state->polarity = PWM_POLARITY_NORMAL;
if (pwm->hwpwm >= PCA9685_MAXCHAN) {
/*
* The "all LEDs" channel does not support HW readout
* Return 0 and disabled for backwards compatibility
*/
state->duty_cycle = 0;
state->enabled = false;
return 0;
}
state->enabled = true;
duty = pca9685_pwm_get_duty(chip, pwm->hwpwm);
state->duty_cycle = DIV_ROUND_DOWN_ULL(duty * state->period, PCA9685_COUNTER_RANGE);
wfhw->prescale = prescale;
return 0;
}
static int pca9685_write_waveform(struct pwm_chip *chip, struct pwm_device *pwm, const void *_wfhw)
{
const struct pca9685_waveform *wfhw = _wfhw;
struct pca9685 *pca = to_pca(chip);
unsigned int current_prescale;
int ret;
guard(mutex)(&pca->lock);
if (wfhw->prescale) {
ret = regmap_read(pca->regmap, PCA9685_PRESCALE, &current_prescale);
if (ret)
return ret;
if (current_prescale != wfhw->prescale) {
if (!pca9685_prescaler_can_change(pca, pwm->hwpwm))
return -EBUSY;
/* Put chip into sleep mode */
ret = pca9685_set_sleep_mode(chip, true);
if (ret)
return ret;
/* Change the chip-wide output frequency */
ret = regmap_write(pca->regmap, PCA9685_PRESCALE, wfhw->prescale);
if (ret)
return ret;
/* Wake the chip up */
ret = pca9685_set_sleep_mode(chip, false);
if (ret)
return ret;
}
}
return regmap_bulk_write(pca->regmap, REG_ON_L(pwm->hwpwm), &wfhw->onoff, 4);
}
static int pca9685_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
{
struct pca9685 *pca = to_pca(chip);
if (pca9685_pwm_test_and_set_inuse(pca, pwm->hwpwm))
return -EBUSY;
if (pwm->hwpwm < PCA9685_MAXCHAN) {
/* PWMs - except the "all LEDs" channel - default to enabled */
mutex_lock(&pca->lock);
@ -497,26 +378,52 @@ static void pca9685_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
struct pca9685 *pca = to_pca(chip);
mutex_lock(&pca->lock);
pca9685_pwm_set_duty(chip, pwm->hwpwm, 0);
clear_bit(pwm->hwpwm, pca->pwms_enabled);
mutex_unlock(&pca->lock);
pm_runtime_put(pwmchip_parent(chip));
pca9685_pwm_clear_inuse(pca, pwm->hwpwm);
}
static const struct pwm_ops pca9685_pwm_ops = {
.apply = pca9685_pwm_apply,
.get_state = pca9685_pwm_get_state,
.sizeof_wfhw = sizeof(struct pca9685_waveform),
.round_waveform_tohw = pca9685_round_waveform_tohw,
.round_waveform_fromhw = pca9685_round_waveform_fromhw,
.read_waveform = pca9685_read_waveform,
.write_waveform = pca9685_write_waveform,
.request = pca9685_pwm_request,
.free = pca9685_pwm_free,
};
static bool pca9685_readable_reg(struct device *dev, unsigned int reg)
{
/* The ALL_LED registers are readable but read as zero */
return reg <= REG_OFF_H(15) || reg >= PCA9685_PRESCALE;
}
static bool pca9685_writeable_reg(struct device *dev, unsigned int reg)
{
return reg <= REG_OFF_H(15) || reg >= PCA9685_ALL_LED_ON_L;
}
static bool pca9685_volatile_reg(struct device *dev, unsigned int reg)
{
/*
* Writing to an ALL_LED register affects all LEDi registers, so they
* are not cachable. :-\
*/
return reg < PCA9685_PRESCALE;
}
static const struct regmap_config pca9685_regmap_i2c_config = {
.reg_bits = 8,
.val_bits = 8,
.readable_reg = pca9685_readable_reg,
.writeable_reg = pca9685_writeable_reg,
.volatile_reg = pca9685_volatile_reg,
.max_register = PCA9685_NUMREGS,
.cache_type = REGCACHE_NONE,
.cache_type = REGCACHE_MAPLE,
};
static int pca9685_pwm_probe(struct i2c_client *client)
@ -544,9 +451,8 @@ static int pca9685_pwm_probe(struct i2c_client *client)
mutex_init(&pca->lock);
ret = pca9685_read_reg(chip, PCA9685_MODE2, &reg);
if (ret)
return ret;
/* clear MODE2_OCH */
reg = 0;
if (device_property_read_bool(&client->dev, "invert"))
reg |= MODE2_INVRT;
@ -562,16 +468,19 @@ static int pca9685_pwm_probe(struct i2c_client *client)
if (ret)
return ret;
/* Disable all LED ALLCALL and SUBx addresses to avoid bus collisions */
/*
* Disable all LED ALLCALL and SUBx addresses to avoid bus collisions,
* enable Auto-Increment.
*/
pca9685_read_reg(chip, PCA9685_MODE1, &reg);
reg &= ~(MODE1_ALLCALL | MODE1_SUB1 | MODE1_SUB2 | MODE1_SUB3);
reg |= MODE1_AI;
pca9685_write_reg(chip, PCA9685_MODE1, reg);
/* Reset OFF/ON registers to POR default */
pca9685_write_reg(chip, PCA9685_ALL_LED_OFF_L, 0);
pca9685_write_reg(chip, PCA9685_ALL_LED_OFF_H, LED_FULL);
pca9685_write_reg(chip, PCA9685_ALL_LED_ON_L, 0);
pca9685_write_reg(chip, PCA9685_ALL_LED_ON_H, LED_FULL);
ret = pca9685_write_4reg(chip, PCA9685_ALL_LED_ON_L, (u8[]){ 0, LED_FULL, 0, LED_FULL });
if (ret < 0)
return dev_err_probe(&client->dev, ret, "Failed to reset ON/OFF registers\n");
chip->ops = &pca9685_pwm_ops;
@ -579,12 +488,6 @@ static int pca9685_pwm_probe(struct i2c_client *client)
if (ret < 0)
return ret;
ret = pca9685_pwm_gpio_probe(chip);
if (ret < 0) {
pwmchip_remove(chip);
return ret;
}
pm_runtime_enable(&client->dev);
if (pm_runtime_enabled(&client->dev)) {

4
drivers/pwm/pwm-tiecap.c
View File

@ -3,6 +3,10 @@
* ECAP PWM driver
*
* Copyright (C) 2012 Texas Instruments, Inc. - https://www.ti.com/
*
* Hardware properties:
* - On disable the PWM pin becomes an input, so the behaviour depends on
* external wiring.
*/
#include <linux/module.h>

154
drivers/pwm/pwm-tiehrpwm.c
View File

@ -36,7 +36,7 @@
#define CLKDIV_MAX 7
#define HSPCLKDIV_MAX 7
#define PERIOD_MAX 0xFFFF
#define PERIOD_MAX 0x10000
/* compare module registers */
#define CMPA 0x12
@ -65,14 +65,10 @@
#define AQCTL_ZRO_FRCHIGH BIT(1)
#define AQCTL_ZRO_FRCTOGGLE (BIT(1) | BIT(0))
#define AQCTL_CHANA_POLNORMAL (AQCTL_CAU_FRCLOW | AQCTL_PRD_FRCHIGH | \
AQCTL_ZRO_FRCHIGH)
#define AQCTL_CHANA_POLINVERSED (AQCTL_CAU_FRCHIGH | AQCTL_PRD_FRCLOW | \
AQCTL_ZRO_FRCLOW)
#define AQCTL_CHANB_POLNORMAL (AQCTL_CBU_FRCLOW | AQCTL_PRD_FRCHIGH | \
AQCTL_ZRO_FRCHIGH)
#define AQCTL_CHANB_POLINVERSED (AQCTL_CBU_FRCHIGH | AQCTL_PRD_FRCLOW | \
AQCTL_ZRO_FRCLOW)
#define AQCTL_CHANA_POLNORMAL (AQCTL_CAU_FRCLOW | AQCTL_ZRO_FRCHIGH)
#define AQCTL_CHANA_POLINVERSED (AQCTL_CAU_FRCHIGH | AQCTL_ZRO_FRCLOW)
#define AQCTL_CHANB_POLNORMAL (AQCTL_CBU_FRCLOW | AQCTL_ZRO_FRCHIGH)
#define AQCTL_CHANB_POLINVERSED (AQCTL_CBU_FRCHIGH | AQCTL_ZRO_FRCLOW)
#define AQSFRC_RLDCSF_MASK (BIT(7) | BIT(6))
#define AQSFRC_RLDCSF_ZRO 0
@ -108,7 +104,6 @@ struct ehrpwm_pwm_chip {
unsigned long clk_rate;
void __iomem *mmio_base;
unsigned long period_cycles[NUM_PWM_CHANNEL];
enum pwm_polarity polarity[NUM_PWM_CHANNEL];
struct clk *tbclk;
struct ehrpwm_context ctx;
};
@ -166,7 +161,7 @@ static int set_prescale_div(unsigned long rqst_prescaler, u16 *prescale_div,
*prescale_div = (1 << clkdiv) *
(hspclkdiv ? (hspclkdiv * 2) : 1);
if (*prescale_div > rqst_prescaler) {
if (*prescale_div >= rqst_prescaler) {
*tb_clk_div = (clkdiv << TBCTL_CLKDIV_SHIFT) |
(hspclkdiv << TBCTL_HSPCLKDIV_SHIFT);
return 0;
@ -177,51 +172,20 @@ static int set_prescale_div(unsigned long rqst_prescaler, u16 *prescale_div,
return 1;
}
static void configure_polarity(struct ehrpwm_pwm_chip *pc, int chan)
{
u16 aqctl_val, aqctl_mask;
unsigned int aqctl_reg;
/*
* Configure PWM output to HIGH/LOW level on counter
* reaches compare register value and LOW/HIGH level
* on counter value reaches period register value and
* zero value on counter
*/
if (chan == 1) {
aqctl_reg = AQCTLB;
aqctl_mask = AQCTL_CBU_MASK;
if (pc->polarity[chan] == PWM_POLARITY_INVERSED)
aqctl_val = AQCTL_CHANB_POLINVERSED;
else
aqctl_val = AQCTL_CHANB_POLNORMAL;
} else {
aqctl_reg = AQCTLA;
aqctl_mask = AQCTL_CAU_MASK;
if (pc->polarity[chan] == PWM_POLARITY_INVERSED)
aqctl_val = AQCTL_CHANA_POLINVERSED;
else
aqctl_val = AQCTL_CHANA_POLNORMAL;
}
aqctl_mask |= AQCTL_PRD_MASK | AQCTL_ZRO_MASK;
ehrpwm_modify(pc->mmio_base, aqctl_reg, aqctl_mask, aqctl_val);
}
/*
* period_ns = 10^9 * (ps_divval * period_cycles) / PWM_CLK_RATE
* duty_ns = 10^9 * (ps_divval * duty_cycles) / PWM_CLK_RATE
*/
static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
u64 duty_ns, u64 period_ns)
u64 duty_ns, u64 period_ns, enum pwm_polarity polarity)
{
struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
u32 period_cycles, duty_cycles;
u16 ps_divval, tb_divval;
unsigned int i, cmp_reg;
unsigned long long c;
u16 aqctl_val, aqctl_mask;
unsigned int aqctl_reg;
if (period_ns > NSEC_PER_SEC)
return -ERANGE;
@ -231,15 +195,10 @@ static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
do_div(c, NSEC_PER_SEC);
period_cycles = (unsigned long)c;
if (period_cycles < 1) {
period_cycles = 1;
duty_cycles = 1;
} else {
c = pc->clk_rate;
c = c * duty_ns;
do_div(c, NSEC_PER_SEC);
duty_cycles = (unsigned long)c;
}
c = pc->clk_rate;
c = c * duty_ns;
do_div(c, NSEC_PER_SEC);
duty_cycles = (unsigned long)c;
/*
* Period values should be same for multiple PWM channels as IP uses
@ -265,56 +224,77 @@ static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
pc->period_cycles[pwm->hwpwm] = period_cycles;
/* Configure clock prescaler to support Low frequency PWM wave */
if (set_prescale_div(period_cycles/PERIOD_MAX, &ps_divval,
if (set_prescale_div(DIV_ROUND_UP(period_cycles, PERIOD_MAX), &ps_divval,
&tb_divval)) {
dev_err(pwmchip_parent(chip), "Unsupported values\n");
return -EINVAL;
}
/* Update period & duty cycle with presacler division */
period_cycles = period_cycles / ps_divval;
duty_cycles = duty_cycles / ps_divval;
if (period_cycles < 1)
period_cycles = 1;
pm_runtime_get_sync(pwmchip_parent(chip));
/* Update clock prescaler values */
ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CLKDIV_MASK, tb_divval);
/* Update period & duty cycle with presacler division */
period_cycles = period_cycles / ps_divval;
duty_cycles = duty_cycles / ps_divval;
if (pwm->hwpwm == 1) {
/* Channel 1 configured with compare B register */
cmp_reg = CMPB;
aqctl_reg = AQCTLB;
aqctl_mask = AQCTL_CBU_MASK;
if (polarity == PWM_POLARITY_INVERSED)
aqctl_val = AQCTL_CHANB_POLINVERSED;
else
aqctl_val = AQCTL_CHANB_POLNORMAL;
/* if duty_cycle is big, don't toggle on CBU */
if (duty_cycles > period_cycles)
aqctl_val &= ~AQCTL_CBU_MASK;
} else {
/* Channel 0 configured with compare A register */
cmp_reg = CMPA;
aqctl_reg = AQCTLA;
aqctl_mask = AQCTL_CAU_MASK;
if (polarity == PWM_POLARITY_INVERSED)
aqctl_val = AQCTL_CHANA_POLINVERSED;
else
aqctl_val = AQCTL_CHANA_POLNORMAL;
/* if duty_cycle is big, don't toggle on CAU */
if (duty_cycles > period_cycles)
aqctl_val &= ~AQCTL_CAU_MASK;
}
aqctl_mask |= AQCTL_PRD_MASK | AQCTL_ZRO_MASK;
ehrpwm_modify(pc->mmio_base, aqctl_reg, aqctl_mask, aqctl_val);
/* Configure shadow loading on Period register */
ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_PRDLD_MASK, TBCTL_PRDLD_SHDW);
ehrpwm_write(pc->mmio_base, TBPRD, period_cycles);
ehrpwm_write(pc->mmio_base, TBPRD, period_cycles - 1);
/* Configure ehrpwm counter for up-count mode */
ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CTRMODE_MASK,
TBCTL_CTRMODE_UP);
if (pwm->hwpwm == 1)
/* Channel 1 configured with compare B register */
cmp_reg = CMPB;
else
/* Channel 0 configured with compare A register */
cmp_reg = CMPA;
ehrpwm_write(pc->mmio_base, cmp_reg, duty_cycles);
if (!(duty_cycles > period_cycles))
ehrpwm_write(pc->mmio_base, cmp_reg, duty_cycles);
pm_runtime_put_sync(pwmchip_parent(chip));
return 0;
}
static int ehrpwm_pwm_set_polarity(struct pwm_chip *chip,
struct pwm_device *pwm,
enum pwm_polarity polarity)
{
struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
/* Configuration of polarity in hardware delayed, do at enable */
pc->polarity[pwm->hwpwm] = polarity;
return 0;
}
static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
@ -339,9 +319,6 @@ static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);
/* Channels polarity can be configured from action qualifier module */
configure_polarity(pc, pwm->hwpwm);
/* Enable TBCLK */
ret = clk_enable(pc->tbclk);
if (ret) {
@ -391,12 +368,7 @@ static void ehrpwm_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
{
struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
if (pwm_is_enabled(pwm)) {
dev_warn(pwmchip_parent(chip), "Removing PWM device without disabling\n");
pm_runtime_put_sync(pwmchip_parent(chip));
}
/* set period value to zero on free */
/* Don't let a pwm without consumer block requests to the other channel */
pc->period_cycles[pwm->hwpwm] = 0;
}
@ -411,10 +383,6 @@ static int ehrpwm_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
ehrpwm_pwm_disable(chip, pwm);
enabled = false;
}
err = ehrpwm_pwm_set_polarity(chip, pwm, state->polarity);
if (err)
return err;
}
if (!state->enabled) {
@ -423,7 +391,7 @@ static int ehrpwm_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
return 0;
}
err = ehrpwm_pwm_config(chip, pwm, state->duty_cycle, state->period);
err = ehrpwm_pwm_config(chip, pwm, state->duty_cycle, state->period, state->polarity);
if (err)
return err;

3
include/linux/pwm.h
View File

@ -5,6 +5,7 @@
#include <linux/cdev.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
@ -321,6 +322,7 @@ struct pwm_ops {
* @npwm: number of PWMs controlled by this chip
* @of_xlate: request a PWM device given a device tree PWM specifier
* @atomic: can the driver's ->apply() be called in atomic context
* @gpio: &struct gpio_chip to operate this PWM chip's lines as GPO
* @uses_pwmchip_alloc: signals if pwmchip_allow was used to allocate this chip
* @operational: signals if the chip can be used (or is already deregistered)
* @nonatomic_lock: mutex for nonatomic chips
@ -340,6 +342,7 @@ struct pwm_chip {
bool atomic;
/* only used internally by the PWM framework */
struct gpio_chip gpio;
bool uses_pwmchip_alloc;
bool operational;
union {