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drm/amd/display: Implement secure display on DCN21
[Why] Porting secure display feature from DCN10 to DCN21. Support single display for now and will extend to multiple displays. [How] - use workqueue to offload works for dmub or dmcu firmware - after receiving ROI update from userspace, set skip_frame_cnt to 1 - refactor amdgpu_dm_crtc_handle_crc_window_irq() - disable PSR before activating secure_display on a crtc - check if secure_display is activated before enabling psr - only work for single display for now. Tested-by: Mark Broadworth <mark.broadworth@amd.com> Reviewed-by: Wayne Lin <Wayne.Lin@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alan Liu
Alex Deucher
parent
d1bc26cb5c
commit
c0459bddd1
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@ -7840,6 +7840,9 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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*/
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if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
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acrtc_attach->dm_irq_params.allow_psr_entry &&
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#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
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!amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
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#endif
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!acrtc_state->stream->link->psr_settings.psr_allow_active)
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amdgpu_dm_psr_enable(acrtc_state->stream);
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} else {
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@ -8301,8 +8304,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
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#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
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if (amdgpu_dm_crc_window_is_activated(crtc)) {
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spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
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acrtc->dm_irq_params.crc_window.update_win = true;
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acrtc->dm_irq_params.crc_window.skip_frame_cnt = 2;
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acrtc->dm_irq_params.window_param.update_win = true;
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acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
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spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock);
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crc_rd_wrk->crtc = crtc;
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spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock);
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@ -89,13 +89,13 @@ static void amdgpu_dm_set_crc_window_default(struct drm_crtc *crtc)
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struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
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spin_lock_irq(&drm_dev->event_lock);
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acrtc->dm_irq_params.crc_window.x_start = 0;
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acrtc->dm_irq_params.crc_window.y_start = 0;
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acrtc->dm_irq_params.crc_window.x_end = 0;
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acrtc->dm_irq_params.crc_window.y_end = 0;
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acrtc->dm_irq_params.crc_window.activated = false;
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acrtc->dm_irq_params.crc_window.update_win = false;
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acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0;
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acrtc->dm_irq_params.window_param.roi.x_start = 0;
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acrtc->dm_irq_params.window_param.roi.y_start = 0;
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acrtc->dm_irq_params.window_param.roi.x_end = 0;
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acrtc->dm_irq_params.window_param.roi.y_end = 0;
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acrtc->dm_irq_params.window_param.activated = false;
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acrtc->dm_irq_params.window_param.update_win = false;
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acrtc->dm_irq_params.window_param.skip_frame_cnt = 0;
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spin_unlock_irq(&drm_dev->event_lock);
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}
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@ -135,6 +135,22 @@ static void amdgpu_dm_crtc_notify_ta_to_read(struct work_struct *work)
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}
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}
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static void
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amdgpu_dm_forward_crc_window(struct work_struct *work)
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{
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struct crc_fw_work *crc_fw_wrk;
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struct amdgpu_display_manager *dm;
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crc_fw_wrk = container_of(work, struct crc_fw_work, forward_roi_work);
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dm = crc_fw_wrk->dm;
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mutex_lock(&dm->dc_lock);
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dc_stream_forward_crc_window(dm->dc, &crc_fw_wrk->roi, crc_fw_wrk->stream, crc_fw_wrk->is_stop_cmd);
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mutex_unlock(&dm->dc_lock);
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kfree(crc_fw_wrk);
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}
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bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc)
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{
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struct drm_device *drm_dev = crtc->dev;
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@ -142,7 +158,7 @@ bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc)
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bool ret = false;
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spin_lock_irq(&drm_dev->event_lock);
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ret = acrtc->dm_irq_params.crc_window.activated;
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ret = acrtc->dm_irq_params.window_param.activated;
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spin_unlock_irq(&drm_dev->event_lock);
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return ret;
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@ -187,9 +203,11 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
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if (adev->dm.crc_rd_wrk) {
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flush_work(&adev->dm.crc_rd_wrk->notify_ta_work);
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spin_lock_irq(&adev->dm.crc_rd_wrk->crc_rd_work_lock);
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if (adev->dm.crc_rd_wrk->crtc == crtc) {
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dc_stream_stop_dmcu_crc_win_update(stream_state->ctx->dc,
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dm_crtc_state->stream);
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/* stop ROI update on this crtc */
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dc_stream_forward_crc_window(stream_state->ctx->dc,
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NULL, stream_state, true);
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adev->dm.crc_rd_wrk->crtc = NULL;
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}
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spin_unlock_irq(&adev->dm.crc_rd_wrk->crc_rd_work_lock);
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@ -439,14 +457,9 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc)
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enum amdgpu_dm_pipe_crc_source cur_crc_src;
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struct amdgpu_crtc *acrtc = NULL;
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struct amdgpu_device *adev = NULL;
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struct crc_rd_work *crc_rd_wrk = NULL;
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struct crc_params *crc_window = NULL, tmp_window;
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struct crc_rd_work *crc_rd_wrk;
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struct crc_fw_work *crc_fw_wrk;
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unsigned long flags1, flags2;
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struct crtc_position position;
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uint32_t v_blank;
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uint32_t v_back_porch;
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uint32_t crc_window_latch_up_line;
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struct dc_crtc_timing *timing_out;
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if (crtc == NULL)
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return;
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@ -458,74 +471,52 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc)
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spin_lock_irqsave(&drm_dev->event_lock, flags1);
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stream_state = acrtc->dm_irq_params.stream;
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cur_crc_src = acrtc->dm_irq_params.crc_src;
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timing_out = &stream_state->timing;
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/* Early return if CRC capture is not enabled. */
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if (!amdgpu_dm_is_valid_crc_source(cur_crc_src))
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goto cleanup;
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if (dm_is_crc_source_crtc(cur_crc_src)) {
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if (acrtc->dm_irq_params.crc_window.activated) {
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if (acrtc->dm_irq_params.crc_window.update_win) {
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if (acrtc->dm_irq_params.crc_window.skip_frame_cnt) {
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acrtc->dm_irq_params.crc_window.skip_frame_cnt -= 1;
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goto cleanup;
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}
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crc_window = &tmp_window;
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if (!dm_is_crc_source_crtc(cur_crc_src))
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goto cleanup;
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tmp_window.windowa_x_start =
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acrtc->dm_irq_params.crc_window.x_start;
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tmp_window.windowa_y_start =
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acrtc->dm_irq_params.crc_window.y_start;
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tmp_window.windowa_x_end =
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acrtc->dm_irq_params.crc_window.x_end;
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tmp_window.windowa_y_end =
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acrtc->dm_irq_params.crc_window.y_end;
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tmp_window.windowb_x_start =
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acrtc->dm_irq_params.crc_window.x_start;
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tmp_window.windowb_y_start =
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acrtc->dm_irq_params.crc_window.y_start;
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tmp_window.windowb_x_end =
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acrtc->dm_irq_params.crc_window.x_end;
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tmp_window.windowb_y_end =
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acrtc->dm_irq_params.crc_window.y_end;
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if (!acrtc->dm_irq_params.window_param.activated)
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goto cleanup;
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dc_stream_forward_dmcu_crc_window(stream_state->ctx->dc,
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stream_state, crc_window);
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if (acrtc->dm_irq_params.window_param.update_win) {
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if (acrtc->dm_irq_params.window_param.skip_frame_cnt) {
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acrtc->dm_irq_params.window_param.skip_frame_cnt -= 1;
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goto cleanup;
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}
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acrtc->dm_irq_params.crc_window.update_win = false;
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/* prepare work for dmub to update ROI */
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crc_fw_wrk = kzalloc(sizeof(*crc_fw_wrk), GFP_ATOMIC);
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if (!crc_fw_wrk)
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goto cleanup;
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dc_stream_get_crtc_position(stream_state->ctx->dc, &stream_state, 1,
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&position.vertical_count,
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&position.nominal_vcount);
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INIT_WORK(&crc_fw_wrk->forward_roi_work, amdgpu_dm_forward_crc_window);
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crc_fw_wrk->dm = &adev->dm;
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crc_fw_wrk->stream = stream_state;
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crc_fw_wrk->roi.x_start = acrtc->dm_irq_params.window_param.roi.x_start;
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crc_fw_wrk->roi.y_start = acrtc->dm_irq_params.window_param.roi.y_start;
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crc_fw_wrk->roi.x_end = acrtc->dm_irq_params.window_param.roi.x_end;
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crc_fw_wrk->roi.y_end = acrtc->dm_irq_params.window_param.roi.y_end;
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schedule_work(&crc_fw_wrk->forward_roi_work);
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v_blank = timing_out->v_total - timing_out->v_border_top -
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timing_out->v_addressable - timing_out->v_border_bottom;
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acrtc->dm_irq_params.window_param.update_win = false;
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acrtc->dm_irq_params.window_param.skip_frame_cnt = 1;
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v_back_porch = v_blank - timing_out->v_front_porch -
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timing_out->v_sync_width;
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} else {
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if (acrtc->dm_irq_params.window_param.skip_frame_cnt) {
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acrtc->dm_irq_params.window_param.skip_frame_cnt -= 1;
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goto cleanup;
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}
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crc_window_latch_up_line = v_back_porch + timing_out->v_sync_width;
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/* take 3 lines margin*/
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if ((position.vertical_count + 3) >= crc_window_latch_up_line)
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acrtc->dm_irq_params.crc_window.skip_frame_cnt = 1;
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else
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acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0;
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} else {
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if (acrtc->dm_irq_params.crc_window.skip_frame_cnt == 0) {
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if (adev->dm.crc_rd_wrk) {
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crc_rd_wrk = adev->dm.crc_rd_wrk;
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spin_lock_irqsave(&crc_rd_wrk->crc_rd_work_lock, flags2);
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crc_rd_wrk->phy_inst =
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stream_state->link->link_enc_hw_inst;
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spin_unlock_irqrestore(&crc_rd_wrk->crc_rd_work_lock, flags2);
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schedule_work(&crc_rd_wrk->notify_ta_work);
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}
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} else {
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acrtc->dm_irq_params.crc_window.skip_frame_cnt -= 1;
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}
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}
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if (adev->dm.crc_rd_wrk) {
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crc_rd_wrk = adev->dm.crc_rd_wrk;
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spin_lock_irqsave(&crc_rd_wrk->crc_rd_work_lock, flags2);
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crc_rd_wrk->phy_inst = stream_state->link->link_enc_hw_inst;
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spin_unlock_irqrestore(&crc_rd_wrk->crc_rd_work_lock, flags2);
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schedule_work(&crc_rd_wrk->notify_ta_work);
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}
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}
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@ -40,11 +40,8 @@ enum amdgpu_dm_pipe_crc_source {
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};
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#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
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struct crc_window_parm {
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uint16_t x_start;
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uint16_t y_start;
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uint16_t x_end;
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uint16_t y_end;
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struct crc_window_param {
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struct crc_region roi;
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/* CRC windwo is activated or not*/
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bool activated;
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/* Update crc window during vertical blank or not */
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@ -53,6 +50,7 @@ struct crc_window_parm {
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int skip_frame_cnt;
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};
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/* read_work for driver to call PSP to read */
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struct crc_rd_work {
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struct work_struct notify_ta_work;
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/* To protect crc_rd_work carried fields*/
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@ -60,6 +58,15 @@ struct crc_rd_work {
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struct drm_crtc *crtc;
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uint8_t phy_inst;
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};
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/* forward_work for driver to forward ROI to dmu */
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struct crc_fw_work {
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struct work_struct forward_roi_work;
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struct amdgpu_display_manager *dm;
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struct dc_stream_state *stream;
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struct crc_region roi;
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bool is_stop_cmd;
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};
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#endif
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static inline bool amdgpu_dm_is_valid_crc_source(enum amdgpu_dm_pipe_crc_source source)
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@ -127,6 +127,9 @@ static void vblank_control_worker(struct work_struct *work)
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amdgpu_dm_psr_disable(vblank_work->stream);
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} else if (vblank_work->stream->link->psr_settings.psr_feature_enabled &&
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!vblank_work->stream->link->psr_settings.psr_allow_active &&
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#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
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!amdgpu_dm_crc_window_is_activated(&vblank_work->acrtc->base) &&
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#endif
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vblank_work->acrtc->dm_irq_params.allow_psr_entry) {
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amdgpu_dm_psr_enable(vblank_work->stream);
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}
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@ -38,6 +38,10 @@
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#include "link_hwss.h"
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#include "dc/dc_dmub_srv.h"
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#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
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#include "amdgpu_dm_psr.h"
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#endif
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struct dmub_debugfs_trace_header {
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uint32_t entry_count;
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uint32_t reserved[3];
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@ -3081,8 +3085,8 @@ static int crc_win_x_start_set(void *data, u64 val)
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struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
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spin_lock_irq(&drm_dev->event_lock);
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acrtc->dm_irq_params.crc_window.x_start = (uint16_t) val;
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acrtc->dm_irq_params.crc_window.update_win = false;
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acrtc->dm_irq_params.window_param.roi.x_start = (uint16_t) val;
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acrtc->dm_irq_params.window_param.update_win = false;
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spin_unlock_irq(&drm_dev->event_lock);
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return 0;
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@ -3098,7 +3102,7 @@ static int crc_win_x_start_get(void *data, u64 *val)
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struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
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spin_lock_irq(&drm_dev->event_lock);
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*val = acrtc->dm_irq_params.crc_window.x_start;
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*val = acrtc->dm_irq_params.window_param.roi.x_start;
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spin_unlock_irq(&drm_dev->event_lock);
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return 0;
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@ -3118,8 +3122,8 @@ static int crc_win_y_start_set(void *data, u64 val)
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struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
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spin_lock_irq(&drm_dev->event_lock);
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acrtc->dm_irq_params.crc_window.y_start = (uint16_t) val;
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acrtc->dm_irq_params.crc_window.update_win = false;
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acrtc->dm_irq_params.window_param.roi.y_start = (uint16_t) val;
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acrtc->dm_irq_params.window_param.update_win = false;
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spin_unlock_irq(&drm_dev->event_lock);
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return 0;
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@ -3135,7 +3139,7 @@ static int crc_win_y_start_get(void *data, u64 *val)
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struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
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spin_lock_irq(&drm_dev->event_lock);
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*val = acrtc->dm_irq_params.crc_window.y_start;
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*val = acrtc->dm_irq_params.window_param.roi.y_start;
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spin_unlock_irq(&drm_dev->event_lock);
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return 0;
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@ -3154,8 +3158,8 @@ static int crc_win_x_end_set(void *data, u64 val)
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struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
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spin_lock_irq(&drm_dev->event_lock);
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acrtc->dm_irq_params.crc_window.x_end = (uint16_t) val;
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acrtc->dm_irq_params.crc_window.update_win = false;
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acrtc->dm_irq_params.window_param.roi.x_end = (uint16_t) val;
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acrtc->dm_irq_params.window_param.update_win = false;
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spin_unlock_irq(&drm_dev->event_lock);
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return 0;
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@ -3171,7 +3175,7 @@ static int crc_win_x_end_get(void *data, u64 *val)
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struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
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spin_lock_irq(&drm_dev->event_lock);
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*val = acrtc->dm_irq_params.crc_window.x_end;
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*val = acrtc->dm_irq_params.window_param.roi.x_end;
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spin_unlock_irq(&drm_dev->event_lock);
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return 0;
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@ -3190,8 +3194,8 @@ static int crc_win_y_end_set(void *data, u64 val)
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struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
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||||
|
||||
spin_lock_irq(&drm_dev->event_lock);
|
||||
acrtc->dm_irq_params.crc_window.y_end = (uint16_t) val;
|
||||
acrtc->dm_irq_params.crc_window.update_win = false;
|
||||
acrtc->dm_irq_params.window_param.roi.y_end = (uint16_t) val;
|
||||
acrtc->dm_irq_params.window_param.update_win = false;
|
||||
spin_unlock_irq(&drm_dev->event_lock);
|
||||
|
||||
return 0;
|
||||
|
|
@ -3207,7 +3211,7 @@ static int crc_win_y_end_get(void *data, u64 *val)
|
|||
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
|
||||
|
||||
spin_lock_irq(&drm_dev->event_lock);
|
||||
*val = acrtc->dm_irq_params.crc_window.y_end;
|
||||
*val = acrtc->dm_irq_params.window_param.roi.y_end;
|
||||
spin_unlock_irq(&drm_dev->event_lock);
|
||||
|
||||
return 0;
|
||||
|
|
@ -3230,31 +3234,38 @@ static int crc_win_update_set(void *data, u64 val)
|
|||
return 0;
|
||||
|
||||
if (val) {
|
||||
new_acrtc = to_amdgpu_crtc(new_crtc);
|
||||
mutex_lock(&adev->dm.dc_lock);
|
||||
/* PSR may write to OTG CRC window control register,
|
||||
* so close it before starting secure_display.
|
||||
*/
|
||||
amdgpu_dm_psr_disable(new_acrtc->dm_irq_params.stream);
|
||||
|
||||
spin_lock_irq(&adev_to_drm(adev)->event_lock);
|
||||
spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock);
|
||||
if (crc_rd_wrk->crtc) {
|
||||
old_crtc = crc_rd_wrk->crtc;
|
||||
old_acrtc = to_amdgpu_crtc(old_crtc);
|
||||
}
|
||||
new_acrtc = to_amdgpu_crtc(new_crtc);
|
||||
|
||||
if (old_crtc && old_crtc != new_crtc) {
|
||||
old_acrtc->dm_irq_params.crc_window.activated = false;
|
||||
old_acrtc->dm_irq_params.crc_window.update_win = false;
|
||||
old_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0;
|
||||
old_acrtc->dm_irq_params.window_param.activated = false;
|
||||
old_acrtc->dm_irq_params.window_param.update_win = false;
|
||||
old_acrtc->dm_irq_params.window_param.skip_frame_cnt = 0;
|
||||
|
||||
new_acrtc->dm_irq_params.crc_window.activated = true;
|
||||
new_acrtc->dm_irq_params.crc_window.update_win = true;
|
||||
new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0;
|
||||
new_acrtc->dm_irq_params.window_param.activated = true;
|
||||
new_acrtc->dm_irq_params.window_param.update_win = true;
|
||||
new_acrtc->dm_irq_params.window_param.skip_frame_cnt = 0;
|
||||
crc_rd_wrk->crtc = new_crtc;
|
||||
} else {
|
||||
new_acrtc->dm_irq_params.crc_window.activated = true;
|
||||
new_acrtc->dm_irq_params.crc_window.update_win = true;
|
||||
new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0;
|
||||
new_acrtc->dm_irq_params.window_param.activated = true;
|
||||
new_acrtc->dm_irq_params.window_param.update_win = true;
|
||||
new_acrtc->dm_irq_params.window_param.skip_frame_cnt = 0;
|
||||
crc_rd_wrk->crtc = new_crtc;
|
||||
}
|
||||
spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock);
|
||||
spin_unlock_irq(&adev_to_drm(adev)->event_lock);
|
||||
mutex_unlock(&adev->dm.dc_lock);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ struct dm_irq_params {
|
|||
#ifdef CONFIG_DEBUG_FS
|
||||
enum amdgpu_dm_pipe_crc_source crc_src;
|
||||
#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
|
||||
struct crc_window_parm crc_window;
|
||||
struct crc_window_param window_param;
|
||||
#endif
|
||||
#endif
|
||||
};
|
||||
|
|
|
|||
|
|
@ -491,86 +491,79 @@ bool dc_stream_get_crtc_position(struct dc *dc,
|
|||
}
|
||||
|
||||
#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
|
||||
bool dc_stream_forward_dmcu_crc_window(struct dc *dc, struct dc_stream_state *stream,
|
||||
struct crc_params *crc_window)
|
||||
static inline void
|
||||
dc_stream_forward_dmub_crc_window(struct dc_dmub_srv *dmub_srv,
|
||||
struct crc_region *roi, struct otg_phy_mux *mux_mapping, bool is_stop)
|
||||
{
|
||||
int i;
|
||||
struct dmcu *dmcu = dc->res_pool->dmcu;
|
||||
struct pipe_ctx *pipe;
|
||||
struct crc_region tmp_win, *crc_win;
|
||||
struct otg_phy_mux mapping_tmp, *mux_mapping;
|
||||
union dmub_rb_cmd cmd = {0};
|
||||
|
||||
/*crc window can't be null*/
|
||||
if (!crc_window)
|
||||
return false;
|
||||
cmd.secure_display.roi_info.phy_id = mux_mapping->phy_output_num;
|
||||
cmd.secure_display.roi_info.otg_id = mux_mapping->otg_output_num;
|
||||
|
||||
if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu))) {
|
||||
crc_win = &tmp_win;
|
||||
mux_mapping = &mapping_tmp;
|
||||
/*set crc window*/
|
||||
tmp_win.x_start = crc_window->windowa_x_start;
|
||||
tmp_win.y_start = crc_window->windowa_y_start;
|
||||
tmp_win.x_end = crc_window->windowa_x_end;
|
||||
tmp_win.y_end = crc_window->windowa_y_end;
|
||||
|
||||
for (i = 0; i < MAX_PIPES; i++) {
|
||||
pipe = &dc->current_state->res_ctx.pipe_ctx[i];
|
||||
if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
|
||||
break;
|
||||
}
|
||||
|
||||
/* Stream not found */
|
||||
if (i == MAX_PIPES)
|
||||
return false;
|
||||
|
||||
|
||||
/*set mux routing info*/
|
||||
mapping_tmp.phy_output_num = stream->link->link_enc_hw_inst;
|
||||
mapping_tmp.otg_output_num = pipe->stream_res.tg->inst;
|
||||
|
||||
dmcu->funcs->forward_crc_window(dmcu, crc_win, mux_mapping);
|
||||
if (is_stop) {
|
||||
cmd.secure_display.header.type = DMUB_CMD__SECURE_DISPLAY;
|
||||
cmd.secure_display.header.sub_type = DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE;
|
||||
} else {
|
||||
DC_LOG_DC("dmcu is not initialized");
|
||||
return false;
|
||||
cmd.secure_display.header.type = DMUB_CMD__SECURE_DISPLAY;
|
||||
cmd.secure_display.header.sub_type = DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY;
|
||||
cmd.secure_display.roi_info.x_start = roi->x_start;
|
||||
cmd.secure_display.roi_info.y_start = roi->y_start;
|
||||
cmd.secure_display.roi_info.x_end = roi->x_end;
|
||||
cmd.secure_display.roi_info.y_end = roi->y_end;
|
||||
}
|
||||
|
||||
return true;
|
||||
dc_dmub_srv_cmd_queue(dmub_srv, &cmd);
|
||||
dc_dmub_srv_cmd_execute(dmub_srv);
|
||||
}
|
||||
|
||||
bool dc_stream_stop_dmcu_crc_win_update(struct dc *dc, struct dc_stream_state *stream)
|
||||
static inline void
|
||||
dc_stream_forward_dmcu_crc_window(struct dmcu *dmcu,
|
||||
struct crc_region *roi, struct otg_phy_mux *mux_mapping, bool is_stop)
|
||||
{
|
||||
int i;
|
||||
struct dmcu *dmcu = dc->res_pool->dmcu;
|
||||
struct pipe_ctx *pipe;
|
||||
struct otg_phy_mux mapping_tmp, *mux_mapping;
|
||||
|
||||
if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu))) {
|
||||
mux_mapping = &mapping_tmp;
|
||||
|
||||
for (i = 0; i < MAX_PIPES; i++) {
|
||||
pipe = &dc->current_state->res_ctx.pipe_ctx[i];
|
||||
if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
|
||||
break;
|
||||
}
|
||||
|
||||
/* Stream not found */
|
||||
if (i == MAX_PIPES)
|
||||
return false;
|
||||
|
||||
|
||||
/*set mux routing info*/
|
||||
mapping_tmp.phy_output_num = stream->link->link_enc_hw_inst;
|
||||
mapping_tmp.otg_output_num = pipe->stream_res.tg->inst;
|
||||
|
||||
if (is_stop)
|
||||
dmcu->funcs->stop_crc_win_update(dmcu, mux_mapping);
|
||||
} else {
|
||||
DC_LOG_DC("dmcu is not initialized");
|
||||
return false;
|
||||
else
|
||||
dmcu->funcs->forward_crc_window(dmcu, roi, mux_mapping);
|
||||
}
|
||||
|
||||
bool
|
||||
dc_stream_forward_crc_window(struct dc *dc,
|
||||
struct crc_region *roi, struct dc_stream_state *stream, bool is_stop)
|
||||
{
|
||||
struct dmcu *dmcu;
|
||||
struct dc_dmub_srv *dmub_srv;
|
||||
struct otg_phy_mux mux_mapping;
|
||||
struct pipe_ctx *pipe;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < MAX_PIPES; i++) {
|
||||
pipe = &dc->current_state->res_ctx.pipe_ctx[i];
|
||||
if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
|
||||
break;
|
||||
}
|
||||
|
||||
/* Stream not found */
|
||||
if (i == MAX_PIPES)
|
||||
return false;
|
||||
|
||||
mux_mapping.phy_output_num = stream->link->link_enc_hw_inst;
|
||||
mux_mapping.otg_output_num = pipe->stream_res.tg->inst;
|
||||
|
||||
dmcu = dc->res_pool->dmcu;
|
||||
dmub_srv = dc->ctx->dmub_srv;
|
||||
|
||||
/* forward to dmub */
|
||||
if (dmub_srv)
|
||||
dc_stream_forward_dmub_crc_window(dmub_srv, roi, &mux_mapping, is_stop);
|
||||
/* forward to dmcu */
|
||||
else if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
|
||||
dc_stream_forward_dmcu_crc_window(dmcu, roi, &mux_mapping, is_stop);
|
||||
else
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
#endif
|
||||
#endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
|
||||
|
||||
/**
|
||||
* dc_stream_configure_crc() - Configure CRC capture for the given stream.
|
||||
|
|
|
|||
|
|
@ -521,10 +521,10 @@ bool dc_stream_get_crtc_position(struct dc *dc,
|
|||
unsigned int *nom_v_pos);
|
||||
|
||||
#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
|
||||
bool dc_stream_forward_dmcu_crc_window(struct dc *dc, struct dc_stream_state *stream,
|
||||
struct crc_params *crc_window);
|
||||
bool dc_stream_stop_dmcu_crc_win_update(struct dc *dc,
|
||||
struct dc_stream_state *stream);
|
||||
bool dc_stream_forward_crc_window(struct dc *dc,
|
||||
struct crc_region *roi,
|
||||
struct dc_stream_state *stream,
|
||||
bool is_stop);
|
||||
#endif
|
||||
|
||||
bool dc_stream_configure_crc(struct dc *dc,
|
||||
|
|
|
|||
|
|
@ -993,4 +993,18 @@ struct display_endpoint_id {
|
|||
enum display_endpoint_type ep_type;
|
||||
};
|
||||
|
||||
#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
|
||||
struct crc_region {
|
||||
uint16_t x_start;
|
||||
uint16_t y_start;
|
||||
uint16_t x_end;
|
||||
uint16_t y_end;
|
||||
};
|
||||
|
||||
struct otg_phy_mux {
|
||||
uint8_t phy_output_num;
|
||||
uint8_t otg_output_num;
|
||||
};
|
||||
#endif
|
||||
|
||||
#endif /* DC_TYPES_H_ */
|
||||
|
|
|
|||
|
|
@ -56,20 +56,6 @@ struct dmcu {
|
|||
bool auto_load_dmcu;
|
||||
};
|
||||
|
||||
#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
|
||||
struct crc_region {
|
||||
uint16_t x_start;
|
||||
uint16_t y_start;
|
||||
uint16_t x_end;
|
||||
uint16_t y_end;
|
||||
};
|
||||
|
||||
struct otg_phy_mux {
|
||||
uint8_t phy_output_num;
|
||||
uint8_t otg_output_num;
|
||||
};
|
||||
#endif
|
||||
|
||||
struct dmcu_funcs {
|
||||
bool (*dmcu_init)(struct dmcu *dmcu);
|
||||
bool (*load_iram)(struct dmcu *dmcu,
|
||||
|
|
|
|||
|
|
@ -729,6 +729,10 @@ enum dmub_cmd_type {
|
|||
/**
|
||||
* Command type used for all VBIOS interface commands.
|
||||
*/
|
||||
/**
|
||||
* Command type used for all SECURE_DISPLAY commands.
|
||||
*/
|
||||
DMUB_CMD__SECURE_DISPLAY = 85,
|
||||
|
||||
/**
|
||||
* Command type used to set DPIA HPD interrupt state
|
||||
|
|
@ -3143,6 +3147,24 @@ struct dmub_rb_cmd_get_usbc_cable_id {
|
|||
} data;
|
||||
};
|
||||
|
||||
enum dmub_cmd_secure_display_type {
|
||||
DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0,
|
||||
DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE,
|
||||
DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY
|
||||
};
|
||||
|
||||
struct dmub_rb_cmd_secure_display {
|
||||
struct dmub_cmd_header header;
|
||||
struct dmub_cmd_roi_info {
|
||||
uint16_t x_start;
|
||||
uint16_t x_end;
|
||||
uint16_t y_start;
|
||||
uint16_t y_end;
|
||||
uint8_t otg_id;
|
||||
uint8_t phy_id;
|
||||
} roi_info;
|
||||
};
|
||||
|
||||
/**
|
||||
* union dmub_rb_cmd - DMUB inbox command.
|
||||
*/
|
||||
|
|
@ -3347,6 +3369,10 @@ union dmub_rb_cmd {
|
|||
* Definition of a DMUB_CMD__QUERY_HPD_STATE command.
|
||||
*/
|
||||
struct dmub_rb_cmd_query_hpd_state query_hpd;
|
||||
/**
|
||||
* Definition of a DMUB_CMD__SECURE_DISPLAY command.
|
||||
*/
|
||||
struct dmub_rb_cmd_secure_display secure_display;
|
||||
/**
|
||||
* Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command.
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user