From df41d58048a51e0f9c9b7a3710349f23efbfe64b Mon Sep 17 00:00:00 2001 From: Antony Kurniawan Soemardi Date: Sun, 21 Sep 2025 03:08:01 +0000 Subject: [PATCH 1/6] ARM: dts: qcom: msm8960: reorder nodes and properties Reorder the nodes in qcom-msm8960.dtsi by unit address and sort properties, as recommended in the Devicetree style guide. This is a cosmetic change only, with no functional impact. Tested-by: Rudraksha Gupta Tested-by: Shinjo Park Signed-off-by: Antony Kurniawan Soemardi Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250921-msm8960-reorder-v2-1-26c478366d21@smankusors.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 857 ++++++++++++----------- 1 file changed, 436 insertions(+), 421 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index 6e272d5345a8..6884f7f5b118 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -15,6 +15,35 @@ / { compatible = "qcom,msm8960"; interrupt-parent = <&intc>; + clocks { + cxo_board: cxo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + clock-output-names = "cxo_board"; + }; + + pxo_board: pxo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + clock-output-names = "pxo_board"; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "sleep_clk"; + }; + }; + + cpu-pmu { + compatible = "qcom,krait-pmu"; + interrupts = ; + qcom,no-pc-write; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -22,9 +51,9 @@ cpus { cpu@0 { compatible = "qcom,krait"; + reg = <0>; enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; - reg = <0>; next-level-cache = <&l2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; @@ -32,9 +61,9 @@ cpu@0 { cpu@1 { compatible = "qcom,krait"; + reg = <1>; enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; - reg = <1>; next-level-cache = <&l2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; @@ -52,6 +81,411 @@ memory@80000000 { reg = <0x80000000 0>; }; + soc: soc { + compatible = "simple-bus"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + rpm: rpm@108000 { + compatible = "qcom,rpm-msm8960"; + reg = <0x108000 0x1000>; + qcom,ipc = <&l2cc 0x8 2>; + + interrupts = , + , + ; + interrupt-names = "ack", + "err", + "wakeup"; + }; + + ssbi: ssbi@500000 { + compatible = "qcom,ssbi"; + reg = <0x500000 0x1000>; + qcom,controller-type = "pmic-arbiter"; + }; + + qfprom: efuse@700000 { + compatible = "qcom,msm8960-qfprom", "qcom,qfprom"; + reg = <0x00700000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + tsens_calib: calib@404 { + reg = <0x404 0x10>; + }; + + tsens_backup: backup-calib@414 { + reg = <0x414 0x10>; + }; + }; + + msmgpio: pinctrl@800000 { + compatible = "qcom,msm8960-pinctrl"; + reg = <0x800000 0x4000>; + gpio-controller; + gpio-ranges = <&msmgpio 0 0 152>; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gcc: clock-controller@900000 { + compatible = "qcom,gcc-msm8960", "syscon"; + reg = <0x900000 0x4000>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&cxo_board>, + <&pxo_board>, + <&lcc PLL4>; + clock-names = "cxo", + "pxo", + "pll4"; + + tsens: thermal-sensor { + compatible = "qcom,msm8960-tsens"; + + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; + interrupts = ; + interrupt-names = "uplow"; + + #qcom,sensors = <5>; + #thermal-sensor-cells = <1>; + }; + }; + + intc: interrupt-controller@2000000 { + compatible = "qcom,msm-qgic2"; + reg = <0x02000000 0x1000>, + <0x02002000 0x1000>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + timer@200a000 { + compatible = "qcom,kpss-wdt-msm8960", "qcom,kpss-timer", + "qcom,msm-timer"; + reg = <0x0200a000 0x100>; + interrupts = , + , + ; + clock-frequency = <27000000>; + clocks = <&sleep_clk>; + clock-names = "sleep"; + cpu-offset = <0x80000>; + }; + + l2cc: clock-controller@2011000 { + compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon"; + reg = <0x2011000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + #clock-cells = <0>; + }; + + acc0: clock-controller@2088000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu0_aux"; + #clock-cells = <0>; + }; + + saw0: power-manager@2089000 { + compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; + + saw0_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; + }; + + acc1: clock-controller@2098000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu1_aux"; + #clock-cells = <0>; + }; + + saw1: power-manager@2099000 { + compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2"; + reg = <0x02099000 0x1000>, <0x02009000 0x1000>; + + saw1_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; + }; + + clock-controller@4000000 { + compatible = "qcom,mmcc-msm8960"; + reg = <0x4000000 0x1000>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + clocks = <&pxo_board>, + <&gcc PLL3>, + <&gcc PLL8_VOTE>, + <0>, + <0>, + <0>, + <0>, + <0>; + clock-names = "pxo", + "pll3", + "pll8_vote", + "dsi1pll", + "dsi1pllbyte", + "dsi2pll", + "dsi2pllbyte", + "hdmipll"; + }; + + sdcc3: mmc@12180000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x12180000 0x2000>; + arm,primecell-periphid = <0x00051180>; + interrupts = ; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <192000000>; + no-1-8-v; + vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; + dma-names = "tx", "rx"; + + status = "disabled"; + }; + + sdcc3bam: dma-controller@12182000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x12182000 0x4000>; + interrupts = ; + clocks = <&gcc SDC3_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + sdcc1: mmc@12400000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x12400000 0x2000>; + arm,primecell-periphid = <0x00051180>; + interrupts = ; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <96000000>; + non-removable; + cap-sd-highspeed; + cap-mmc-highspeed; + vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; + dma-names = "tx", "rx"; + + status = "disabled"; + }; + + sdcc1bam: dma-controller@12402000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x12402000 0x4000>; + interrupts = ; + clocks = <&gcc SDC1_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + usb1: usb@12500000 { + compatible = "qcom,ci-hdrc"; + reg = <0x12500000 0x200>, + <0x12500200 0x200>; + interrupts = ; + clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>; + clock-names = "core", "iface"; + assigned-clocks = <&gcc USB_HS1_XCVR_CLK>; + assigned-clock-rates = <60000000>; + resets = <&gcc USB_HS1_RESET>; + reset-names = "core"; + phy_type = "ulpi"; + ahb-burst-config = <0>; + phys = <&usb_hs1_phy>; + phy-names = "usb-phy"; + #reset-cells = <1>; + + status = "disabled"; + + ulpi { + usb_hs1_phy: phy { + compatible = "qcom,usb-hs-phy-msm8960", + "qcom,usb-hs-phy"; + clocks = <&sleep_clk>, <&cxo_board>; + clock-names = "sleep", "ref"; + resets = <&usb1 0>; + reset-names = "por"; + #phy-cells = <0>; + }; + }; + }; + + gsbi1: gsbi@16000000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x16000000 0x100>; + ranges; + cell-index = <1>; + clocks = <&gcc GSBI1_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + + gsbi1_spi: spi@16080000 { + compatible = "qcom,spi-qup-v1.1.1"; + reg = <0x16080000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + cs-gpios = <&msmgpio 8 0>; + clocks = <&gcc GSBI1_QUP_CLK>, + <&gcc GSBI1_H_CLK>; + clock-names = "core", + "iface"; + + status = "disabled"; + }; + }; + + gsbi3: gsbi@16200000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x16200000 0x100>; + ranges; + cell-index = <3>; + clocks = <&gcc GSBI3_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + + gsbi3_i2c: i2c@16280000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16280000 0x1000>; + pinctrl-0 = <&i2c3_default_state>; + pinctrl-1 = <&i2c3_sleep_state>; + pinctrl-names = "default", "sleep"; + interrupts = ; + clocks = <&gcc GSBI3_QUP_CLK>, + <&gcc GSBI3_H_CLK>; + clock-names = "core", + "iface"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + gsbi5: gsbi@16400000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x16400000 0x100>; + ranges; + cell-index = <5>; + clocks = <&gcc GSBI5_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + syscon-tcsr = <&tcsr>; + + status = "disabled"; + + gsbi5_serial: serial@16440000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16440000 0x1000>, + <0x16400000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI5_UART_CLK>, + <&gcc GSBI5_H_CLK>; + clock-names = "core", + "iface"; + + status = "disabled"; + }; + }; + + gsbi8: gsbi@1a000000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x1a000000 0x100>; + ranges; + cell-index = <8>; + clocks = <&gcc GSBI8_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + syscon-tcsr = <&tcsr>; + + status = "disabled"; + + gsbi8_serial: serial@1a040000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x1a040000 0x1000>, + <0x1a000000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI8_UART_CLK>, + <&gcc GSBI8_H_CLK>; + clock-names = "core", + "iface"; + + status = "disabled"; + }; + }; + + tcsr: syscon@1a400000 { + compatible = "qcom,tcsr-msm8960", "syscon"; + reg = <0x1a400000 0x100>; + }; + + rng@1a500000 { + compatible = "qcom,prng"; + reg = <0x1a500000 0x200>; + clocks = <&gcc PRNG_CLK>; + clock-names = "core"; + }; + + lcc: clock-controller@28000000 { + compatible = "qcom,lcc-msm8960"; + reg = <0x28000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&pxo_board>, + <&gcc PLL4_VOTE>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + clock-names = "pxo", + "pll4_vote", + "mi2s_codec_clk", + "codec_i2s_mic_codec_clk", + "spare_i2s_mic_codec_clk", + "codec_i2s_spkr_codec_clk", + "spare_i2s_spkr_codec_clk", + "pcm_codec_clk"; + }; + }; + thermal-zones { cpu0-thermal { polling-delay-passive = <250>; @@ -94,35 +528,6 @@ cpu_crit1: trip1 { }; }; - cpu-pmu { - compatible = "qcom,krait-pmu"; - interrupts = ; - qcom,no-pc-write; - }; - - clocks { - cxo_board: cxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - clock-output-names = "cxo_board"; - }; - - pxo_board: pxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - clock-output-names = "pxo_board"; - }; - - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "sleep_clk"; - }; - }; - /* Temporary fixed regulator */ vsdcc_fixed: vsdcc-regulator { compatible = "regulator-fixed"; @@ -131,395 +536,5 @@ vsdcc_fixed: vsdcc-regulator { regulator-max-microvolt = <2700000>; regulator-always-on; }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - intc: interrupt-controller@2000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x02000000 0x1000>, - <0x02002000 0x1000>; - }; - - timer@200a000 { - compatible = "qcom,kpss-wdt-msm8960", "qcom,kpss-timer", - "qcom,msm-timer"; - interrupts = , - , - ; - reg = <0x0200a000 0x100>; - clock-frequency = <27000000>; - clocks = <&sleep_clk>; - clock-names = "sleep"; - cpu-offset = <0x80000>; - }; - - qfprom: efuse@700000 { - compatible = "qcom,msm8960-qfprom", "qcom,qfprom"; - reg = <0x00700000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - tsens_calib: calib@404 { - reg = <0x404 0x10>; - }; - - tsens_backup: backup-calib@414 { - reg = <0x414 0x10>; - }; - }; - - msmgpio: pinctrl@800000 { - compatible = "qcom,msm8960-pinctrl"; - gpio-controller; - gpio-ranges = <&msmgpio 0 0 152>; - #gpio-cells = <2>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x800000 0x4000>; - }; - - gcc: clock-controller@900000 { - compatible = "qcom,gcc-msm8960", "syscon"; - #clock-cells = <1>; - #reset-cells = <1>; - reg = <0x900000 0x4000>; - clocks = <&cxo_board>, - <&pxo_board>, - <&lcc PLL4>; - clock-names = "cxo", "pxo", "pll4"; - - tsens: thermal-sensor { - compatible = "qcom,msm8960-tsens"; - - nvmem-cells = <&tsens_calib>, <&tsens_backup>; - nvmem-cell-names = "calib", "calib_backup"; - interrupts = ; - interrupt-names = "uplow"; - - #qcom,sensors = <5>; - #thermal-sensor-cells = <1>; - }; - }; - - lcc: clock-controller@28000000 { - compatible = "qcom,lcc-msm8960"; - reg = <0x28000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - clocks = <&pxo_board>, - <&gcc PLL4_VOTE>, - <0>, - <0>, <0>, - <0>, <0>, - <0>; - clock-names = "pxo", - "pll4_vote", - "mi2s_codec_clk", - "codec_i2s_mic_codec_clk", - "spare_i2s_mic_codec_clk", - "codec_i2s_spkr_codec_clk", - "spare_i2s_spkr_codec_clk", - "pcm_codec_clk"; - }; - - clock-controller@4000000 { - compatible = "qcom,mmcc-msm8960"; - reg = <0x4000000 0x1000>; - #clock-cells = <1>; - #power-domain-cells = <1>; - #reset-cells = <1>; - clocks = <&pxo_board>, - <&gcc PLL3>, - <&gcc PLL8_VOTE>, - <0>, - <0>, - <0>, - <0>, - <0>; - clock-names = "pxo", - "pll3", - "pll8_vote", - "dsi1pll", - "dsi1pllbyte", - "dsi2pll", - "dsi2pllbyte", - "hdmipll"; - }; - - l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon"; - reg = <0x2011000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&pxo_board>; - clock-names = "pll8_vote", "pxo"; - #clock-cells = <0>; - }; - - rpm: rpm@108000 { - compatible = "qcom,rpm-msm8960"; - reg = <0x108000 0x1000>; - qcom,ipc = <&l2cc 0x8 2>; - - interrupts = , - , - ; - interrupt-names = "ack", "err", "wakeup"; - }; - - acc0: clock-controller@2088000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02088000 0x1000>, <0x02008000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&pxo_board>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu0_aux"; - #clock-cells = <0>; - }; - - acc1: clock-controller@2098000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02098000 0x1000>, <0x02008000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&pxo_board>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu1_aux"; - #clock-cells = <0>; - }; - - saw0: power-manager@2089000 { - compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2"; - reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - - saw0_vreg: regulator { - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1300000>; - }; - }; - - saw1: power-manager@2099000 { - compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - - saw1_vreg: regulator { - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1300000>; - }; - }; - - gsbi5: gsbi@16400000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <5>; - reg = <0x16400000 0x100>; - clocks = <&gcc GSBI5_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon-tcsr = <&tcsr>; - - status = "disabled"; - - gsbi5_serial: serial@16440000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16440000 0x1000>, - <0x16400000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - - gsbi8: gsbi@1a000000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <8>; - reg = <0x1a000000 0x100>; - clocks = <&gcc GSBI8_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon-tcsr = <&tcsr>; - - status = "disabled"; - - gsbi8_serial: serial@1a040000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x1a040000 0x1000>, - <0x1a000000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI8_UART_CLK>, - <&gcc GSBI8_H_CLK>; - clock-names = "core", - "iface"; - - status = "disabled"; - }; - }; - - ssbi: ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - }; - - rng@1a500000 { - compatible = "qcom,prng"; - reg = <0x1a500000 0x200>; - clocks = <&gcc PRNG_CLK>; - clock-names = "core"; - }; - - sdcc3: mmc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x2000>; - interrupts = ; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <192000000>; - no-1-8-v; - vmmc-supply = <&vsdcc_fixed>; - dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; - dma-names = "tx", "rx"; - }; - - sdcc3bam: dma-controller@12182000 { - compatible = "qcom,bam-v1.3.0"; - reg = <0x12182000 0x4000>; - interrupts = ; - clocks = <&gcc SDC3_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - sdcc1: mmc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x2000>; - interrupts = ; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <96000000>; - non-removable; - cap-sd-highspeed; - cap-mmc-highspeed; - vmmc-supply = <&vsdcc_fixed>; - dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; - dma-names = "tx", "rx"; - }; - - sdcc1bam: dma-controller@12402000 { - compatible = "qcom,bam-v1.3.0"; - reg = <0x12402000 0x4000>; - interrupts = ; - clocks = <&gcc SDC1_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - tcsr: syscon@1a400000 { - compatible = "qcom,tcsr-msm8960", "syscon"; - reg = <0x1a400000 0x100>; - }; - - gsbi1: gsbi@16000000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <1>; - reg = <0x16000000 0x100>; - clocks = <&gcc GSBI1_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - status = "disabled"; - - gsbi1_spi: spi@16080000 { - compatible = "qcom,spi-qup-v1.1.1"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x16080000 0x1000>; - interrupts = ; - cs-gpios = <&msmgpio 8 0>; - - clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - - usb1: usb@12500000 { - compatible = "qcom,ci-hdrc"; - reg = <0x12500000 0x200>, - <0x12500200 0x200>; - interrupts = ; - clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>; - clock-names = "core", "iface"; - assigned-clocks = <&gcc USB_HS1_XCVR_CLK>; - assigned-clock-rates = <60000000>; - resets = <&gcc USB_HS1_RESET>; - reset-names = "core"; - phy_type = "ulpi"; - ahb-burst-config = <0>; - phys = <&usb_hs1_phy>; - phy-names = "usb-phy"; - #reset-cells = <1>; - status = "disabled"; - - ulpi { - usb_hs1_phy: phy { - compatible = "qcom,usb-hs-phy-msm8960", - "qcom,usb-hs-phy"; - clocks = <&sleep_clk>, <&cxo_board>; - clock-names = "sleep", "ref"; - resets = <&usb1 0>; - reset-names = "por"; - #phy-cells = <0>; - }; - }; - }; - - gsbi3: gsbi@16200000 { - compatible = "qcom,gsbi-v1.0.0"; - reg = <0x16200000 0x100>; - ranges; - cell-index = <3>; - clocks = <&gcc GSBI3_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - - gsbi3_i2c: i2c@16280000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x16280000 0x1000>; - pinctrl-0 = <&i2c3_default_state>; - pinctrl-1 = <&i2c3_sleep_state>; - pinctrl-names = "default", "sleep"; - interrupts = ; - clocks = <&gcc GSBI3_QUP_CLK>, - <&gcc GSBI3_H_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - }; }; #include "qcom-msm8960-pins.dtsi" From 34fc20c4844454765c8ba32fdc006a2246a3f246 Mon Sep 17 00:00:00 2001 From: Antony Kurniawan Soemardi Date: Sun, 21 Sep 2025 03:08:05 +0000 Subject: [PATCH 2/6] ARM: dts: qcom: msm8960: inline qcom-msm8960-pins.dtsi Inline qcom-msm8960-pins.dtsi into the main SoC dtsi. Most Qualcomm SoCs embed their TLMM definitions directly, with only msm8960 and apq8064 using a separate pins file. After this change, only apq8064 remains split. This is a cosmetic change only, with no functional impact. Tested-by: Rudraksha Gupta Tested-by: Shinjo Park Signed-off-by: Antony Kurniawan Soemardi Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250921-msm8960-reorder-v2-2-26c478366d21@smankusors.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8960-pins.dtsi | 61 ------------------- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 59 +++++++++++++++++- 2 files changed, 58 insertions(+), 62 deletions(-) delete mode 100644 arch/arm/boot/dts/qcom/qcom-msm8960-pins.dtsi diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960-pins.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960-pins.dtsi deleted file mode 100644 index f18753e9f5ef..000000000000 --- a/arch/arm/boot/dts/qcom/qcom-msm8960-pins.dtsi +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -&msmgpio { - i2c3_default_state: i2c3-default-state { - i2c3-pins { - pins = "gpio16", "gpio17"; - function = "gsbi3"; - drive-strength = <8>; - bias-disable; - }; - }; - - i2c3_sleep_state: i2c3-sleep-state { - i2c3-pins { - pins = "gpio16", "gpio17"; - function = "gpio"; - drive-strength = <2>; - bias-bus-hold; - }; - }; - - sdcc3_default_state: sdcc3-default-state { - clk-pins { - pins = "sdc3_clk"; - drive-strength = <8>; - bias-disable; - }; - - cmd-pins { - pins = "sdc3_cmd"; - drive-strength = <8>; - bias-pull-up; - }; - - data-pins { - pins = "sdc3_data"; - drive-strength = <8>; - bias-pull-up; - }; - }; - - sdcc3_sleep_state: sdcc3-sleep-state { - clk-pins { - pins = "sdc3_clk"; - drive-strength = <2>; - bias-disable; - }; - - cmd-pins { - pins = "sdc3_cmd"; - drive-strength = <2>; - bias-pull-up; - }; - - data-pins { - pins = "sdc3_data"; - drive-strength = <2>; - bias-pull-up; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index 6884f7f5b118..097baee47897 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -130,6 +130,64 @@ msmgpio: pinctrl@800000 { interrupts = ; interrupt-controller; #interrupt-cells = <2>; + + i2c3_default_state: i2c3-default-state { + i2c3-pins { + pins = "gpio16", "gpio17"; + function = "gsbi3"; + drive-strength = <8>; + bias-disable; + }; + }; + + i2c3_sleep_state: i2c3-sleep-state { + i2c3-pins { + pins = "gpio16", "gpio17"; + function = "gpio"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + sdcc3_default_state: sdcc3-default-state { + clk-pins { + pins = "sdc3_clk"; + drive-strength = <8>; + bias-disable; + }; + + cmd-pins { + pins = "sdc3_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + data-pins { + pins = "sdc3_data"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + sdcc3_sleep_state: sdcc3-sleep-state { + clk-pins { + pins = "sdc3_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc3_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc3_data"; + drive-strength = <2>; + bias-pull-up; + }; + }; }; gcc: clock-controller@900000 { @@ -537,4 +595,3 @@ vsdcc_fixed: vsdcc-regulator { regulator-always-on; }; }; -#include "qcom-msm8960-pins.dtsi" From f239a394f91086bef632e145346e05fe65eb6914 Mon Sep 17 00:00:00 2001 From: Antony Kurniawan Soemardi Date: Sun, 21 Sep 2025 03:08:08 +0000 Subject: [PATCH 3/6] ARM: dts: qcom: msm8960: add I2C nodes for gsbi10 and gsbi12 These are present on msm8960 and are required for devices such as the Sony Xperia SP, which has NFC wired to gsbi10 and various motion sensors wired to gsbi12. The nodes are added disabled by default. Signed-off-by: Antony Kurniawan Soemardi Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250921-msm8960-reorder-v2-3-26c478366d21@smankusors.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 96 ++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index 097baee47897..890b34bdf8c3 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -149,6 +149,42 @@ i2c3-pins { }; }; + i2c10_default_state: i2c10-default-state { + i2c10-pins { + pins = "gpio73", "gpio74"; + function = "gsbi10"; + drive-strength = <8>; + bias-disable; + }; + }; + + i2c10_sleep_state: i2c10-sleep-state { + i2c10-pins { + pins = "gpio73", "gpio74"; + function = "gpio"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + i2c12_default_state: i2c12-default-state { + i2c12-pins { + pins = "gpio44", "gpio45"; + function = "gsbi12"; + drive-strength = <8>; + bias-disable; + }; + }; + + i2c12_sleep_state: i2c12-sleep-state { + i2c12-pins { + pins = "gpio44", "gpio45"; + function = "gpio"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + sdcc3_default_state: sdcc3-default-state { clk-pins { pins = "sdc3_clk"; @@ -364,6 +400,36 @@ sdcc1bam: dma-controller@12402000 { qcom,ee = <0>; }; + gsbi12: gsbi@12480000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x12480000 0x100>; + ranges; + cell-index = <12>; + clocks = <&gcc GSBI12_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + + gsbi12_i2c: i2c@124a0000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x124a0000 0x1000>; + pinctrl-0 = <&i2c12_default_state>; + pinctrl-1 = <&i2c12_sleep_state>; + pinctrl-names = "default", "sleep"; + interrupts = ; + clocks = <&gcc GSBI12_QUP_CLK>, + <&gcc GSBI12_H_CLK>; + clock-names = "core", + "iface"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + usb1: usb@12500000 { compatible = "qcom,ci-hdrc"; reg = <0x12500000 0x200>, @@ -508,6 +574,36 @@ gsbi8_serial: serial@1a040000 { }; }; + gsbi10: gsbi@1a200000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x1a200000 0x100>; + ranges; + cell-index = <10>; + clocks = <&gcc GSBI10_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + + gsbi10_i2c: i2c@1a280000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x1a280000 0x1000>; + pinctrl-0 = <&i2c10_default_state>; + pinctrl-1 = <&i2c10_sleep_state>; + pinctrl-names = "default", "sleep"; + interrupts = ; + clocks = <&gcc GSBI10_QUP_CLK>, + <&gcc GSBI10_H_CLK>; + clock-names = "core", + "iface"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + tcsr: syscon@1a400000 { compatible = "qcom,tcsr-msm8960", "syscon"; reg = <0x1a400000 0x100>; From 47f46fa7328b8429d4c41dd98e0268ed906ab50f Mon Sep 17 00:00:00 2001 From: Antony Kurniawan Soemardi Date: Sun, 21 Sep 2025 03:08:12 +0000 Subject: [PATCH 4/6] ARM: dts: qcom: msm8960: add I2C nodes for gsbi1 and gsbi8 These are present on msm8960 and are required for devices such as the Casio G'zOne, which has NFC wired to gsbi1 and audio amplifier wired to gsbi8. The nodes are added disabled by default. Co-developed-by: Shinjo Park Signed-off-by: Shinjo Park Signed-off-by: Antony Kurniawan Soemardi Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250921-msm8960-reorder-v2-4-26c478366d21@smankusors.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 70 ++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index 890b34bdf8c3..0aaf60dcda64 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -131,6 +131,24 @@ msmgpio: pinctrl@800000 { interrupt-controller; #interrupt-cells = <2>; + i2c1_default_state: i2c1-default-state { + i2c1-pins { + pins = "gpio8", "gpio9"; + function = "gsbi1"; + drive-strength = <8>; + bias-disable; + }; + }; + + i2c1_sleep_state: i2c1-sleep-state { + i2c1-pins { + pins = "gpio8", "gpio9"; + function = "gpio"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + i2c3_default_state: i2c3-default-state { i2c3-pins { pins = "gpio16", "gpio17"; @@ -149,6 +167,24 @@ i2c3-pins { }; }; + i2c8_default_state: i2c8-default-state { + i2c8-pins { + pins = "gpio36", "gpio37"; + function = "gsbi8"; + drive-strength = <8>; + bias-disable; + }; + }; + + i2c8_sleep_state: i2c8-sleep-state { + i2c8-pins { + pins = "gpio36", "gpio37"; + function = "gpio"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + i2c10_default_state: i2c10-default-state { i2c10-pins { pins = "gpio73", "gpio74"; @@ -474,6 +510,23 @@ gsbi1: gsbi@16000000 { status = "disabled"; + gsbi1_i2c: i2c@16080000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16080000 0x1000>; + pinctrl-0 = <&i2c1_default_state>; + pinctrl-1 = <&i2c1_sleep_state>; + pinctrl-names = "default", "sleep"; + interrupts = ; + clocks = <&gcc GSBI1_QUP_CLK>, + <&gcc GSBI1_H_CLK>; + clock-names = "core", + "iface"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + gsbi1_spi: spi@16080000 { compatible = "qcom,spi-qup-v1.1.1"; reg = <0x16080000 0x1000>; @@ -572,6 +625,23 @@ gsbi8_serial: serial@1a040000 { status = "disabled"; }; + + gsbi8_i2c: i2c@1a080000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x1a080000 0x1000>; + pinctrl-0 = <&i2c8_default_state>; + pinctrl-1 = <&i2c8_sleep_state>; + pinctrl-names = "default", "sleep"; + interrupts = ; + clocks = <&gcc GSBI8_QUP_CLK>, + <&gcc GSBI8_H_CLK>; + clock-names = "core", + "iface"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; }; gsbi10: gsbi@1a200000 { From d35984295d5ea5035c6255570716e68bdf826554 Mon Sep 17 00:00:00 2001 From: Antony Kurniawan Soemardi Date: Sun, 21 Sep 2025 03:08:15 +0000 Subject: [PATCH 5/6] ARM: dts: qcom: msm8960: rename msmgpio node to tlmm Rename the GPIO controller node from "msmgpio" to "tlmm" to match the convention used by other Qualcomm SoCs. Suggested-by: Shinjo Park Signed-off-by: Antony Kurniawan Soemardi Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250921-msm8960-reorder-v2-5-26c478366d21@smankusors.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts | 10 +++++----- .../dts/qcom/qcom-msm8960-samsung-expressatt.dts | 12 ++++++------ arch/arm/boot/dts/qcom/qcom-msm8960-sony-huashan.dts | 2 +- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 6 +++--- 4 files changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts index 36f4c997b0b3..1df078d7d89b 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts @@ -19,7 +19,7 @@ chosen { ext_l2: gpio-regulator { compatible = "regulator-fixed"; regulator-name = "ext_l2"; - gpio = <&msmgpio 91 0>; + gpio = <&tlmm 91 0>; startup-delay-us = <10000>; enable-active-high; }; @@ -38,12 +38,12 @@ &gsbi1_spi { ethernet@0 { compatible = "micrel,ks8851"; reg = <0>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <90 IRQ_TYPE_LEVEL_LOW>; spi-max-frequency = <5400000>; vdd-supply = <&ext_l2>; vdd-io-supply = <&pm8921_lvs6>; - reset-gpios = <&msmgpio 89 0>; + reset-gpios = <&tlmm 89 0>; }; }; @@ -56,7 +56,7 @@ &gsbi5_serial { status = "okay"; }; -&msmgpio { +&tlmm { spi1_default: spi1-default-state { mosi-pins { pins = "gpio6"; @@ -90,7 +90,7 @@ clk-pins { }; &pm8921 { - interrupts-extended = <&msmgpio 104 IRQ_TYPE_LEVEL_LOW>; + interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; }; &pm8921_keypad { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts b/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts index 49d117ea033a..5ee919dce75b 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts @@ -31,7 +31,7 @@ gpio-keys { key-home { label = "Home"; - gpios = <&msmgpio 40 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 40 GPIO_ACTIVE_LOW>; debounce-interval = <5>; linux,code = ; wakeup-event-action = ; @@ -40,14 +40,14 @@ key-home { key-volume-up { label = "Volume Up"; - gpios = <&msmgpio 50 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 50 GPIO_ACTIVE_LOW>; debounce-interval = <5>; linux,code = ; }; key-volume-down { label = "Volume Down"; - gpios = <&msmgpio 81 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 81 GPIO_ACTIVE_LOW>; debounce-interval = <5>; linux,code = ; }; @@ -102,7 +102,7 @@ &gsbi3_i2c { touchscreen@4a { compatible = "atmel,maxtouch"; reg = <0x4a>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <11 IRQ_TYPE_EDGE_FALLING>; vdda-supply = <&pm8921_lvs6>; vdd-supply = <&pm8921_l17>; @@ -111,7 +111,7 @@ touchscreen@4a { }; }; -&msmgpio { +&tlmm { spi1_default: spi1-default-state { mosi-pins { pins = "gpio6"; @@ -160,7 +160,7 @@ touchscreen: touchscreen-int-state { }; &pm8921 { - interrupts-extended = <&msmgpio 104 IRQ_TYPE_LEVEL_LOW>; + interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; }; &rpm { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960-sony-huashan.dts b/arch/arm/boot/dts/qcom/qcom-msm8960-sony-huashan.dts index f2f59fc8b9b6..591dc837e600 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960-sony-huashan.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8960-sony-huashan.dts @@ -54,7 +54,7 @@ &gsbi8_serial { }; &pm8921 { - interrupts-extended = <&msmgpio 104 IRQ_TYPE_LEVEL_LOW>; + interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; }; &pm8921_gpio { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index 0aaf60dcda64..38bd4fd8dda5 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -121,11 +121,11 @@ tsens_backup: backup-calib@414 { }; }; - msmgpio: pinctrl@800000 { + tlmm: pinctrl@800000 { compatible = "qcom,msm8960-pinctrl"; reg = <0x800000 0x4000>; gpio-controller; - gpio-ranges = <&msmgpio 0 0 152>; + gpio-ranges = <&tlmm 0 0 152>; #gpio-cells = <2>; interrupts = ; interrupt-controller; @@ -533,7 +533,7 @@ gsbi1_spi: spi@16080000 { #address-cells = <1>; #size-cells = <0>; interrupts = ; - cs-gpios = <&msmgpio 8 0>; + cs-gpios = <&tlmm 8 0>; clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; clock-names = "core", From 84df51667a196a0eadb22294eed1c6440241d74a Mon Sep 17 00:00:00 2001 From: Raymond Hackley Date: Sat, 11 Oct 2025 18:58:00 +0000 Subject: [PATCH 6/6] ARM: dts: qcom: msm8226-samsung-ms013g: add simple-framebuffer Add simple-framebuffer, necessary power-domains and clocks for ms013g. Signed-off-by: Raymond Hackley Link: https://lore.kernel.org/r/20251011185750.743615-1-raymondhackley@protonmail.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/qcom-msm8226-samsung-ms013g.dts | 31 ++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-ms013g.dts b/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-ms013g.dts index 08b50dc63923..80fe2916501a 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-ms013g.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-ms013g.dts @@ -13,13 +13,37 @@ / { chassis-type = "handset"; aliases { + display0 = &framebuffer0; mmc0 = &sdhc_1; /* SDC1 eMMC slot */ mmc1 = &sdhc_2; /* SDC2 SD card slot */ serial0 = &blsp1_uart3; }; chosen { - stdout-path = "serial0:115200n8"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + stdout-path = "display0"; + + framebuffer0: framebuffer@3200000 { + compatible = "simple-framebuffer"; + reg = <0x03200000 0x800000>; + memory-region = <&cont_splash_region>; + + width = <720>; + height = <1280>; + stride = <(720 * 3)>; + format = "r8g8b8"; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + power-domains = <&mmcc MDSS_GDSC>; + }; }; gpio-hall-sensor { @@ -93,6 +117,11 @@ reg_vdd_tsp_a: regulator-vdd-tsp-a { }; reserved-memory { + cont_splash_region: cont-splash@3200000 { + reg = <0x03200000 0x800000>; + no-map; + }; + smem_region: smem@fa00000 { reg = <0x0fa00000 0x100000>; no-map;