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crypto: qat - remove unused get_num_accels()

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The get_num_accels() hook in struct adf_hw_device_data has had no
callers since commit d237230728 ("crypto: qat - remove unused
character device and IOCTLs"), which deleted its last user in
adf_ctl_drv.c. Every device driver still populates it and two
implementations are still exported, all of it dead code.

Remove the hook, its generation-level implementations
adf_gen2_get_num_accels() and adf_gen4_get_num_accels(), the
per-device static implementations and all the assignments.

The hw_data->num_accel field is left untouched as it is still used.

Signed-off-by: Ahsan Atta <ahsan.atta@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Ahsan Atta 2026-10-01 13:28:41 +01:00 committed by Herbert Xu
parent 7d91d0ae0c
commit c01d396a91
14 changed files with 0 additions and 47 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c
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@ -443,7 +443,6 @@ void adf_init_hw_data_420xx(struct adf_hw_device_data *hw_data, u32 dev_id)
hw_data->enable_error_correction = adf_gen4_enable_error_correction;
hw_data->get_accel_mask = adf_gen4_get_accel_mask;
hw_data->get_ae_mask = get_ae_mask;
hw_data->get_num_accels = adf_gen4_get_num_accels;
hw_data->get_num_aes = adf_gen4_get_num_aes;
hw_data->get_sram_bar_id = adf_gen4_get_sram_bar_id;
hw_data->get_etr_bar_id = adf_gen4_get_etr_bar_id;

1
drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
View File

@ -412,7 +412,6 @@ void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data, u32 dev_id)
hw_data->enable_error_correction = adf_gen4_enable_error_correction;
hw_data->get_accel_mask = adf_gen4_get_accel_mask;
hw_data->get_ae_mask = get_ae_mask;
hw_data->get_num_accels = adf_gen4_get_num_accels;
hw_data->get_num_aes = adf_gen4_get_num_aes;
hw_data->get_sram_bar_id = adf_gen4_get_sram_bar_id;
hw_data->get_etr_bar_id = adf_gen4_get_etr_bar_id;

6
drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c
View File

@ -326,11 +326,6 @@ static u32 get_accel_mask(struct adf_hw_device_data *self)
return ADF_GEN6_ACCELERATORS_MASK;
}
static u32 get_num_accels(struct adf_hw_device_data *self)
{
return ADF_GEN6_MAX_ACCELERATORS;
}
static u32 get_num_aes(struct adf_hw_device_data *self)
{
return self ? hweight32(self->ae_mask) : 0;
@ -1023,7 +1018,6 @@ void adf_init_hw_data_6xxx(struct adf_hw_device_data *hw_data)
hw_data->enable_error_correction = enable_error_correction;
hw_data->get_accel_mask = get_accel_mask;
hw_data->get_ae_mask = get_ae_mask;
hw_data->get_num_accels = get_num_accels;
hw_data->get_num_aes = get_num_aes;
hw_data->get_sram_bar_id = get_sram_bar_id;
hw_data->get_etr_bar_id = get_etr_bar_id;

1
drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c
View File

@ -129,7 +129,6 @@ void adf_init_hw_data_c3xxx(struct adf_hw_device_data *hw_data)
hw_data->get_accel_mask = get_accel_mask;
hw_data->get_ae_mask = get_ae_mask;
hw_data->get_accel_cap = adf_gen2_get_accel_cap;
hw_data->get_num_accels = adf_gen2_get_num_accels;
hw_data->get_num_aes = adf_gen2_get_num_aes;
hw_data->get_sram_bar_id = get_sram_bar_id;
hw_data->get_etr_bar_id = get_etr_bar_id;

6
drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c
View File

@ -24,11 +24,6 @@ static u32 get_ae_mask(struct adf_hw_device_data *self)
return ADF_C3XXXIOV_ACCELENGINES_MASK;
}
static u32 get_num_accels(struct adf_hw_device_data *self)
{
return ADF_C3XXXIOV_MAX_ACCELERATORS;
}
static u32 get_num_aes(struct adf_hw_device_data *self)
{
return ADF_C3XXXIOV_MAX_ACCELENGINES;
@ -80,7 +75,6 @@ void adf_init_hw_data_c3xxxiov(struct adf_hw_device_data *hw_data)
hw_data->disable_iov = adf_vf2pf_notify_shutdown;
hw_data->get_accel_mask = get_accel_mask;
hw_data->get_ae_mask = get_ae_mask;
hw_data->get_num_accels = get_num_accels;
hw_data->get_num_aes = get_num_aes;
hw_data->get_etr_bar_id = get_etr_bar_id;
hw_data->get_misc_bar_id = get_misc_bar_id;

1
drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c
View File

@ -131,7 +131,6 @@ void adf_init_hw_data_c62x(struct adf_hw_device_data *hw_data)
hw_data->get_accel_mask = get_accel_mask;
hw_data->get_ae_mask = get_ae_mask;
hw_data->get_accel_cap = adf_gen2_get_accel_cap;
hw_data->get_num_accels = adf_gen2_get_num_accels;
hw_data->get_num_aes = adf_gen2_get_num_aes;
hw_data->get_sram_bar_id = get_sram_bar_id;
hw_data->get_etr_bar_id = get_etr_bar_id;

6
drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c
View File

@ -24,11 +24,6 @@ static u32 get_ae_mask(struct adf_hw_device_data *self)
return ADF_C62XIOV_ACCELENGINES_MASK;
}
static u32 get_num_accels(struct adf_hw_device_data *self)
{
return ADF_C62XIOV_MAX_ACCELERATORS;
}
static u32 get_num_aes(struct adf_hw_device_data *self)
{
return ADF_C62XIOV_MAX_ACCELENGINES;
@ -80,7 +75,6 @@ void adf_init_hw_data_c62xiov(struct adf_hw_device_data *hw_data)
hw_data->disable_iov = adf_vf2pf_notify_shutdown;
hw_data->get_accel_mask = get_accel_mask;
hw_data->get_ae_mask = get_ae_mask;
hw_data->get_num_accels = get_num_accels;
hw_data->get_num_aes = get_num_aes;
hw_data->get_etr_bar_id = get_etr_bar_id;
hw_data->get_misc_bar_id = get_misc_bar_id;

1
drivers/crypto/intel/qat/qat_common/adf_accel_devices.h
View File

@ -279,7 +279,6 @@ struct adf_hw_device_data {
u32 (*get_misc_bar_id)(struct adf_hw_device_data *self);
u32 (*get_etr_bar_id)(struct adf_hw_device_data *self);
u32 (*get_num_aes)(struct adf_hw_device_data *self);
u32 (*get_num_accels)(struct adf_hw_device_data *self);
void (*get_arb_info)(struct arb_info *arb_csrs_info);
void (*get_admin_info)(struct admin_info *admin_csrs_info);
enum dev_sku_info (*get_sku)(struct adf_hw_device_data *self);

9
drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c
View File

@ -7,15 +7,6 @@
#include "icp_qat_hw.h"
#include <linux/pci.h>
u32 adf_gen2_get_num_accels(struct adf_hw_device_data *self)
{
if (!self || !self->accel_mask)
return 0;
return hweight16(self->accel_mask);
}
EXPORT_SYMBOL_GPL(adf_gen2_get_num_accels);
u32 adf_gen2_get_num_aes(struct adf_hw_device_data *self)
{
if (!self || !self->ae_mask)

1
drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.h
View File

@ -78,7 +78,6 @@
#define ADF_GEN2_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30)
#define ADF_GEN2_SMIA1_MASK 0x1
u32 adf_gen2_get_num_accels(struct adf_hw_device_data *self);
u32 adf_gen2_get_num_aes(struct adf_hw_device_data *self);
void adf_gen2_enable_error_correction(struct adf_accel_dev *accel_dev);
void adf_gen2_cfg_iov_thds(struct adf_accel_dev *accel_dev, bool enable,

6
drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c
View File

@ -21,12 +21,6 @@ u32 adf_gen4_get_accel_mask(struct adf_hw_device_data *self)
}
EXPORT_SYMBOL_GPL(adf_gen4_get_accel_mask);
u32 adf_gen4_get_num_accels(struct adf_hw_device_data *self)
{
return ADF_GEN4_MAX_ACCELERATORS;
}
EXPORT_SYMBOL_GPL(adf_gen4_get_num_accels);
u32 adf_gen4_get_num_aes(struct adf_hw_device_data *self)
{
if (!self || !self->ae_mask)

1
drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h
View File

@ -157,7 +157,6 @@ void adf_gen4_get_arb_info(struct arb_info *arb_info);
u32 adf_gen4_get_etr_bar_id(struct adf_hw_device_data *self);
u32 adf_gen4_get_heartbeat_clock(struct adf_hw_device_data *self);
u32 adf_gen4_get_misc_bar_id(struct adf_hw_device_data *self);
u32 adf_gen4_get_num_accels(struct adf_hw_device_data *self);
u32 adf_gen4_get_num_aes(struct adf_hw_device_data *self);
enum dev_sku_info adf_gen4_get_sku(struct adf_hw_device_data *self);
u32 adf_gen4_get_sram_bar_id(struct adf_hw_device_data *self);

1
drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
View File

@ -229,7 +229,6 @@ void adf_init_hw_data_dh895xcc(struct adf_hw_device_data *hw_data)
hw_data->get_accel_mask = get_accel_mask;
hw_data->get_ae_mask = get_ae_mask;
hw_data->get_accel_cap = get_accel_cap;
hw_data->get_num_accels = adf_gen2_get_num_accels;
hw_data->get_num_aes = adf_gen2_get_num_aes;
hw_data->get_etr_bar_id = get_etr_bar_id;
hw_data->get_misc_bar_id = get_misc_bar_id;

6
drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c
View File

@ -24,11 +24,6 @@ static u32 get_ae_mask(struct adf_hw_device_data *self)
return ADF_DH895XCCIOV_ACCELENGINES_MASK;
}
static u32 get_num_accels(struct adf_hw_device_data *self)
{
return ADF_DH895XCCIOV_MAX_ACCELERATORS;
}
static u32 get_num_aes(struct adf_hw_device_data *self)
{
return ADF_DH895XCCIOV_MAX_ACCELENGINES;
@ -80,7 +75,6 @@ void adf_init_hw_data_dh895xcciov(struct adf_hw_device_data *hw_data)
hw_data->disable_iov = adf_vf2pf_notify_shutdown;
hw_data->get_accel_mask = get_accel_mask;
hw_data->get_ae_mask = get_ae_mask;
hw_data->get_num_accels = get_num_accels;
hw_data->get_num_aes = get_num_aes;
hw_data->get_etr_bar_id = get_etr_bar_id;
hw_data->get_misc_bar_id = get_misc_bar_id;