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clk: rockchip: rk3328: Set max parent rate for i2s fractional divider

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Set I2S clk parent to CPLL.

Change-Id: I2eaa920c6ab02cbec944b11f3aea2e7fe8551659
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang 2018-06-05 10:21:31 +08:00 committed by Tao Huang
parent f2a73282ea
commit bfacad511d
1 changed files with 8 additions and 6 deletions
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14
drivers/clk/rockchip/clk-rk3328.c
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@ -24,6 +24,7 @@
#define RK3328_GRF_SOC_STATUS0 0x480
#define RK3328_GRF_MAC_CON1 0x904
#define RK3328_GRF_MAC_CON2 0x908
#define RK3328_I2S_FRAC_MAX_PRATE 600000000
enum rk3328_plls {
apll, dpll, cpll, gpll, npll,
@ -217,6 +218,7 @@ PNAME(mux_mac2phy_src_p) = { "clk_mac2phy_src",
"phy_50m_out" };
PNAME(mux_mac2io_ext_p) = { "clk_mac2io",
"gmac_clkin" };
PNAME(mux_i2s_plls_p) = { "cpll", "dummy_gpll" };
static struct rockchip_pll_clock rk3328_pll_clks[] __initdata = {
[apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
@ -375,36 +377,36 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
RK3328_CLKGATE_CON(17), 13, GFLAGS),
/* PD_I2S */
COMPOSITE(0, "clk_i2s0_div", mux_2plls_p, 0,
COMPOSITE(0, "clk_i2s0_div", mux_i2s_plls_p, 0,
RK3328_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 7, DFLAGS,
RK3328_CLKGATE_CON(1), 1, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,
RK3328_CLKSEL_CON(7), 0,
RK3328_CLKGATE_CON(1), 2, GFLAGS,
&rk3328_i2s0_fracmux, 0),
&rk3328_i2s0_fracmux, RK3328_I2S_FRAC_MAX_PRATE),
GATE(SCLK_I2S0, "clk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
RK3328_CLKGATE_CON(1), 3, GFLAGS),
COMPOSITE(0, "clk_i2s1_div", mux_2plls_p, 0,
COMPOSITE(0, "clk_i2s1_div", mux_i2s_plls_p, 0,
RK3328_CLKSEL_CON(8), 15, 1, MFLAGS, 0, 7, DFLAGS,
RK3328_CLKGATE_CON(1), 4, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,
RK3328_CLKSEL_CON(9), 0,
RK3328_CLKGATE_CON(1), 5, GFLAGS,
&rk3328_i2s1_fracmux, 0),
&rk3328_i2s1_fracmux, RK3328_I2S_FRAC_MAX_PRATE),
GATE(SCLK_I2S1, "clk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
RK3328_CLKGATE_CON(1), 6, GFLAGS),
COMPOSITE_NODIV(SCLK_I2S1_OUT, "i2s1_out", mux_i2s1out_p, 0,
RK3328_CLKSEL_CON(8), 12, 1, MFLAGS,
RK3328_CLKGATE_CON(1), 7, GFLAGS),
COMPOSITE(0, "clk_i2s2_div", mux_2plls_p, 0,
COMPOSITE(0, "clk_i2s2_div", mux_i2s_plls_p, 0,
RK3328_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 7, DFLAGS,
RK3328_CLKGATE_CON(1), 8, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,
RK3328_CLKSEL_CON(11), 0,
RK3328_CLKGATE_CON(1), 9, GFLAGS,
&rk3328_i2s2_fracmux, 0),
&rk3328_i2s2_fracmux, RK3328_I2S_FRAC_MAX_PRATE),
GATE(SCLK_I2S2, "clk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
RK3328_CLKGATE_CON(1), 10, GFLAGS),
COMPOSITE_NODIV(SCLK_I2S2_OUT, "i2s2_out", mux_i2s2out_p, 0,