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drm/amdgpu/vcn5.0.1: read back register after written
The addition of register read-back in VCN v5.0.1 is intended to prevent potential race conditions. Reviewed-by: Ruijing Dong <ruijing.dong@amd.com> Signed-off-by: David (Ming Qiang) Wu <David.Wu3@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1038,6 +1038,11 @@ static int vcn_v5_0_1_start(struct amdgpu_vcn_inst *vinst)
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WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
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fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
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/* Keeping one read-back to ensure all register writes are done,
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* otherwise it may introduce race conditions.
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*/
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RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);
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return 0;
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}
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@ -1072,6 +1077,11 @@ static void vcn_v5_0_1_stop_dpg_mode(struct amdgpu_vcn_inst *vinst)
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/* disable dynamic power gating mode */
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WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0,
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~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
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/* Keeping one read-back to ensure all register writes are done,
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* otherwise it may introduce race conditions.
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*/
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RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);
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}
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/**
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@ -1147,6 +1157,11 @@ static int vcn_v5_0_1_stop(struct amdgpu_vcn_inst *vinst)
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/* clear status */
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WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0);
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/* Keeping one read-back to ensure all register writes are done,
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* otherwise it may introduce race conditions.
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*/
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RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);
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return 0;
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}
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