i2c: i801: Gate SPD instantiation on SPD Write Disable bit

When DDR5 memory modules are present, probing the spd5118 hub requires
page-selection write transactions. If the BIOS has set the SPD Write
Disable (SPD_WD) bit in SMBHSTCFG, the transaction fails and wedges the
controller into an unrecoverable "SMBus is busy" state.

Pass the PCH SPD Write Disable status into the SMBus core via
i2c_register_spd_write_disable(). This safely skips spd5118 instantiation
under write-protection while leaving legacy DDR4 (ee1004) functional.

Retain the original #ifdef CONFIG_I2C_I801_MUX preprocessor block around
mux_pdev to prevent compile-time regressions when the multiplexer driver
is disabled.

Closes: https://bugzilla.kernel.org/show_bug.cgi?id=213345
Co-developed-by: Saranya Gopal <saranya.gopal@intel.com>
Signed-off-by: Saranya Gopal <saranya.gopal@intel.com>
Signed-off-by: Yo-Jung <yo-jung@canonical.com>
Tested-by: Mark Pearson <mpearson-lenovo@squebb.ca>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://patch.msgid.link/20261013080603.808196-1-saranya.gopal@intel.com
This commit is contained in:
Yo-Jung 2026-10-13 13:36:03 +05:30 committed by Andi Shyti
parent 09753024bb
commit bf31dd72f0
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@ -1170,6 +1170,14 @@ static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
}
}
static void i801_register_spd(struct i801_priv *priv)
{
if (priv->original_hstcfg & SMBHSTCFG_SPD_WD)
i2c_register_spd_write_disable(&priv->adapter);
else
i2c_register_spd_write_enable(&priv->adapter);
}
/* Register optional targets */
static void i801_probe_optional_targets(struct i801_priv *priv)
{
@ -1193,7 +1201,7 @@ static void i801_probe_optional_targets(struct i801_priv *priv)
#ifdef CONFIG_I2C_I801_MUX
if (!priv->mux_pdev)
#endif
i2c_register_spd_write_enable(&priv->adapter);
i801_register_spd(priv);
}
#else
static void __init input_apanel_init(void) {}