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pinctrl: samsung: use add_pin_ranges method to add pinctrl ranges

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This is preferable since we can read the base in the global GPIO
numberspace from the chip instead of needing to select it ourselves.

Past versions could not do this, since they needed to add all the ranges
before enabling the pinctrl subsystem, which was done before registering
the GPIO chip. However, right now we enable the pinctrl subsystem after
registering the chip and so this became possible.

Signed-off-by: Mateusz Majewski <m.majewski2@samsung.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Tested-by: Sam Protsenko <semen.protsenko@linaro.org>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Link: https://lore.kernel.org/r/20231006125557.212681-3-m.majewski2@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Mateusz Majewski 2023-10-06 14:55:55 +02:00 committed by Krzysztof Kozlowski
parent 2aca5c591e
commit bf128c1f0f
2 changed files with 20 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
drivers/pinctrl/samsung/pinctrl-samsung.c
View File

@ -665,6 +665,21 @@ static int samsung_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
return (virq) ? : -ENXIO;
}
static int samsung_add_pin_ranges(struct gpio_chip *gc)
{
struct samsung_pin_bank *bank = gpiochip_get_data(gc);
bank->grange.name = bank->name;
bank->grange.id = bank->id;
bank->grange.pin_base = bank->drvdata->pin_base + bank->pin_base;
bank->grange.base = gc->base;
bank->grange.npins = bank->nr_pins;
bank->grange.gc = &bank->gpio_chip;
pinctrl_add_gpio_range(bank->drvdata->pctl_dev, &bank->grange);
return 0;
}
static struct samsung_pin_group *samsung_pinctrl_create_groups(
struct device *dev,
struct samsung_pinctrl_drv_data *drvdata,
@ -892,6 +907,7 @@ static int samsung_pinctrl_register(struct platform_device *pdev,
/* for each pin, the name of the pin is pin-bank name + pin number */
for (bank = 0; bank < drvdata->nr_banks; bank++) {
pin_bank = &drvdata->pin_banks[bank];
pin_bank->id = bank;
for (pin = 0; pin < pin_bank->nr_pins; pin++) {
sprintf(pin_names, "%s-%d", pin_bank->name, pin);
pdesc = pindesc + pin_bank->pin_base + pin;
@ -911,18 +927,6 @@ static int samsung_pinctrl_register(struct platform_device *pdev,
return ret;
}
for (bank = 0; bank < drvdata->nr_banks; ++bank) {
pin_bank = &drvdata->pin_banks[bank];
pin_bank->grange.name = pin_bank->name;
pin_bank->grange.id = bank;
pin_bank->grange.pin_base = drvdata->pin_base
+ pin_bank->pin_base;
pin_bank->grange.base = pin_bank->grange.pin_base;
pin_bank->grange.npins = pin_bank->nr_pins;
pin_bank->grange.gc = &pin_bank->gpio_chip;
pinctrl_add_gpio_range(drvdata->pctl_dev, &pin_bank->grange);
}
return 0;
}
@ -947,6 +951,7 @@ static const struct gpio_chip samsung_gpiolib_chip = {
.direction_input = samsung_gpio_direction_input,
.direction_output = samsung_gpio_direction_output,
.to_irq = samsung_gpio_to_irq,
.add_pin_ranges = samsung_add_pin_ranges,
.owner = THIS_MODULE,
};
@ -963,7 +968,7 @@ static int samsung_gpiolib_register(struct platform_device *pdev,
bank->gpio_chip = samsung_gpiolib_chip;
gc = &bank->gpio_chip;
gc->base = bank->grange.base;
gc->base = drvdata->pin_base + bank->pin_base;
gc->ngpio = bank->nr_pins;
gc->parent = &pdev->dev;
gc->fwnode = bank->fwnode;

2
drivers/pinctrl/samsung/pinctrl-samsung.h
View File

@ -148,6 +148,7 @@ struct samsung_pin_bank_data {
* @eint_mask: bit mask of pins which support EINT function.
* @eint_offset: SoC-specific EINT register or interrupt offset of bank.
* @name: name to be prefixed for each pin in this pin bank.
* @id: id of the bank, propagated to the pin range.
* @pin_base: starting pin number of the bank.
* @soc_priv: per-bank private data for SoC-specific code.
* @of_node: OF node of the bank.
@ -170,6 +171,7 @@ struct samsung_pin_bank {
u32 eint_mask;
u32 eint_offset;
const char *name;
u32 id;
u32 pin_base;
void *soc_priv;