github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-31 02:24:24 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

x86/mce, EDAC/mce_amd: Reorder SMCA bank type enums

Browse Source 
Originally, the SMCA bank type enums were ordered based on processor
documentation. However, the ordering became inconsistent after new bank
types were added over time.

Sort the bank type enums alphanumerically in most places.  Sort the
"enum to HWID/McaType" mapping by HWID/McaType. Drop redundant code
comments.

No functional changes.

  [ bp: Sort them alphanumerically. ]

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://patch.msgid.link/20260307163316.345923-2-yazen.ghannam@amd.com
This commit is contained in:
Yazen Ghannam 2026-03-07 11:33:14 -05:00 committed by Borislav Petkov (AMD)
parent 11439c4635
commit bee9f4178b
3 changed files with 98 additions and 112 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

55
arch/x86/include/asm/mce.h
View File

@ -343,44 +343,49 @@ extern void apei_mce_report_mem_error(int corrected,
*/
#ifdef CONFIG_X86_MCE_AMD
/* These may be used by multiple smca_hwid_mcatypes */
/*
* These may be used by multiple smca_hwid_mcatypes.
*
* Keep in alphanumeric order, numerals before letters.
* Exception: Keep "V2, etc." with their originals.
*/
enum smca_bank_types {
SMCA_LS = 0, /* Load Store */
SMCA_LS_V2,
SMCA_IF, /* Instruction Fetch */
SMCA_L2_CACHE, /* L2 Cache */
SMCA_DE, /* Decoder Unit */
SMCA_RESERVED, /* Reserved */
SMCA_EX, /* Execution Unit */
SMCA_FP, /* Floating Point */
SMCA_L3_CACHE, /* L3 Cache */
SMCA_CS, /* Coherent Slave */
SMCA_CS_V2,
SMCA_PIE, /* Power, Interrupts, etc. */
SMCA_UMC, /* Unified Memory Controller */
SMCA_UMC_V2,
SMCA_DE, /* Decoder Unit */
SMCA_EX, /* Execution Unit */
SMCA_FP, /* Floating Point */
SMCA_GMI_PCS, /* GMI PCS Unit */
SMCA_GMI_PHY, /* GMI PHY Unit */
SMCA_IF, /* Instruction Fetch */
SMCA_L2_CACHE, /* L2 Cache */
SMCA_L3_CACHE, /* L3 Cache */
SMCA_LS, /* Load Store */
SMCA_LS_V2,
SMCA_MA_LLC, /* Memory Attached Last Level Cache */
SMCA_PB, /* Parameter Block */
SMCA_PSP, /* Platform Security Processor */
SMCA_PSP_V2,
SMCA_SMU, /* System Management Unit */
SMCA_SMU_V2,
SMCA_MP5, /* Microprocessor 5 Unit */
SMCA_MPDMA, /* MPDMA Unit */
SMCA_NBIF, /* NBIF Unit */
SMCA_NBIO, /* Northbridge IO Unit */
SMCA_PB, /* Parameter Block */
SMCA_PCIE, /* PCI Express Unit */
SMCA_PCIE_V2,
SMCA_XGMI_PCS, /* xGMI PCS Unit */
SMCA_NBIF, /* NBIF Unit */
SMCA_SHUB, /* System HUB Unit */
SMCA_PIE, /* Power, Interrupts, etc. */
SMCA_PSP, /* Platform Security Processor */
SMCA_PSP_V2,
SMCA_RESERVED, /* Reserved */
SMCA_SATA, /* SATA Unit */
SMCA_SHUB, /* System HUB Unit */
SMCA_SMU, /* System Management Unit */
SMCA_SMU_V2,
SMCA_UMC, /* Unified Memory Controller */
SMCA_UMC_V2,
SMCA_USB, /* USB Unit */
SMCA_USR_DP, /* Ultra Short Reach Data Plane Controller */
SMCA_USR_CP, /* Ultra Short Reach Control Plane Controller */
SMCA_GMI_PCS, /* GMI PCS Unit */
SMCA_XGMI_PHY, /* xGMI PHY Unit */
SMCA_USR_DP, /* Ultra Short Reach Data Plane Controller */
SMCA_WAFL_PHY, /* WAFL PHY Unit */
SMCA_GMI_PHY, /* GMI PHY Unit */
SMCA_XGMI_PCS, /* xGMI PCS Unit */
SMCA_XGMI_PHY, /* xGMI PHY Unit */
N_SMCA_BANK_TYPES
};

117
arch/x86/kernel/cpu/mce/amd.c
View File

@ -95,39 +95,39 @@ static DEFINE_PER_CPU_READ_MOSTLY(struct smca_bank[MAX_NR_BANKS], smca_banks);
static DEFINE_PER_CPU_READ_MOSTLY(u8[N_SMCA_BANK_TYPES], smca_bank_counts);
static const char * const smca_names[] = {
[SMCA_LS ... SMCA_LS_V2] = "load_store",
[SMCA_IF] = "insn_fetch",
[SMCA_L2_CACHE] = "l2_cache",
[SMCA_CS ... SMCA_CS_V2] = "coherent_slave",
[SMCA_DE] = "decode_unit",
[SMCA_RESERVED] = "reserved",
[SMCA_EX] = "execution_unit",
[SMCA_FP] = "floating_point",
[SMCA_GMI_PCS] = "gmi_pcs",
[SMCA_GMI_PHY] = "gmi_phy",
[SMCA_IF] = "insn_fetch",
[SMCA_L2_CACHE] = "l2_cache",
[SMCA_L3_CACHE] = "l3_cache",
[SMCA_CS ... SMCA_CS_V2] = "coherent_slave",
[SMCA_LS ... SMCA_LS_V2] = "load_store",
[SMCA_MA_LLC] = "ma_llc",
[SMCA_MP5] = "mp5",
[SMCA_MPDMA] = "mpdma",
[SMCA_NBIF] = "nbif",
[SMCA_NBIO] = "nbio",
[SMCA_PB] = "param_block",
[SMCA_PCIE ... SMCA_PCIE_V2] = "pcie",
[SMCA_PIE] = "pie",
[SMCA_PSP ... SMCA_PSP_V2] = "psp",
[SMCA_RESERVED] = "reserved",
[SMCA_SATA] = "sata",
[SMCA_SHUB] = "shub",
[SMCA_SMU ... SMCA_SMU_V2] = "smu",
/* UMC v2 is separate because both of them can exist in a single system. */
[SMCA_UMC] = "umc",
[SMCA_UMC_V2] = "umc_v2",
[SMCA_MA_LLC] = "ma_llc",
[SMCA_PB] = "param_block",
[SMCA_PSP ... SMCA_PSP_V2] = "psp",
[SMCA_SMU ... SMCA_SMU_V2] = "smu",
[SMCA_MP5] = "mp5",
[SMCA_MPDMA] = "mpdma",
[SMCA_NBIO] = "nbio",
[SMCA_PCIE ... SMCA_PCIE_V2] = "pcie",
[SMCA_XGMI_PCS] = "xgmi_pcs",
[SMCA_NBIF] = "nbif",
[SMCA_SHUB] = "shub",
[SMCA_SATA] = "sata",
[SMCA_USB] = "usb",
[SMCA_USR_DP] = "usr_dp",
[SMCA_USR_CP] = "usr_cp",
[SMCA_GMI_PCS] = "gmi_pcs",
[SMCA_XGMI_PHY] = "xgmi_phy",
[SMCA_USR_DP] = "usr_dp",
[SMCA_WAFL_PHY] = "wafl_phy",
[SMCA_GMI_PHY] = "gmi_phy",
[SMCA_XGMI_PCS] = "xgmi_pcs",
[SMCA_XGMI_PHY] = "xgmi_phy",
};
static const char *smca_get_name(enum smca_bank_types t)
@ -153,68 +153,49 @@ enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank)
}
EXPORT_SYMBOL_GPL(smca_get_bank_type);
/*
* Format:
* { bank_type, hwid_mcatype }
*
* alphanumerically sorted by bank type.
*/
static const struct smca_hwid smca_hwid_mcatypes[] = {
/* { bank_type, hwid_mcatype } */
/* Reserved type */
{ SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0) },
/* ZN Core (HWID=0xB0) MCA types */
{ SMCA_LS, HWID_MCATYPE(0xB0, 0x0) },
{ SMCA_LS_V2, HWID_MCATYPE(0xB0, 0x10) },
{ SMCA_IF, HWID_MCATYPE(0xB0, 0x1) },
{ SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2) },
{ SMCA_CS, HWID_MCATYPE(0x2E, 0x0) },
{ SMCA_CS_V2, HWID_MCATYPE(0x2E, 0x2) },
{ SMCA_DE, HWID_MCATYPE(0xB0, 0x3) },
/* HWID 0xB0 MCATYPE 0x4 is Reserved */
{ SMCA_EX, HWID_MCATYPE(0xB0, 0x5) },
{ SMCA_FP, HWID_MCATYPE(0xB0, 0x6) },
{ SMCA_GMI_PCS, HWID_MCATYPE(0x241, 0x0) },
{ SMCA_GMI_PHY, HWID_MCATYPE(0x269, 0x0) },
{ SMCA_IF, HWID_MCATYPE(0xB0, 0x1) },
{ SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2) },
{ SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7) },
/* Data Fabric MCA types */
{ SMCA_CS, HWID_MCATYPE(0x2E, 0x0) },
{ SMCA_PIE, HWID_MCATYPE(0x2E, 0x1) },
{ SMCA_CS_V2, HWID_MCATYPE(0x2E, 0x2) },
{ SMCA_LS, HWID_MCATYPE(0xB0, 0x0) },
{ SMCA_LS_V2, HWID_MCATYPE(0xB0, 0x10) },
{ SMCA_MA_LLC, HWID_MCATYPE(0x2E, 0x4) },
/* Unified Memory Controller MCA type */
{ SMCA_UMC, HWID_MCATYPE(0x96, 0x0) },
{ SMCA_UMC_V2, HWID_MCATYPE(0x96, 0x1) },
/* Parameter Block MCA type */
{ SMCA_PB, HWID_MCATYPE(0x05, 0x0) },
/* Platform Security Processor MCA type */
{ SMCA_PSP, HWID_MCATYPE(0xFF, 0x0) },
{ SMCA_PSP_V2, HWID_MCATYPE(0xFF, 0x1) },
/* System Management Unit MCA type */
{ SMCA_SMU, HWID_MCATYPE(0x01, 0x0) },
{ SMCA_SMU_V2, HWID_MCATYPE(0x01, 0x1) },
/* Microprocessor 5 Unit MCA type */
{ SMCA_MP5, HWID_MCATYPE(0x01, 0x2) },
/* MPDMA MCA type */
{ SMCA_MPDMA, HWID_MCATYPE(0x01, 0x3) },
/* Northbridge IO Unit MCA type */
{ SMCA_NBIF, HWID_MCATYPE(0x6C, 0x0) },
{ SMCA_NBIO, HWID_MCATYPE(0x18, 0x0) },
/* PCI Express Unit MCA type */
{ SMCA_PB, HWID_MCATYPE(0x05, 0x0) },
{ SMCA_PCIE, HWID_MCATYPE(0x46, 0x0) },
{ SMCA_PCIE_V2, HWID_MCATYPE(0x46, 0x1) },
{ SMCA_XGMI_PCS, HWID_MCATYPE(0x50, 0x0) },
{ SMCA_NBIF, HWID_MCATYPE(0x6C, 0x0) },
{ SMCA_SHUB, HWID_MCATYPE(0x80, 0x0) },
{ SMCA_PIE, HWID_MCATYPE(0x2E, 0x1) },
{ SMCA_PSP, HWID_MCATYPE(0xFF, 0x0) },
{ SMCA_PSP_V2, HWID_MCATYPE(0xFF, 0x1) },
{ SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0) },
{ SMCA_SATA, HWID_MCATYPE(0xA8, 0x0) },
{ SMCA_SHUB, HWID_MCATYPE(0x80, 0x0) },
{ SMCA_SMU, HWID_MCATYPE(0x01, 0x0) },
{ SMCA_SMU_V2, HWID_MCATYPE(0x01, 0x1) },
{ SMCA_UMC, HWID_MCATYPE(0x96, 0x0) },
{ SMCA_UMC_V2, HWID_MCATYPE(0x96, 0x1) },
{ SMCA_USB, HWID_MCATYPE(0xAA, 0x0) },
{ SMCA_USR_DP, HWID_MCATYPE(0x170, 0x0) },
{ SMCA_USR_CP, HWID_MCATYPE(0x180, 0x0) },
{ SMCA_GMI_PCS, HWID_MCATYPE(0x241, 0x0) },
{ SMCA_XGMI_PHY, HWID_MCATYPE(0x259, 0x0) },
{ SMCA_USR_DP, HWID_MCATYPE(0x170, 0x0) },
{ SMCA_WAFL_PHY, HWID_MCATYPE(0x267, 0x0) },
{ SMCA_GMI_PHY, HWID_MCATYPE(0x269, 0x0) },
{ SMCA_XGMI_PCS, HWID_MCATYPE(0x50, 0x0) },
{ SMCA_XGMI_PHY, HWID_MCATYPE(0x259, 0x0) },
};
/*

38
drivers/edac/mce_amd.c
View File

@ -689,36 +689,36 @@ static void decode_mc6_mce(struct mce *m)
}
static const char * const smca_long_names[] = {
[SMCA_LS ... SMCA_LS_V2] = "Load Store Unit",
[SMCA_IF] = "Instruction Fetch Unit",
[SMCA_L2_CACHE] = "L2 Cache",
[SMCA_CS ... SMCA_CS_V2] = "Coherent Slave",
[SMCA_DE] = "Decode Unit",
[SMCA_RESERVED] = "Reserved",
[SMCA_EX] = "Execution Unit",
[SMCA_FP] = "Floating Point Unit",
[SMCA_GMI_PCS] = "Global Memory Interconnect PCS Unit",
[SMCA_GMI_PHY] = "Global Memory Interconnect PHY Unit",
[SMCA_IF] = "Instruction Fetch Unit",
[SMCA_L2_CACHE] = "L2 Cache",
[SMCA_L3_CACHE] = "L3 Cache",
[SMCA_CS ... SMCA_CS_V2] = "Coherent Slave",
[SMCA_LS ... SMCA_LS_V2] = "Load Store Unit",
[SMCA_MP5] = "Microprocessor 5 Unit",
[SMCA_MPDMA] = "MPDMA Unit",
[SMCA_NBIF] = "NBIF Unit",
[SMCA_NBIO] = "Northbridge IO Unit",
[SMCA_PB] = "Parameter Block",
[SMCA_PCIE ... SMCA_PCIE_V2] = "PCI Express Unit",
[SMCA_PIE] = "Power, Interrupts, etc.",
[SMCA_PSP ... SMCA_PSP_V2] = "Platform Security Processor",
[SMCA_RESERVED] = "Reserved",
[SMCA_SATA] = "SATA Unit",
[SMCA_SHUB] = "System Hub Unit",
[SMCA_SMU ... SMCA_SMU_V2] = "System Management Unit",
/* UMC v2 is separate because both of them can exist in a single system. */
[SMCA_UMC] = "Unified Memory Controller",
[SMCA_UMC_V2] = "Unified Memory Controller v2",
[SMCA_PB] = "Parameter Block",
[SMCA_PSP ... SMCA_PSP_V2] = "Platform Security Processor",
[SMCA_SMU ... SMCA_SMU_V2] = "System Management Unit",
[SMCA_MP5] = "Microprocessor 5 Unit",
[SMCA_MPDMA] = "MPDMA Unit",
[SMCA_NBIO] = "Northbridge IO Unit",
[SMCA_PCIE ... SMCA_PCIE_V2] = "PCI Express Unit",
[SMCA_XGMI_PCS] = "Ext Global Memory Interconnect PCS Unit",
[SMCA_NBIF] = "NBIF Unit",
[SMCA_SHUB] = "System Hub Unit",
[SMCA_SATA] = "SATA Unit",
[SMCA_USB] = "USB Unit",
[SMCA_GMI_PCS] = "Global Memory Interconnect PCS Unit",
[SMCA_XGMI_PHY] = "Ext Global Memory Interconnect PHY Unit",
[SMCA_WAFL_PHY] = "WAFL PHY Unit",
[SMCA_GMI_PHY] = "Global Memory Interconnect PHY Unit",
[SMCA_XGMI_PCS] = "Ext Global Memory Interconnect PCS Unit",
[SMCA_XGMI_PHY] = "Ext Global Memory Interconnect PHY Unit",
};
static const char *smca_get_long_name(enum smca_bank_types t)