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wifi: rtw89: debug: Wi-Fi 7 update simulation of SER L0/L1 by halt H2C command

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Wi-Fi 7 FW fixes support of triggering SER L0/L1 simulation via halt H2C
command on v0.35.108.0. After that, the halt H2C command trigger for
Wi-Fi 6 and Wi-Fi 7 can be the same. Update FW feature table and share the
halt H2C command trigger function between Wi-Fi 6 and Wi-Fi 7.

Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/20260515014433.16168-3-pkshih@realtek.com
This commit is contained in:
Zong-Zhe Yang 2026-05-15 09:44:22 +08:00 committed by Ping-Ke Shih
parent e384397796
commit becd1c37ef
2 changed files with 58 additions and 71 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

127
drivers/net/wireless/realtek/rtw89/debug.c
View File

@ -3543,53 +3543,13 @@ rtw89_debug_priv_early_h2c_set(struct rtw89_dev *rtwdev,
return count;
}
static int rtw89_dbg_trigger_l1_error_by_halt_h2c_ax(struct rtw89_dev *rtwdev)
{
if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))
return -EBUSY;
return rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L1_RESET_FORCE);
}
static int rtw89_dbg_trigger_l1_error_by_halt_h2c_be(struct rtw89_dev *rtwdev)
{
if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))
return -EBUSY;
rtw89_leave_ps_mode(rtwdev);
rtw89_write32_set(rtwdev, R_BE_FW_TRIGGER_IDCT_ISR,
B_BE_DMAC_FW_TRIG_IDCT | B_BE_DMAC_FW_ERR_IDCT_IMR);
return 0;
}
static int rtw89_dbg_trigger_l1_error_by_halt_h2c(struct rtw89_dev *rtwdev)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
switch (chip->chip_gen) {
case RTW89_CHIP_AX:
return rtw89_dbg_trigger_l1_error_by_halt_h2c_ax(rtwdev);
case RTW89_CHIP_BE:
return rtw89_dbg_trigger_l1_error_by_halt_h2c_be(rtwdev);
default:
return -EOPNOTSUPP;
}
}
static int rtw89_dbg_trigger_l1_error(struct rtw89_dev *rtwdev)
static int rtw89_dbg_trigger_l1_error_ax(struct rtw89_dev *rtwdev)
{
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
struct rtw89_cpuio_ctrl ctrl_para = {0};
struct rtw89_cpuio_ctrl ctrl_para = {};
u16 pkt_id;
int ret;
if (RTW89_CHK_FW_FEATURE(SIM_SER_L0L1_BY_HALT_H2C, &rtwdev->fw))
return rtw89_dbg_trigger_l1_error_by_halt_h2c(rtwdev);
rtw89_leave_ps_mode(rtwdev);
ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id);
if (ret)
return ret;
@ -3608,6 +3568,52 @@ static int rtw89_dbg_trigger_l1_error(struct rtw89_dev *rtwdev)
return 0;
}
static int rtw89_dbg_trigger_l1_error_be(struct rtw89_dev *rtwdev)
{
int ret;
ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
if (ret)
return ret;
rtw89_write32_set(rtwdev, R_BE_FW_TRIGGER_IDCT_ISR,
B_BE_DMAC_FW_TRIG_IDCT | B_BE_DMAC_FW_ERR_IDCT_IMR);
return 0;
}
static int rtw89_dbg_trigger_l1_error_by_halt_h2c(struct rtw89_dev *rtwdev)
{
if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))
return -EBUSY;
return rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L1_RESET_FORCE);
}
static int rtw89_dbg_trigger_l1_error(struct rtw89_dev *rtwdev)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
int (*sim_l1)(struct rtw89_dev *rtwdev);
switch (chip->chip_gen) {
case RTW89_CHIP_AX:
sim_l1 = rtw89_dbg_trigger_l1_error_ax;
break;
case RTW89_CHIP_BE:
sim_l1 = rtw89_dbg_trigger_l1_error_be;
break;
default:
return -EOPNOTSUPP;
}
if (RTW89_CHK_FW_FEATURE(SIM_SER_L0L1_BY_HALT_H2C, &rtwdev->fw))
return rtw89_dbg_trigger_l1_error_by_halt_h2c(rtwdev);
rtw89_leave_ps_mode(rtwdev);
return sim_l1(rtwdev);
}
static int rtw89_dbg_trigger_l0_error_ax(struct rtw89_dev *rtwdev)
{
u16 val16;
@ -3632,55 +3638,36 @@ static int rtw89_dbg_trigger_l0_error_ax(struct rtw89_dev *rtwdev)
static int rtw89_dbg_trigger_l0_error_be(struct rtw89_dev *rtwdev)
{
u8 val8;
int ret;
ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL);
if (ret)
return ret;
val8 = rtw89_read8(rtwdev, R_BE_CMAC_FUNC_EN);
rtw89_write8(rtwdev, R_BE_CMAC_FUNC_EN, val8 & ~B_BE_TMAC_EN);
mdelay(1);
rtw89_write8(rtwdev, R_BE_CMAC_FUNC_EN, val8);
return 0;
}
static int rtw89_dbg_trigger_l0_error_by_halt_h2c_ax(struct rtw89_dev *rtwdev)
{
if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))
return -EBUSY;
return rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L0_RESET_FORCE);
}
static int rtw89_dbg_trigger_l0_error_by_halt_h2c_be(struct rtw89_dev *rtwdev)
{
if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))
return -EBUSY;
rtw89_leave_ps_mode(rtwdev);
rtw89_write32_set(rtwdev, R_BE_CMAC_FW_TRIGGER_IDCT_ISR,
B_BE_CMAC_FW_TRIG_IDCT | B_BE_CMAC_FW_ERR_IDCT_IMR);
return 0;
}
static int rtw89_dbg_trigger_l0_error_by_halt_h2c(struct rtw89_dev *rtwdev)
{
if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))
return -EBUSY;
return rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L0_RESET_FORCE);
}
static int rtw89_dbg_trigger_l0_error(struct rtw89_dev *rtwdev)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
int (*sim_l0_by_halt_h2c)(struct rtw89_dev *rtwdev);
int (*sim_l0)(struct rtw89_dev *rtwdev);
switch (chip->chip_gen) {
case RTW89_CHIP_AX:
sim_l0_by_halt_h2c = rtw89_dbg_trigger_l0_error_by_halt_h2c_ax;
sim_l0 = rtw89_dbg_trigger_l0_error_ax;
break;
case RTW89_CHIP_BE:
sim_l0_by_halt_h2c = rtw89_dbg_trigger_l0_error_by_halt_h2c_be;
sim_l0 = rtw89_dbg_trigger_l0_error_be;
break;
default:
@ -3688,7 +3675,7 @@ static int rtw89_dbg_trigger_l0_error(struct rtw89_dev *rtwdev)
}
if (RTW89_CHK_FW_FEATURE(SIM_SER_L0L1_BY_HALT_H2C, &rtwdev->fw))
return sim_l0_by_halt_h2c(rtwdev);
return rtw89_dbg_trigger_l0_error_by_halt_h2c(rtwdev);
rtw89_leave_ps_mode(rtwdev);

2
drivers/net/wireless/realtek/rtw89/fw.c
View File

@ -931,8 +931,8 @@ static const struct __fw_feat_cfg fw_feat_tbl[] = {
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 84, 0, RFK_PRE_NOTIFY_MCC_V1),
__CFG_FW_FEAT(RTL8922A, lt, 0, 35, 84, 0, ADDR_CAM_V0),
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 92, 0, TX_HISTORY_V1),
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 97, 0, SIM_SER_L0L1_BY_HALT_H2C),
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 100, 0, SER_POST_RECOVER_DMAC),
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 108, 0, SIM_SER_L0L1_BY_HALT_H2C),
};
static void rtw89_fw_iterate_feature_cfg(struct rtw89_fw_info *fw,