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x86/cpu/transmeta: Rescan CPUID(0x1) after modifying capabilities

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Transmeta CPUs allow masking CPUID(0x1).EDX feature flags via MSR writes.  If
a bit is cleared in the 0x80860004 MSR, its corresponding feature flag is not
reported by CPUID.

Refresh the CPUID parser's CPUID(0x1) cache after all MSR bits are unmasked.

Note, the MSR 0x80860004 semantics are documented in the "BIOS Programmer's
Guide: Transmeta Crusoe Processor" document, dated June 14, 2002.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://patch.msgid.link/20260528153923.403473-9-darwi@linutronix.de
This commit is contained in:
Ahmed S. Darwish 2026-05-28 17:37:30 +02:00 committed by Borislav Petkov (AMD)
parent 924be9d673
commit bec89bf9ea
1 changed files with 1 additions and 0 deletions
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arch/x86/kernel/cpu/transmeta.c
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@ -88,6 +88,7 @@ static void init_transmeta(struct cpuinfo_x86 *c)
/* Unhide possibly hidden capability flags */
rdmsr(0x80860004, cap_mask, uk);
wrmsr(0x80860004, ~0, uk);
cpuid_refresh_leaf(c, 0x1);
c->x86_capability[CPUID_1_EDX] = cpuid_edx(0x00000001);
wrmsr(0x80860004, cap_mask, uk);