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drm/i915/vrr: Add DC Balance params to crtc_state

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Add DC Balance params to crtc_state, also add state checker
params for related properties.

--v3:
- Seggregate crtc_state params with this patch. (Ankit)

--v4:
- Update commit message and header. (Ankit)
- Add +1 to VMIN and VMAX only when it is non-zero. (Ankit)

--v5:
- Add headers in sorted order. (Jani Nikula)

--v6:
- Add a separate function to get and check dc_balance params.
- Avoid repeatative use of MMIO read. (Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20251223104542.2688548-6-mitulkumar.ajitkumar.golani@intel.com
This commit is contained in:
Mitul Golani 2025-12-23 16:15:27 +05:30 committed by Ankit Nautiyal
parent 19467b46c2
commit be843f3480
3 changed files with 46 additions and 0 deletions
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7
drivers/gpu/drm/i915/display/intel_display.c
View File

@ -5476,6 +5476,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
PIPE_CONF_CHECK_BOOL(cmrr.enable);
PIPE_CONF_CHECK_I(vrr.dc_balance.vmin);
PIPE_CONF_CHECK_I(vrr.dc_balance.vmax);
PIPE_CONF_CHECK_I(vrr.dc_balance.guardband);
PIPE_CONF_CHECK_I(vrr.dc_balance.slope);
PIPE_CONF_CHECK_I(vrr.dc_balance.max_increase);
PIPE_CONF_CHECK_I(vrr.dc_balance.max_decrease);
PIPE_CONF_CHECK_I(vrr.dc_balance.vblank_target);
}
if (!fastset || intel_vrr_always_use_vrr_tg(display)) {

7
drivers/gpu/drm/i915/display/intel_display_types.h
View File

@ -1384,6 +1384,13 @@ struct intel_crtc_state {
u8 pipeline_full;
u16 flipline, vmin, vmax, guardband;
u32 vsync_end, vsync_start;
struct {
bool enable;
u16 vmin, vmax;
u16 guardband, slope;
u16 max_increase, max_decrease;
u16 vblank_target;
} dc_balance;
} vrr;
/* Content Match Refresh Rate state */

32
drivers/gpu/drm/i915/display/intel_vrr.c
View File

@ -9,6 +9,7 @@
#include "intel_de.h"
#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_dmc_regs.h"
#include "intel_dp.h"
#include "intel_psr.h"
#include "intel_vrr.h"
@ -785,6 +786,35 @@ bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state)
crtc_state->vrr.flipline == crtc_state->vrr.vmin;
}
static
void intel_vrr_get_dc_balance_config(struct intel_crtc_state *crtc_state)
{
u32 reg_val;
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum pipe pipe = crtc->pipe;
if (!HAS_VRR_DC_BALANCE(display))
return;
reg_val = intel_de_read(display, PIPEDMC_DCB_VMIN(pipe));
crtc_state->vrr.dc_balance.vmin = reg_val ? reg_val + 1 : 0;
reg_val = intel_de_read(display, PIPEDMC_DCB_VMAX(pipe));
crtc_state->vrr.dc_balance.vmax = reg_val ? reg_val + 1 : 0;
crtc_state->vrr.dc_balance.guardband =
intel_de_read(display, PIPEDMC_DCB_GUARDBAND(pipe));
crtc_state->vrr.dc_balance.max_increase =
intel_de_read(display, PIPEDMC_DCB_MAX_INCREASE(pipe));
crtc_state->vrr.dc_balance.max_decrease =
intel_de_read(display, PIPEDMC_DCB_MAX_DECREASE(pipe));
crtc_state->vrr.dc_balance.slope =
intel_de_read(display, PIPEDMC_DCB_SLOPE(pipe));
crtc_state->vrr.dc_balance.vblank_target =
intel_de_read(display, PIPEDMC_DCB_VBLANK(pipe));
}
void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
@ -866,6 +896,8 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
else
crtc_state->vrr.enable = vrr_enable;
intel_vrr_get_dc_balance_config(crtc_state);
/*
* #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is set for mode_flags.
* Since CMRR is currently disabled, set this flag for VRR for now.