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clk: renesas: Updates for v6.8

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- Add EtherNet TSN and PCIe clocks on the R-Car V4H SoC,
   - Reuse reset functionality in the RZ/G2L clock driver.
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Merge tag 'renesas-clk-for-v6.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add EtherNet TSN and PCIe clocks on the Renesas R-Car V4H SoC
 - Reuse reset functionality in the Renesas RZ/G2L clock driver

* tag 'renesas-clk-for-v6.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: rzg2l-cpg: Reuse code in rzg2l_cpg_reset()
  clk: renesas: r8a779g0: Add PCIe clocks
  clk: renesas: r8a779g0: Add EtherTSN clock
This commit is contained in:
Stephen Boyd 2023-12-04 15:59:50 -08:00
commit be587cb529
2 changed files with 18 additions and 23 deletions
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3
drivers/clk/renesas/r8a779g0-cpg-mssr.c
View File

@ -192,6 +192,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
DEF_MOD("msi3", 621, R8A779G0_CLK_MSO),
DEF_MOD("msi4", 622, R8A779G0_CLK_MSO),
DEF_MOD("msi5", 623, R8A779G0_CLK_MSO),
DEF_MOD("pciec0", 624, R8A779G0_CLK_S0D2_HSC),
DEF_MOD("pscie1", 625, R8A779G0_CLK_S0D2_HSC),
DEF_MOD("pwm", 628, R8A779G0_CLK_SASYNCPERD4),
DEF_MOD("rpc-if", 629, R8A779G0_CLK_RPCD2),
DEF_MOD("scif0", 702, R8A779G0_CLK_SASYNCPERD4),
@ -235,6 +237,7 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
DEF_MOD("pfc2", 917, R8A779G0_CLK_CL16M),
DEF_MOD("pfc3", 918, R8A779G0_CLK_CL16M),
DEF_MOD("tsc", 919, R8A779G0_CLK_CL16M),
DEF_MOD("tsn", 2723, R8A779G0_CLK_S0D4_HSC),
DEF_MOD("ssiu", 2926, R8A779G0_CLK_S0D6_PER),
DEF_MOD("ssi", 2927, R8A779G0_CLK_S0D6_PER),
};

38
drivers/clk/renesas/rzg2l-cpg.c
View File

@ -1410,29 +1410,6 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
#define rcdev_to_priv(x) container_of(x, struct rzg2l_cpg_priv, rcdev)
static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
const struct rzg2l_cpg_info *info = priv->info;
unsigned int reg = info->resets[id].off;
u32 dis = BIT(info->resets[id].bit);
u32 we = dis << 16;
dev_dbg(rcdev->dev, "reset id:%ld offset:0x%x\n", id, CLK_RST_R(reg));
/* Reset module */
writel(we, priv->base + CLK_RST_R(reg));
/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
udelay(35);
/* Release module from reset state */
writel(we | dis, priv->base + CLK_RST_R(reg));
return 0;
}
static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
unsigned long id)
{
@ -1463,6 +1440,21 @@ static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev,
return 0;
}
static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev,
unsigned long id)
{
int ret;
ret = rzg2l_cpg_assert(rcdev, id);
if (ret)
return ret;
/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
udelay(35);
return rzg2l_cpg_deassert(rcdev, id);
}
static int rzg2l_cpg_status(struct reset_controller_dev *rcdev,
unsigned long id)
{