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sched/mmcid: Cacheline align MM CID storage

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Both the per CPU storage and the data in mm_struct are heavily used in
context switch. As they can end up next to other frequently modified data,
they are subject to false sharing.

Make them cache line aligned.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Link: https://patch.msgid.link/20251119172549.194111661@linutronix.de
This commit is contained in:
Thomas Gleixner 2025-11-19 18:26:49 +01:00 committed by Peter Zijlstra
parent 8cea569ca7
commit be4463fa2c
1 changed files with 2 additions and 2 deletions
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4
include/linux/rseq_types.h
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@ -112,7 +112,7 @@ struct sched_mm_cid {
*/
struct mm_cid_pcpu {
unsigned int cid;
};
}____cacheline_aligned_in_smp;
/**
* struct mm_mm_cid - Storage for per MM CID data
@ -126,7 +126,7 @@ struct mm_mm_cid {
struct mm_cid_pcpu __percpu *pcpu;
unsigned int nr_cpus_allowed;
raw_spinlock_t lock;
};
}____cacheline_aligned_in_smp;
#else /* CONFIG_SCHED_MM_CID */
struct mm_mm_cid { };
struct sched_mm_cid { };