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perf vendor events intel: Update arrowlake events from 1.17 to 1.19

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The updated events were published in:
b84e75626a

Signed-off-by: Chun-Tse Shao <ctshao@google.com>
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Reviewed-by: Ian Rogers <irogers@google.com>
Link: b84e75626a
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
This commit is contained in:
Chun-Tse Shao 2026-06-09 14:50:40 -07:00 committed by Namhyung Kim
parent 2b123a1a09
commit be4147c51a
5 changed files with 217 additions and 7 deletions
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30
tools/perf/pmu-events/arch/x86/arrowlake/cache.json
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@ -1,6 +1,6 @@
[
{
"BriefDescription": "Counts the number of request that were not accepted into the L2Q because the L2Q is FULL.",
"BriefDescription": "Counts the number of requests that were not accepted into the L2Q because the L2Q is FULL.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x31",
"EventName": "CORE_REJECT_L2Q.ANY",
@ -8,6 +8,15 @@
"SampleAfterValue": "1000003",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of requests that were not accepted into the L2Q because the L2Q is FULL.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x31",
"EventName": "CORE_REJECT_L2Q.ANY",
"PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a cores dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event.) Counts on a per core basis.",
"SampleAfterValue": "200003",
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches.",
"Counter": "0,1,2,3,4,5,6,7",
@ -310,6 +319,15 @@
"SampleAfterValue": "1000003",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x30",
"EventName": "L2_REJECT_XQ.ANY",
"PublicDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 write-back victims).",
"SampleAfterValue": "200003",
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Counts the number of L2 Cache Accesses Counts the total number of L2 Cache Accesses - sum of hits, misses, rejects front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only, per core event",
"Counter": "0,1,2,3,4,5,6,7",
@ -1382,6 +1400,16 @@
"UMask": "0x83",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of memory uops retired. A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST)",
"Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.ALL",
"SampleAfterValue": "200003",
"UMask": "0x83",
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Counts the number of load uops retired.",
"Counter": "0,1,2,3,4,5,6,7",

45
tools/perf/pmu-events/arch/x86/arrowlake/floating-point.json
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@ -510,6 +510,15 @@
"UMask": "0x1f",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of uops executed on all floating point ports.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb2",
"EventName": "FP_VINT_UOPS_EXECUTED.ALL",
"SampleAfterValue": "1000003",
"UMask": "0xf",
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Counts the number of uops executed on floating point and vector integer port 0.",
"Counter": "0,1,2,3,4,5,6,7",
@ -519,6 +528,15 @@
"UMask": "0x2",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of uops executed on floating point and vector integer port 0.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb2",
"EventName": "FP_VINT_UOPS_EXECUTED.P0",
"SampleAfterValue": "1000003",
"UMask": "0x2",
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Counts the number of uops executed on floating point and vector integer port 1.",
"Counter": "0,1,2,3,4,5,6,7",
@ -528,6 +546,15 @@
"UMask": "0x4",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of uops executed on floating point and vector integer port 1.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb2",
"EventName": "FP_VINT_UOPS_EXECUTED.P1",
"SampleAfterValue": "1000003",
"UMask": "0x4",
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Counts the number of uops executed on floating point and vector integer port 2.",
"Counter": "0,1,2,3,4,5,6,7",
@ -537,6 +564,15 @@
"UMask": "0x8",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of uops executed on floating point and vector integer port 2.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb2",
"EventName": "FP_VINT_UOPS_EXECUTED.P2",
"SampleAfterValue": "1000003",
"UMask": "0x8",
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Counts the number of uops executed on floating point and vector integer port 3.",
"Counter": "0,1,2,3,4,5,6,7",
@ -555,6 +591,15 @@
"UMask": "0x1e",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of uops executed on floating point and vector integer port 0, 1, 2.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb2",
"EventName": "FP_VINT_UOPS_EXECUTED.PRIMARY",
"SampleAfterValue": "1000003",
"UMask": "0xe",
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Counts the number of uops executed on floating point and vector integer store data port.",
"Counter": "0,1,2,3,4,5,6,7",

18
tools/perf/pmu-events/arch/x86/arrowlake/memory.json
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@ -173,6 +173,15 @@
"UMask": "0x2",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to request buffers full or lock in progress.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "LD_HEAD.WCB_FULL",
"SampleAfterValue": "1000003",
"UMask": "0x2",
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to request buffers full or lock in progress.",
"Counter": "0,1,2,3,4,5,6,7",
@ -182,6 +191,15 @@
"UMask": "0x82",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to request buffers full or lock in progress.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "LD_HEAD.WCB_FULL_AT_RET",
"SampleAfterValue": "1000003",
"UMask": "0x82",
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Counts the number of memory ordering machine clears triggered due to a snoop from an external agent. Does not count internally generated machine clears such as those due to disambiguations.",
"Counter": "0,1,2,3,4,5,6,7",

129
tools/perf/pmu-events/arch/x86/arrowlake/pipeline.json
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@ -209,7 +209,6 @@
"EventName": "BR_INST_RETIRED.COND_TAKEN_FWD",
"PublicDescription": "Counts taken forward conditional branch instructions retired. Available PDIST counters: 0,1",
"SampleAfterValue": "400009",
"UMask": "0x102",
"Unit": "cpu_core"
},
{
@ -608,7 +607,7 @@
"EventName": "BR_MISP_RETIRED.COND_TAKEN_BWD_COST",
"PublicDescription": "number of branch instructions retired that were mispredicted and taken backward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0,1",
"SampleAfterValue": "400009",
"UMask": "0x8001",
"UMask": "0x41",
"Unit": "cpu_core"
},
{
@ -637,7 +636,7 @@
"EventName": "BR_MISP_RETIRED.COND_TAKEN_FWD_COST",
"PublicDescription": "number of branch instructions retired that were mispredicted and taken forward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0,1",
"SampleAfterValue": "400009",
"UMask": "0x8002",
"UMask": "0x140",
"Unit": "cpu_core"
},
{
@ -773,11 +772,11 @@
"Unit": "cpu_core"
},
{
"BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS",
"BriefDescription": "This event counts the number of mispredicted ret instructions retired.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.RET",
"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired. Available PDIST counters: 0,1",
"PublicDescription": "This event counts the number of mispredicted ret instructions retired. Available PDIST counters: 0,1",
"SampleAfterValue": "100007",
"UMask": "0x8",
"Unit": "cpu_core"
@ -1326,6 +1325,15 @@
"UMask": "0xff",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of uops executed on all Integer ports.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "INT_UOPS_EXECUTED.ALL",
"SampleAfterValue": "1000003",
"UMask": "0xff",
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Counts the number of uops executed on a load port.",
"Counter": "0,1,2,3,4,5,6,7",
@ -1336,6 +1344,16 @@
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of uops executed on a load port.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "INT_UOPS_EXECUTED.LD",
"PublicDescription": "Counts the number of uops executed on a load port. This event counts for integer uops even if the destination is FP/vector",
"SampleAfterValue": "1000003",
"UMask": "0x1",
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Counts the number of uops executed on integer port 0.",
"Counter": "0,1,2,3,4,5,6,7",
@ -1345,6 +1363,15 @@
"UMask": "0x8",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of uops executed on integer port 0.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "INT_UOPS_EXECUTED.P0",
"SampleAfterValue": "1000003",
"UMask": "0x8",
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Counts the number of uops executed on integer port 1.",
"Counter": "0,1,2,3,4,5,6,7",
@ -1354,6 +1381,15 @@
"UMask": "0x10",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of uops executed on integer port 1.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "INT_UOPS_EXECUTED.P1",
"SampleAfterValue": "1000003",
"UMask": "0x10",
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Counts the number of uops executed on integer port 2.",
"Counter": "0,1,2,3,4,5,6,7",
@ -1363,6 +1399,15 @@
"UMask": "0x20",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of uops executed on integer port 2.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "INT_UOPS_EXECUTED.P2",
"SampleAfterValue": "1000003",
"UMask": "0x20",
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Counts the number of uops executed on integer port 3.",
"Counter": "0,1,2,3,4,5,6,7",
@ -1372,6 +1417,15 @@
"UMask": "0x40",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of uops executed on integer port 3.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "INT_UOPS_EXECUTED.P3",
"SampleAfterValue": "1000003",
"UMask": "0x40",
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Counts the number of uops executed on integer port 0,1, 2, 3.",
"Counter": "0,1,2,3,4,5,6,7",
@ -1381,6 +1435,15 @@
"UMask": "0x78",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of uops executed on integer port 0,1, 2, 3.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "INT_UOPS_EXECUTED.PRIMARY",
"SampleAfterValue": "1000003",
"UMask": "0x78",
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Counts the number of uops executed on a Store address port.",
"Counter": "0,1,2,3,4,5,6,7",
@ -1391,6 +1454,16 @@
"UMask": "0x2",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of uops executed on a Store address port.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "INT_UOPS_EXECUTED.STA",
"PublicDescription": "Counts the number of uops executed on a Store address port. This event counts integer uops even if the data source is FP/vector",
"SampleAfterValue": "1000003",
"UMask": "0x2",
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Counts the number of uops executed on an integer store data and jump port.",
"Counter": "0,1,2,3,4,5,6,7",
@ -1400,6 +1473,15 @@
"UMask": "0x4",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of uops executed on an integer store data and jump port.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "INT_UOPS_EXECUTED.STD_JMP",
"SampleAfterValue": "1000003",
"UMask": "0x4",
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Number of vector integer instructions retired of 128-bit vector-width.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
@ -1691,6 +1773,15 @@
"UMask": "0x88",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of machine clears that flush the pipeline and restart the machine without the use of microcode.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.FAST",
"SampleAfterValue": "20003",
"UMask": "0x10",
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Counts number of virtual trap actually taken (e.g. highest priority event during retirement). It can count virtual trap from FPC port 0 or port 1 (x87/SSE) equally in a single counter.",
"Counter": "0,1,2,3,4,5,6,7",
@ -1700,6 +1791,15 @@
"UMask": "0x40",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of virtual traps taken.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.FPC_VIRTUAL_TRAP",
"SampleAfterValue": "20003",
"UMask": "0x40",
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Counts the number of nukes due to memory renaming",
"Counter": "0,1,2,3,4,5,6,7",
@ -2015,6 +2115,15 @@
"UMask": "0x8",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of issue slots not consumed due to a color request for an FCW or MXCSR control register when all 4 colors (copies) are already in use.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x75",
"EventName": "SERIALIZATION.COLOR_STALLS",
"SampleAfterValue": "200003",
"UMask": "0x8",
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Counts the number of issue slots where no uop could issue due to an IQ scoreboard that stalls allocation until a specified older uop retires or (in the case of jump scoreboard) executes. Commonly executed instructions with IQ scoreboards include LFENCE and MFENCE.",
"Counter": "0,1,2,3,4,5,6,7",
@ -2034,6 +2143,16 @@
"UMask": "0x2",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x75",
"EventName": "SERIALIZATION.NON_C01_MS_SCB",
"PublicDescription": "Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires. The most commonly executed instruction with an MS scoreboard is PAUSE.",
"SampleAfterValue": "200003",
"UMask": "0x2",
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions.",
"Counter": "0,1,2,3,4,5,6,7,8,9",

2
tools/perf/pmu-events/arch/x86/mapfile.csv
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@ -1,7 +1,7 @@
Family-model,Version,Filename,EventType
GenuineIntel-6-(97|9A|B7|BA|BF),v1.39,alderlake,core
GenuineIntel-6-BE,v1.39,alderlaken,core
GenuineIntel-6-C[56],v1.17,arrowlake,core
GenuineIntel-6-C[56],v1.19,arrowlake,core
GenuineIntel-6-(1C|26|27|35|36),v5,bonnell,core
GenuineIntel-6-(3D|47),v30,broadwell,core
GenuineIntel-6-56,v12,broadwellde,core

1 Family-model Version Filename EventType
2 GenuineIntel-6-(97|9A|B7|BA|BF) v1.39 alderlake core
3 GenuineIntel-6-BE v1.39 alderlaken core
4 GenuineIntel-6-C[56] v1.17 v1.19 arrowlake core
5 GenuineIntel-6-(1C|26|27|35|36) v5 bonnell core
6 GenuineIntel-6-(3D|47) v30 broadwell core
7 GenuineIntel-6-56 v12 broadwellde core