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phy: rockchip: naneng-combphy: Always configure SSC spread direction

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Commit 0b31f29755 ("phy: rockchip: naneng-combphy: Consolidate SSC
configuration") moved the SSC spread spectrum direction setup into the
new rk_combphy_common_cfg_ssc() helper. That helper returns early when
the 'rockchip,enable-ssc' property is absent, whereas the equivalent
RK3568_PHYREG32 direction writes previously ran unconditionally in the
per-type switch statements, independent of whether SSC modulation was
actually enabled.

As no in-tree board sets 'rockchip,enable-ssc', this changed the behavior
at least for USB3 on RK3576, which now fails to bring up the link.
USB 2.0 still enumerates, but USB 3.0 does not, and the SuperSpeed root
port floods the log every second with:

  usb usb2-port1: Cannot enable. Maybe the USB cable is bad?

This was observed on two different RK3576 devices with a CoreChips SL6341
USB 2.0/3.0 hub connected to the USB DRD controller running in host mode.

Perform the SSC direction writes for PCIe/USB3 (and SATA) before the
enable_ssc check so that they always run, as they did before the
consolidation.

Cc: stable@vger.kernel.org
Closes: https://lore.kernel.org/all/CAKTNdwH_ZMQa-97h+tqdsWqXKtorkFF9wHAMn60-8ZGKuze_Mg@mail.gmail.com/
Fixes: 0b31f29755 ("phy: rockchip: naneng-combphy: Consolidate SSC configuration")
Signed-off-by: Alexey Charkov <alchark@flipper.net>
Tested-by: Liu Changjie <liucj1228@outlook.com>
Link: https://patch.msgid.link/20260714-naneng-ssc-fix-v1-1-1c40a58061ae@flipper.net
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Alexey Charkov 2026-07-14 19:41:20 +04:00 committed by Vinod Koul
parent 361f533a2d
commit be2b5b17b7
1 changed files with 3 additions and 3 deletions
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6
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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@ -452,9 +452,6 @@ static void rk_combphy_common_cfg_ssc(struct rockchip_combphy_priv *priv, unsign
struct device_node *np = priv->dev->of_node;
u32 val;
if (!priv->enable_ssc)
return;
/* Set SSC downward spread spectrum for PCIe and USB3 */
if (priv->type == PHY_TYPE_PCIE || priv->type == PHY_TYPE_USB3) {
val = FIELD_PREP(RK3568_PHYREG32_SSC_MASK, RK3568_PHYREG32_SSC_DOWNWARD);
@ -471,6 +468,9 @@ static void rk_combphy_common_cfg_ssc(struct rockchip_combphy_priv *priv, unsign
RK3568_PHYREG32);
}
if (!priv->enable_ssc)
return;
/* Enable SSC */
val = readl(priv->mmio + RK3568_PHYREG8);
val |= RK3568_PHYREG8_SSC_EN;