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MIPS: OCTEON: program L2C_CTL, not L2C_CFG, on OCTEON II
cvmx_helper_initialize_packet_io_global() sets the L2 arbitration modes by rewriting L2C_CFG. That register (0x1180080000000) does not exist on OCTEON II; there the L2 controller is configured through L2C_CTL (0x1180080800000), whose corresponding fields are rsp_arb_mode and xmc_arb_mode. On a CN6335 the stray write hung the board hard when this function ran - no exception, no watchdog, just a dead console. Keep the L2C_CFG write for CN3XXX/CN5XXX and program L2C_CTL on CN6XXX with the values the vendor SDK uses there (rsp_arb_mode 1, xmc_arb_mode 0), which is the same trade the existing code makes for the older parts: keep IO blocks from being starved under high L2 load. Assisted-by: Claude:claude-opus-5 Signed-off-by: Orgad Shaneh <orgads@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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@ -1014,7 +1014,6 @@ int cvmx_helper_initialize_packet_io_global(void)
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{
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int result = 0;
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int interface;
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union cvmx_l2c_cfg l2c_cfg;
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const int num_interfaces = cvmx_helper_get_number_of_interfaces();
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/*
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@ -1029,10 +1028,21 @@ int cvmx_helper_initialize_packet_io_global(void)
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* to the cores. This avoids conditions where IO blocks might
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* be starved under very high L2 loads.
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*/
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l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
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l2c_cfg.s.lrf_arb_mode = 0;
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l2c_cfg.s.rfb_arb_mode = 0;
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cvmx_write_csr(CVMX_L2C_CFG, l2c_cfg.u64);
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if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
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union cvmx_l2c_ctl l2c_ctl;
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l2c_ctl.u64 = cvmx_read_csr(CVMX_L2C_CTL);
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l2c_ctl.s.rsp_arb_mode = 1;
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l2c_ctl.s.xmc_arb_mode = 0;
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cvmx_write_csr(CVMX_L2C_CTL, l2c_ctl.u64);
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} else {
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union cvmx_l2c_cfg l2c_cfg;
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l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
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l2c_cfg.s.lrf_arb_mode = 0;
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l2c_cfg.s.rfb_arb_mode = 0;
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cvmx_write_csr(CVMX_L2C_CFG, l2c_cfg.u64);
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}
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cvmx_pko_initialize_global();
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for (interface = 0; interface < num_interfaces; interface++) {
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