MIPS: OCTEON: program L2C_CTL, not L2C_CFG, on OCTEON II

cvmx_helper_initialize_packet_io_global() sets the L2 arbitration modes
by rewriting L2C_CFG. That register (0x1180080000000) does not exist on
OCTEON II; there the L2 controller is configured through L2C_CTL
(0x1180080800000), whose corresponding fields are rsp_arb_mode and
xmc_arb_mode.

On a CN6335 the stray write hung the board hard when this function ran -
no exception, no watchdog, just a dead console.

Keep the L2C_CFG write for CN3XXX/CN5XXX and program L2C_CTL on CN6XXX
with the values the vendor SDK uses there (rsp_arb_mode 1,
xmc_arb_mode 0), which is the same trade the existing code makes for
the older parts: keep IO blocks from being starved under high L2 load.

Assisted-by: Claude:claude-opus-5
Signed-off-by: Orgad Shaneh <orgads@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Orgad Shaneh 2026-09-15 07:12:47 +00:00 committed by Thomas Bogendoerfer
parent 7d22c1e6d1
commit bd97813030

View File

@ -1014,7 +1014,6 @@ int cvmx_helper_initialize_packet_io_global(void)
{
int result = 0;
int interface;
union cvmx_l2c_cfg l2c_cfg;
const int num_interfaces = cvmx_helper_get_number_of_interfaces();
/*
@ -1029,10 +1028,21 @@ int cvmx_helper_initialize_packet_io_global(void)
* to the cores. This avoids conditions where IO blocks might
* be starved under very high L2 loads.
*/
l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
l2c_cfg.s.lrf_arb_mode = 0;
l2c_cfg.s.rfb_arb_mode = 0;
cvmx_write_csr(CVMX_L2C_CFG, l2c_cfg.u64);
if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
union cvmx_l2c_ctl l2c_ctl;
l2c_ctl.u64 = cvmx_read_csr(CVMX_L2C_CTL);
l2c_ctl.s.rsp_arb_mode = 1;
l2c_ctl.s.xmc_arb_mode = 0;
cvmx_write_csr(CVMX_L2C_CTL, l2c_ctl.u64);
} else {
union cvmx_l2c_cfg l2c_cfg;
l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
l2c_cfg.s.lrf_arb_mode = 0;
l2c_cfg.s.rfb_arb_mode = 0;
cvmx_write_csr(CVMX_L2C_CFG, l2c_cfg.u64);
}
cvmx_pko_initialize_global();
for (interface = 0; interface < num_interfaces; interface++) {