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wifi: ath10k: Constify structures in hw.c
Structures defined in hw.c are not modified in this driver. Constifying these structures moves some data to a read-only section, so increase overall security. On a x86_64, with allmodconfig: Before: ====== text data bss dec hex filename 10357 951 0 11308 2c2c drivers/net/wireless/ath/ath10k/hw.o After: ===== text data bss dec hex filename 11125 203 0 11328 2c40 drivers/net/wireless/ath/ath10k/hw.o Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Baochen Qiang <quic_bqiang@quicinc.com> Link: https://patch.msgid.link/504b4d5276d13f5f9c3bffcfdaf244006312c22b.1745051315.git.christophe.jaillet@wanadoo.fr Signed-off-by: Jeff Johnson <jeff.johnson@oss.qualcomm.com>
This commit is contained in:
Christophe JAILLET
Jeff Johnson
parent
2ef2d31925
commit
bd8402eec9
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@ -80,7 +80,7 @@ static inline u32 shadow_sr_wr_ind_addr(struct ath10k *ar,
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static inline unsigned int
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ath10k_set_ring_byte(unsigned int offset,
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struct ath10k_hw_ce_regs_addr_map *addr_map)
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const struct ath10k_hw_ce_regs_addr_map *addr_map)
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{
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return ((offset << addr_map->lsb) & addr_map->mask);
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}
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@ -203,7 +203,7 @@ static inline void ath10k_ce_src_ring_dmax_set(struct ath10k *ar,
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u32 ce_ctrl_addr,
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unsigned int n)
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{
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struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs;
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const struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs;
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u32 ctrl1_addr = ath10k_ce_read32(ar, ce_ctrl_addr +
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ctrl_regs->addr);
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@ -217,7 +217,7 @@ static inline void ath10k_ce_src_ring_byte_swap_set(struct ath10k *ar,
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u32 ce_ctrl_addr,
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unsigned int n)
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{
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struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs;
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const struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs;
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u32 ctrl1_addr = ath10k_ce_read32(ar, ce_ctrl_addr +
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ctrl_regs->addr);
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@ -231,7 +231,7 @@ static inline void ath10k_ce_dest_ring_byte_swap_set(struct ath10k *ar,
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u32 ce_ctrl_addr,
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unsigned int n)
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{
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struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs;
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const struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs;
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u32 ctrl1_addr = ath10k_ce_read32(ar, ce_ctrl_addr +
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ctrl_regs->addr);
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@ -313,7 +313,7 @@ static inline void ath10k_ce_src_ring_highmark_set(struct ath10k *ar,
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u32 ce_ctrl_addr,
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unsigned int n)
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{
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struct ath10k_hw_ce_dst_src_wm_regs *srcr_wm = ar->hw_ce_regs->wm_srcr;
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const struct ath10k_hw_ce_dst_src_wm_regs *srcr_wm = ar->hw_ce_regs->wm_srcr;
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u32 addr = ath10k_ce_read32(ar, ce_ctrl_addr + srcr_wm->addr);
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ath10k_ce_write32(ar, ce_ctrl_addr + srcr_wm->addr,
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@ -325,7 +325,7 @@ static inline void ath10k_ce_src_ring_lowmark_set(struct ath10k *ar,
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u32 ce_ctrl_addr,
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unsigned int n)
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{
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struct ath10k_hw_ce_dst_src_wm_regs *srcr_wm = ar->hw_ce_regs->wm_srcr;
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const struct ath10k_hw_ce_dst_src_wm_regs *srcr_wm = ar->hw_ce_regs->wm_srcr;
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u32 addr = ath10k_ce_read32(ar, ce_ctrl_addr + srcr_wm->addr);
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ath10k_ce_write32(ar, ce_ctrl_addr + srcr_wm->addr,
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@ -337,7 +337,7 @@ static inline void ath10k_ce_dest_ring_highmark_set(struct ath10k *ar,
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u32 ce_ctrl_addr,
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unsigned int n)
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{
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struct ath10k_hw_ce_dst_src_wm_regs *dstr_wm = ar->hw_ce_regs->wm_dstr;
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const struct ath10k_hw_ce_dst_src_wm_regs *dstr_wm = ar->hw_ce_regs->wm_dstr;
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u32 addr = ath10k_ce_read32(ar, ce_ctrl_addr + dstr_wm->addr);
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ath10k_ce_write32(ar, ce_ctrl_addr + dstr_wm->addr,
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@ -349,7 +349,7 @@ static inline void ath10k_ce_dest_ring_lowmark_set(struct ath10k *ar,
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u32 ce_ctrl_addr,
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unsigned int n)
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{
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struct ath10k_hw_ce_dst_src_wm_regs *dstr_wm = ar->hw_ce_regs->wm_dstr;
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const struct ath10k_hw_ce_dst_src_wm_regs *dstr_wm = ar->hw_ce_regs->wm_dstr;
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u32 addr = ath10k_ce_read32(ar, ce_ctrl_addr + dstr_wm->addr);
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ath10k_ce_write32(ar, ce_ctrl_addr + dstr_wm->addr,
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@ -360,7 +360,7 @@ static inline void ath10k_ce_dest_ring_lowmark_set(struct ath10k *ar,
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static inline void ath10k_ce_copy_complete_inter_enable(struct ath10k *ar,
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u32 ce_ctrl_addr)
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{
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struct ath10k_hw_ce_host_ie *host_ie = ar->hw_ce_regs->host_ie;
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const struct ath10k_hw_ce_host_ie *host_ie = ar->hw_ce_regs->host_ie;
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u32 host_ie_addr = ath10k_ce_read32(ar, ce_ctrl_addr +
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ar->hw_ce_regs->host_ie_addr);
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@ -372,7 +372,7 @@ static inline void ath10k_ce_copy_complete_inter_enable(struct ath10k *ar,
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static inline void ath10k_ce_copy_complete_intr_disable(struct ath10k *ar,
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u32 ce_ctrl_addr)
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{
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struct ath10k_hw_ce_host_ie *host_ie = ar->hw_ce_regs->host_ie;
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const struct ath10k_hw_ce_host_ie *host_ie = ar->hw_ce_regs->host_ie;
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u32 host_ie_addr = ath10k_ce_read32(ar, ce_ctrl_addr +
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ar->hw_ce_regs->host_ie_addr);
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@ -384,7 +384,7 @@ static inline void ath10k_ce_copy_complete_intr_disable(struct ath10k *ar,
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static inline void ath10k_ce_watermark_intr_disable(struct ath10k *ar,
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u32 ce_ctrl_addr)
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{
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struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs;
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const struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs;
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u32 host_ie_addr = ath10k_ce_read32(ar, ce_ctrl_addr +
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ar->hw_ce_regs->host_ie_addr);
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@ -396,7 +396,7 @@ static inline void ath10k_ce_watermark_intr_disable(struct ath10k *ar,
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static inline void ath10k_ce_error_intr_disable(struct ath10k *ar,
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u32 ce_ctrl_addr)
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{
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struct ath10k_hw_ce_misc_regs *misc_regs = ar->hw_ce_regs->misc_regs;
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const struct ath10k_hw_ce_misc_regs *misc_regs = ar->hw_ce_regs->misc_regs;
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u32 misc_ie_addr = ath10k_ce_read32(ar,
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ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr);
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@ -410,7 +410,7 @@ static inline void ath10k_ce_engine_int_status_clear(struct ath10k *ar,
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u32 ce_ctrl_addr,
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unsigned int mask)
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{
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struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs;
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const struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs;
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ath10k_ce_write32(ar, ce_ctrl_addr + wm_regs->addr, mask);
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}
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@ -1230,7 +1230,7 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id)
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{
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struct ath10k_ce *ce = ath10k_ce_priv(ar);
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struct ath10k_ce_pipe *ce_state = &ce->ce_states[ce_id];
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struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs;
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const struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs;
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u32 ctrl_addr = ce_state->ctrl_addr;
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/*
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@ -212,40 +212,40 @@ const struct ath10k_hw_regs wcn3990_regs = {
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.pcie_intr_fw_mask = 0x00100000,
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};
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static struct ath10k_hw_ce_regs_addr_map wcn3990_src_ring = {
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static const struct ath10k_hw_ce_regs_addr_map wcn3990_src_ring = {
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.msb = 0x00000010,
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.lsb = 0x00000010,
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.mask = GENMASK(17, 17),
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};
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static struct ath10k_hw_ce_regs_addr_map wcn3990_dst_ring = {
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static const struct ath10k_hw_ce_regs_addr_map wcn3990_dst_ring = {
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.msb = 0x00000012,
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.lsb = 0x00000012,
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.mask = GENMASK(18, 18),
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};
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static struct ath10k_hw_ce_regs_addr_map wcn3990_dmax = {
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static const struct ath10k_hw_ce_regs_addr_map wcn3990_dmax = {
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.msb = 0x00000000,
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.lsb = 0x00000000,
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.mask = GENMASK(15, 0),
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};
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static struct ath10k_hw_ce_ctrl1 wcn3990_ctrl1 = {
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static const struct ath10k_hw_ce_ctrl1 wcn3990_ctrl1 = {
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.addr = 0x00000018,
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.src_ring = &wcn3990_src_ring,
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.dst_ring = &wcn3990_dst_ring,
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.dmax = &wcn3990_dmax,
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};
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static struct ath10k_hw_ce_regs_addr_map wcn3990_host_ie_cc = {
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static const struct ath10k_hw_ce_regs_addr_map wcn3990_host_ie_cc = {
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.mask = GENMASK(0, 0),
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};
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static struct ath10k_hw_ce_host_ie wcn3990_host_ie = {
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static const struct ath10k_hw_ce_host_ie wcn3990_host_ie = {
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.copy_complete = &wcn3990_host_ie_cc,
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};
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static struct ath10k_hw_ce_host_wm_regs wcn3990_wm_reg = {
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static const struct ath10k_hw_ce_host_wm_regs wcn3990_wm_reg = {
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.dstr_lmask = 0x00000010,
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.dstr_hmask = 0x00000008,
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.srcr_lmask = 0x00000004,
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@ -255,7 +255,7 @@ static struct ath10k_hw_ce_host_wm_regs wcn3990_wm_reg = {
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.addr = 0x00000030,
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};
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static struct ath10k_hw_ce_misc_regs wcn3990_misc_reg = {
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static const struct ath10k_hw_ce_misc_regs wcn3990_misc_reg = {
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.axi_err = 0x00000100,
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.dstr_add_err = 0x00000200,
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.srcr_len_err = 0x00000100,
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@ -266,19 +266,19 @@ static struct ath10k_hw_ce_misc_regs wcn3990_misc_reg = {
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.addr = 0x00000038,
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};
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static struct ath10k_hw_ce_regs_addr_map wcn3990_src_wm_low = {
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static const struct ath10k_hw_ce_regs_addr_map wcn3990_src_wm_low = {
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.msb = 0x00000000,
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.lsb = 0x00000010,
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.mask = GENMASK(31, 16),
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};
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static struct ath10k_hw_ce_regs_addr_map wcn3990_src_wm_high = {
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static const struct ath10k_hw_ce_regs_addr_map wcn3990_src_wm_high = {
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.msb = 0x0000000f,
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.lsb = 0x00000000,
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.mask = GENMASK(15, 0),
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};
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static struct ath10k_hw_ce_dst_src_wm_regs wcn3990_wm_src_ring = {
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static const struct ath10k_hw_ce_dst_src_wm_regs wcn3990_wm_src_ring = {
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.addr = 0x0000004c,
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.low_rst = 0x00000000,
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.high_rst = 0x00000000,
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@ -286,18 +286,18 @@ static struct ath10k_hw_ce_dst_src_wm_regs wcn3990_wm_src_ring = {
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.wm_high = &wcn3990_src_wm_high,
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};
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static struct ath10k_hw_ce_regs_addr_map wcn3990_dst_wm_low = {
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static const struct ath10k_hw_ce_regs_addr_map wcn3990_dst_wm_low = {
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.lsb = 0x00000010,
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.mask = GENMASK(31, 16),
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};
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static struct ath10k_hw_ce_regs_addr_map wcn3990_dst_wm_high = {
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static const struct ath10k_hw_ce_regs_addr_map wcn3990_dst_wm_high = {
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.msb = 0x0000000f,
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.lsb = 0x00000000,
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.mask = GENMASK(15, 0),
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};
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static struct ath10k_hw_ce_dst_src_wm_regs wcn3990_wm_dst_ring = {
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static const struct ath10k_hw_ce_dst_src_wm_regs wcn3990_wm_dst_ring = {
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.addr = 0x00000050,
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.low_rst = 0x00000000,
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.high_rst = 0x00000000,
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@ -305,7 +305,7 @@ static struct ath10k_hw_ce_dst_src_wm_regs wcn3990_wm_dst_ring = {
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.wm_high = &wcn3990_dst_wm_high,
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};
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static struct ath10k_hw_ce_ctrl1_upd wcn3990_ctrl1_upd = {
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static const struct ath10k_hw_ce_ctrl1_upd wcn3990_ctrl1_upd = {
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.shift = 19,
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.mask = 0x00080000,
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.enable = 0x00000000,
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@ -344,25 +344,25 @@ const struct ath10k_hw_values wcn3990_values = {
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.ce_desc_meta_data_lsb = 4,
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};
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static struct ath10k_hw_ce_regs_addr_map qcax_src_ring = {
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static const struct ath10k_hw_ce_regs_addr_map qcax_src_ring = {
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.msb = 0x00000010,
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.lsb = 0x00000010,
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.mask = GENMASK(16, 16),
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};
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static struct ath10k_hw_ce_regs_addr_map qcax_dst_ring = {
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static const struct ath10k_hw_ce_regs_addr_map qcax_dst_ring = {
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.msb = 0x00000011,
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.lsb = 0x00000011,
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.mask = GENMASK(17, 17),
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};
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static struct ath10k_hw_ce_regs_addr_map qcax_dmax = {
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static const struct ath10k_hw_ce_regs_addr_map qcax_dmax = {
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.msb = 0x0000000f,
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.lsb = 0x00000000,
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.mask = GENMASK(15, 0),
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};
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static struct ath10k_hw_ce_ctrl1 qcax_ctrl1 = {
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static const struct ath10k_hw_ce_ctrl1 qcax_ctrl1 = {
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.addr = 0x00000010,
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.hw_mask = 0x0007ffff,
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.sw_mask = 0x0007ffff,
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@ -375,31 +375,31 @@ static struct ath10k_hw_ce_ctrl1 qcax_ctrl1 = {
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.dmax = &qcax_dmax,
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};
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static struct ath10k_hw_ce_regs_addr_map qcax_cmd_halt_status = {
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static const struct ath10k_hw_ce_regs_addr_map qcax_cmd_halt_status = {
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.msb = 0x00000003,
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.lsb = 0x00000003,
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.mask = GENMASK(3, 3),
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};
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static struct ath10k_hw_ce_cmd_halt qcax_cmd_halt = {
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static const struct ath10k_hw_ce_cmd_halt qcax_cmd_halt = {
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.msb = 0x00000000,
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.mask = GENMASK(0, 0),
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.status_reset = 0x00000000,
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.status = &qcax_cmd_halt_status,
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};
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static struct ath10k_hw_ce_regs_addr_map qcax_host_ie_cc = {
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static const struct ath10k_hw_ce_regs_addr_map qcax_host_ie_cc = {
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.msb = 0x00000000,
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.lsb = 0x00000000,
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.mask = GENMASK(0, 0),
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};
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static struct ath10k_hw_ce_host_ie qcax_host_ie = {
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static const struct ath10k_hw_ce_host_ie qcax_host_ie = {
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.copy_complete_reset = 0x00000000,
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.copy_complete = &qcax_host_ie_cc,
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};
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static struct ath10k_hw_ce_host_wm_regs qcax_wm_reg = {
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static const struct ath10k_hw_ce_host_wm_regs qcax_wm_reg = {
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.dstr_lmask = 0x00000010,
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.dstr_hmask = 0x00000008,
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.srcr_lmask = 0x00000004,
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@ -409,7 +409,7 @@ static struct ath10k_hw_ce_host_wm_regs qcax_wm_reg = {
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.addr = 0x00000030,
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};
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static struct ath10k_hw_ce_misc_regs qcax_misc_reg = {
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static const struct ath10k_hw_ce_misc_regs qcax_misc_reg = {
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.axi_err = 0x00000400,
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.dstr_add_err = 0x00000200,
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.srcr_len_err = 0x00000100,
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@ -420,19 +420,19 @@ static struct ath10k_hw_ce_misc_regs qcax_misc_reg = {
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.addr = 0x00000038,
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};
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static struct ath10k_hw_ce_regs_addr_map qcax_src_wm_low = {
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static const struct ath10k_hw_ce_regs_addr_map qcax_src_wm_low = {
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.msb = 0x0000001f,
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.lsb = 0x00000010,
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.mask = GENMASK(31, 16),
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};
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static struct ath10k_hw_ce_regs_addr_map qcax_src_wm_high = {
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static const struct ath10k_hw_ce_regs_addr_map qcax_src_wm_high = {
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.msb = 0x0000000f,
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.lsb = 0x00000000,
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.mask = GENMASK(15, 0),
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};
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static struct ath10k_hw_ce_dst_src_wm_regs qcax_wm_src_ring = {
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static const struct ath10k_hw_ce_dst_src_wm_regs qcax_wm_src_ring = {
|
||||
.addr = 0x0000004c,
|
||||
.low_rst = 0x00000000,
|
||||
.high_rst = 0x00000000,
|
||||
|
|
@ -440,18 +440,18 @@ static struct ath10k_hw_ce_dst_src_wm_regs qcax_wm_src_ring = {
|
|||
.wm_high = &qcax_src_wm_high,
|
||||
};
|
||||
|
||||
static struct ath10k_hw_ce_regs_addr_map qcax_dst_wm_low = {
|
||||
static const struct ath10k_hw_ce_regs_addr_map qcax_dst_wm_low = {
|
||||
.lsb = 0x00000010,
|
||||
.mask = GENMASK(31, 16),
|
||||
};
|
||||
|
||||
static struct ath10k_hw_ce_regs_addr_map qcax_dst_wm_high = {
|
||||
static const struct ath10k_hw_ce_regs_addr_map qcax_dst_wm_high = {
|
||||
.msb = 0x0000000f,
|
||||
.lsb = 0x00000000,
|
||||
.mask = GENMASK(15, 0),
|
||||
};
|
||||
|
||||
static struct ath10k_hw_ce_dst_src_wm_regs qcax_wm_dst_ring = {
|
||||
static const struct ath10k_hw_ce_dst_src_wm_regs qcax_wm_dst_ring = {
|
||||
.addr = 0x00000050,
|
||||
.low_rst = 0x00000000,
|
||||
.high_rst = 0x00000000,
|
||||
|
|
|
|||
|
|
@ -289,19 +289,22 @@ struct ath10k_hw_ce_ctrl1 {
|
|||
u32 sw_wr_mask;
|
||||
u32 reset_mask;
|
||||
u32 reset;
|
||||
struct ath10k_hw_ce_regs_addr_map *src_ring;
|
||||
struct ath10k_hw_ce_regs_addr_map *dst_ring;
|
||||
struct ath10k_hw_ce_regs_addr_map *dmax; };
|
||||
const struct ath10k_hw_ce_regs_addr_map *src_ring;
|
||||
const struct ath10k_hw_ce_regs_addr_map *dst_ring;
|
||||
const struct ath10k_hw_ce_regs_addr_map *dmax;
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_cmd_halt {
|
||||
u32 status_reset;
|
||||
u32 msb;
|
||||
u32 mask;
|
||||
struct ath10k_hw_ce_regs_addr_map *status; };
|
||||
const struct ath10k_hw_ce_regs_addr_map *status;
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_host_ie {
|
||||
u32 copy_complete_reset;
|
||||
struct ath10k_hw_ce_regs_addr_map *copy_complete; };
|
||||
const struct ath10k_hw_ce_regs_addr_map *copy_complete;
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_host_wm_regs {
|
||||
u32 dstr_lmask;
|
||||
|
|
@ -328,8 +331,9 @@ struct ath10k_hw_ce_dst_src_wm_regs {
|
|||
u32 addr;
|
||||
u32 low_rst;
|
||||
u32 high_rst;
|
||||
struct ath10k_hw_ce_regs_addr_map *wm_low;
|
||||
struct ath10k_hw_ce_regs_addr_map *wm_high; };
|
||||
const struct ath10k_hw_ce_regs_addr_map *wm_low;
|
||||
const struct ath10k_hw_ce_regs_addr_map *wm_high;
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_ctrl1_upd {
|
||||
u32 shift;
|
||||
|
|
@ -355,14 +359,14 @@ struct ath10k_hw_ce_regs {
|
|||
u32 ce_rri_low;
|
||||
u32 ce_rri_high;
|
||||
u32 host_ie_addr;
|
||||
struct ath10k_hw_ce_host_wm_regs *wm_regs;
|
||||
struct ath10k_hw_ce_misc_regs *misc_regs;
|
||||
struct ath10k_hw_ce_ctrl1 *ctrl1_regs;
|
||||
struct ath10k_hw_ce_cmd_halt *cmd_halt;
|
||||
struct ath10k_hw_ce_host_ie *host_ie;
|
||||
struct ath10k_hw_ce_dst_src_wm_regs *wm_srcr;
|
||||
struct ath10k_hw_ce_dst_src_wm_regs *wm_dstr;
|
||||
struct ath10k_hw_ce_ctrl1_upd *upd;
|
||||
const struct ath10k_hw_ce_host_wm_regs *wm_regs;
|
||||
const struct ath10k_hw_ce_misc_regs *misc_regs;
|
||||
const struct ath10k_hw_ce_ctrl1 *ctrl1_regs;
|
||||
const struct ath10k_hw_ce_cmd_halt *cmd_halt;
|
||||
const struct ath10k_hw_ce_host_ie *host_ie;
|
||||
const struct ath10k_hw_ce_dst_src_wm_regs *wm_srcr;
|
||||
const struct ath10k_hw_ce_dst_src_wm_regs *wm_dstr;
|
||||
const struct ath10k_hw_ce_ctrl1_upd *upd;
|
||||
};
|
||||
|
||||
struct ath10k_hw_values {
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user