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ARM: rockchip: correct L2 latency setting

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dkl 2014-02-07 20:19:16 +08:00
parent 026195c1e3
commit bd1ad1b0a6
1 changed files with 1 additions and 1 deletions
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2
arch/arm/boot/dts/rk3188.dtsi
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@ -69,7 +69,7 @@ L2: cache-controller@10138000 {
cache-unified;
cache-level = <2>;
arm,tag-latency = <1 1 1>;
arm,data-latency = <2 3 1>;
arm,data-latency = <3 1 2>;
rockchip,prefetch-ctrl = <0x70000003>;
/* L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN */
rockchip,power-ctrl = <0x3>;