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phy: rockchip: usbdp: Register DP aux bridge
Add support to use USB-C connectors with the DP altmode helper code on
devicetree based platforms. To get this working there must be a DRM
bridge chain from the DisplayPort controller to the USB-C connector.
E.g. on Rockchip RK3576:
root@rk3576 # cat /sys/kernel/debug/dri/0/encoder-0/bridges
bridge[0]: dw_dp_bridge_funcs
refcount: 7
type: [10] DP
OF: /soc/dp@27e40000:rockchip,rk3576-dp
ops: [0x47] detect edid hpd
bridge[1]: drm_aux_bridge_funcs
refcount: 4
type: [0] Unknown
OF: /soc/phy@2b010000:rockchip,rk3576-usbdp-phy
ops: [0x0]
bridge[2]: drm_aux_hpd_bridge_funcs
refcount: 5
type: [10] DP
OF: /soc/i2c@2ac50000/typec-portc@22/connector:usb-c-connector
ops: [0x4] hpd
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Igor Paunovic <royalnet026@gmail.com> # Orange Pi 5 Plus
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Link: https://patch.msgid.link/20260915-rockchip-usbdp-cleanup-v15-16-80e2c11d1ce8@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
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commit
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@ -136,8 +136,10 @@ config PHY_ROCKCHIP_USBDP
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tristate "Rockchip USBDP COMBO PHY Driver"
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depends on ARCH_ROCKCHIP && OF
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depends on TYPEC
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depends on DRM || DRM=n
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select GENERIC_PHY
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select USB_COMMON
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select DRM_AUX_BRIDGE if DRM_BRIDGE
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help
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Enable this to support the Rockchip USB3.0/DP combo PHY with
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Samsung IP block. This is required for USB3 support on RK3588.
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@ -6,6 +6,7 @@
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* Copyright (C) 2024 Collabora Ltd
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*/
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#include <drm/bridge/aux-bridge.h>
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#include <dt-bindings/phy/phy.h>
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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@ -1413,6 +1414,7 @@ static int rk_udphy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct phy_provider *phy_provider;
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struct fwnode_handle *dp_aux_ep;
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struct resource *res;
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struct rk_udphy *udphy;
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void __iomem *base;
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@ -1467,6 +1469,21 @@ static int rk_udphy_probe(struct platform_device *pdev)
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return ret;
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}
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/*
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* Only register the DRM bridge, if the DP aux channel is connected.
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* Some boards use the USBDP PHY only for its USB3 capabilities. The
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* aux bridge itself will be registered using port 0, endpoint 0, which
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* is fine as that is the actual superspeed data connection shared by
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* USB3 and DP based on the mux config.
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*/
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dp_aux_ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 3, 0, 0);
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if (dp_aux_ep) {
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ret = drm_aux_bridge_register(dev);
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fwnode_handle_put(dp_aux_ep);
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if (ret)
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return ret;
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}
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udphy->phy_u3 = devm_phy_create(dev, dev->of_node, &rk_udphy_usb3_phy_ops);
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if (IS_ERR(udphy->phy_u3)) {
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ret = PTR_ERR(udphy->phy_u3);
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