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drm/amd/display: Add FRL register for DCN302

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Add the required FRL registers for DCN302.

Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rodrigo Siqueira 2023-06-07 13:53:28 -06:00 committed by Alex Deucher
parent 8a03fad662
commit bcd7f8081d
2 changed files with 2019 additions and 0 deletions
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112
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h
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@ -14303,12 +14303,124 @@
#define mmDC_PERFMON25_PERFMON_HI_BASE_IDX 3
#define mmDC_PERFMON25_PERFMON_LOW 0x08cf
#define mmDC_PERFMON25_PERFMON_LOW_BASE_IDX 3
// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec
// base address: 0x2634c
#define mmHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3
#define mmHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3
#define mmHDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL 0x08d4
#define mmHDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL_BASE_IDX 3
#define mmHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5
#define mmHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3
#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6
#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3
#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7
#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3
#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8
#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3
// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec
// base address: 0x2637c
#define mmHDMI_TB_ENC_CONTROL 0x08df
#define mmHDMI_TB_ENC_CONTROL_BASE_IDX 3
#define mmHDMI_TB_ENC_PIXEL_FORMAT 0x08e0
#define mmHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3
#define mmHDMI_TB_ENC_PACKET_CONTROL 0x08e1
#define mmHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3
#define mmHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2
#define mmHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3
#define mmHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3
#define mmHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3
#define mmHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4
#define mmHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3
#define mmHDMI_TB_ENC_GC_CONTROL 0x08e5
#define mmHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3
#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6
#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3
#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7
#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3
#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8
#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3
#define mmHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9
#define mmHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3
#define mmHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea
#define mmHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3
#define mmHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb
#define mmHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3
#define mmHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec
#define mmHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3
#define mmHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed
#define mmHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3
#define mmHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee
#define mmHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3
#define mmHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef
#define mmHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3
#define mmHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0
#define mmHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3
#define mmHDMI_TB_ENC_DB_CONTROL 0x08f1
#define mmHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3
#define mmHDMI_TB_ENC_ACR_32_0 0x08f2
#define mmHDMI_TB_ENC_ACR_32_0_BASE_IDX 3
#define mmHDMI_TB_ENC_ACR_32_1 0x08f3
#define mmHDMI_TB_ENC_ACR_32_1_BASE_IDX 3
#define mmHDMI_TB_ENC_ACR_44_0 0x08f4
#define mmHDMI_TB_ENC_ACR_44_0_BASE_IDX 3
#define mmHDMI_TB_ENC_ACR_44_1 0x08f5
#define mmHDMI_TB_ENC_ACR_44_1_BASE_IDX 3
#define mmHDMI_TB_ENC_ACR_48_0 0x08f6
#define mmHDMI_TB_ENC_ACR_48_0_BASE_IDX 3
#define mmHDMI_TB_ENC_ACR_48_1 0x08f7
#define mmHDMI_TB_ENC_ACR_48_1_BASE_IDX 3
#define mmHDMI_TB_ENC_ACR_STATUS_0 0x08f8
#define mmHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3
#define mmHDMI_TB_ENC_ACR_STATUS_1 0x08f9
#define mmHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3
#define mmHDMI_TB_ENC_BUFFER_CONTROL 0x08fb
#define mmHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3
#define mmHDMI_TB_ENC_MEM_CTRL 0x08fe
#define mmHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3
#define mmHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff
#define mmHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3
#define mmHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900
#define mmHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3
#define mmHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901
#define mmHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3
#define mmHDMI_TB_ENC_CRC_CNTL 0x0903
#define mmHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3
#define mmHDMI_TB_ENC_CRC_RESULT_0 0x0904
#define mmHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3
#define mmHDMI_TB_ENC_MODE 0x0908
#define mmHDMI_TB_ENC_MODE_BASE_IDX 3
#define mmHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909
#define mmHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3
#define mmHDMI_TB_ENC_CRC_RESULT_1 0x090a
#define mmHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3
// base address: 0x264f0
#define mmDME5_DME_CONTROL 0x093c
#define mmDME5_DME_CONTROL_BASE_IDX 3
#define mmDME5_DME_MEMORY_CONTROL 0x093d
#define mmDME5_DME_MEMORY_CONTROL_BASE_IDX 3
// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec
// base address: 0x2656c
#define mmHDMI_LINK_ENC_CONTROL 0x095b
#define mmHDMI_LINK_ENC_CONTROL_BASE_IDX 3
#define mmHDMI_LINK_ENC_CLK_CTRL 0x095c
#define mmHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3
// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec
// base address: 0x26594
#define mmHDMI_FRL_ENC_CONFIG 0x0965
#define mmHDMI_FRL_ENC_CONFIG_BASE_IDX 3
#define mmHDMI_FRL_ENC_CONFIG2 0x0966
#define mmHDMI_FRL_ENC_CONFIG2_BASE_IDX 3
#define mmHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967
#define mmHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3
#define mmHDMI_FRL_ENC_MEM_CTRL 0x0968
#define mmHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3
// addressBlock: dce_dc_hpo_hdmi_stream_enc0_hdcp2_hdcp2_dispdec
// base address: 0x264f8

1907
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_sh_mask.h
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