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riscv: dts: thead: add ziccrse for th1520

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Existing rv64 hardware conforms to the rva20 profile.

Ziccrse is an additional extension required by the rva20 profile, so
th1520 has this extension.

Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Drew Fustini <fustini@kernel.org>
This commit is contained in:
Han Gao 2025-09-19 04:44:48 +08:00 committed by Drew Fustini
parent aef6dc0066
commit bcc3b9c5de
1 changed files with 16 additions and 8 deletions
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24
arch/riscv/boot/dts/thead/th1520.dtsi
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@ -24,8 +24,10 @@ c910_0: cpu@0 {
device_type = "cpu";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm", "xtheadvector";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"xtheadvector";
thead,vlenb = <16>;
reg = <0>;
i-cache-block-size = <64>;
@ -49,8 +51,10 @@ c910_1: cpu@1 {
device_type = "cpu";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm", "xtheadvector";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"xtheadvector";
thead,vlenb = <16>;
reg = <1>;
i-cache-block-size = <64>;
@ -74,8 +78,10 @@ c910_2: cpu@2 {
device_type = "cpu";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm", "xtheadvector";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"xtheadvector";
thead,vlenb = <16>;
reg = <2>;
i-cache-block-size = <64>;
@ -99,8 +105,10 @@ c910_3: cpu@3 {
device_type = "cpu";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm", "xtheadvector";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm",
"xtheadvector";
thead,vlenb = <16>;
reg = <3>;
i-cache-block-size = <64>;