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mfd: intel-m10-bmc: Prefix register defines with M10BMC_N3000
Prefix the M10BMC defines register defines with M10BMC_N3000 to make it more obvious these are related to some board type. All current non-N3000 board types have the same layout so they'll be reused. The less generic makes it more obvious they're not meant for the generic/interface agnostic code. Reviewed-by: Russ Weight <russell.h.weight@intel.com> Reviewed-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Lee Jones <lee@kernel.org> Link: https://lore.kernel.org/r/20230116100845.6153-8-ilpo.jarvinen@linux.intel.com
This commit is contained in:
Ilpo Järvinen
Lee Jones
parent
3e10c805b3
commit
bcababfc60
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@ -58,12 +58,12 @@ static ssize_t mac_address_show(struct device *dev,
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return ret;
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return sysfs_emit(buf, "%02x:%02x:%02x:%02x:%02x:%02x\n",
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(u8)FIELD_GET(M10BMC_MAC_BYTE1, macaddr_low),
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(u8)FIELD_GET(M10BMC_MAC_BYTE2, macaddr_low),
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(u8)FIELD_GET(M10BMC_MAC_BYTE3, macaddr_low),
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(u8)FIELD_GET(M10BMC_MAC_BYTE4, macaddr_low),
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(u8)FIELD_GET(M10BMC_MAC_BYTE5, macaddr_high),
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(u8)FIELD_GET(M10BMC_MAC_BYTE6, macaddr_high));
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(u8)FIELD_GET(M10BMC_N3000_MAC_BYTE1, macaddr_low),
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(u8)FIELD_GET(M10BMC_N3000_MAC_BYTE2, macaddr_low),
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(u8)FIELD_GET(M10BMC_N3000_MAC_BYTE3, macaddr_low),
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(u8)FIELD_GET(M10BMC_N3000_MAC_BYTE4, macaddr_low),
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(u8)FIELD_GET(M10BMC_N3000_MAC_BYTE5, macaddr_high),
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(u8)FIELD_GET(M10BMC_N3000_MAC_BYTE6, macaddr_high));
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}
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static DEVICE_ATTR_RO(mac_address);
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@ -78,7 +78,7 @@ static ssize_t mac_count_show(struct device *dev,
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if (ret)
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return ret;
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return sysfs_emit(buf, "%u\n", (u8)FIELD_GET(M10BMC_MAC_COUNT, macaddr_high));
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return sysfs_emit(buf, "%u\n", (u8)FIELD_GET(M10BMC_N3000_MAC_COUNT, macaddr_high));
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}
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static DEVICE_ATTR_RO(mac_count);
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@ -14,9 +14,9 @@
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#include <linux/spi/spi.h>
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static const struct regmap_range m10bmc_regmap_range[] = {
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regmap_reg_range(M10BMC_LEGACY_BUILD_VER, M10BMC_LEGACY_BUILD_VER),
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regmap_reg_range(M10BMC_SYS_BASE, M10BMC_SYS_END),
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regmap_reg_range(M10BMC_FLASH_BASE, M10BMC_FLASH_END),
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regmap_reg_range(M10BMC_N3000_LEGACY_BUILD_VER, M10BMC_N3000_LEGACY_BUILD_VER),
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regmap_reg_range(M10BMC_N3000_SYS_BASE, M10BMC_N3000_SYS_END),
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regmap_reg_range(M10BMC_N3000_FLASH_BASE, M10BMC_N3000_FLASH_END),
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};
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static const struct regmap_access_table m10bmc_access_table = {
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@ -30,7 +30,7 @@ static struct regmap_config intel_m10bmc_regmap_config = {
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.reg_stride = 4,
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.wr_table = &m10bmc_access_table,
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.rd_table = &m10bmc_access_table,
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.max_register = M10BMC_MEM_END,
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.max_register = M10BMC_N3000_MEM_END,
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};
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static int check_m10bmc_version(struct intel_m10bmc *ddata)
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@ -41,16 +41,16 @@ static int check_m10bmc_version(struct intel_m10bmc *ddata)
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/*
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* This check is to filter out the very old legacy BMC versions. In the
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* old BMC chips, the BMC version info is stored in the old version
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* register (M10BMC_LEGACY_BUILD_VER), so its read out value would have
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* not been M10BMC_VER_LEGACY_INVALID (0xffffffff). But in new BMC
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* register (M10BMC_N3000_LEGACY_BUILD_VER), so its read out value would have
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* not been M10BMC_N3000_VER_LEGACY_INVALID (0xffffffff). But in new BMC
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* chips that the driver supports, the value of this register should be
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* M10BMC_VER_LEGACY_INVALID.
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* M10BMC_N3000_VER_LEGACY_INVALID.
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*/
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ret = m10bmc_raw_read(ddata, M10BMC_LEGACY_BUILD_VER, &v);
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ret = m10bmc_raw_read(ddata, M10BMC_N3000_LEGACY_BUILD_VER, &v);
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if (ret)
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return -ENODEV;
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if (v != M10BMC_VER_LEGACY_INVALID) {
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if (v != M10BMC_N3000_VER_LEGACY_INVALID) {
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dev_err(ddata->dev, "bad version M10BMC detected\n");
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return -ENODEV;
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}
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@ -92,23 +92,23 @@ static int intel_m10_bmc_spi_probe(struct spi_device *spi)
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}
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static const struct m10bmc_csr_map m10bmc_n3000_csr_map = {
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.base = M10BMC_SYS_BASE,
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.build_version = M10BMC_BUILD_VER,
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.fw_version = NIOS2_FW_VERSION,
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.mac_low = M10BMC_MAC_LOW,
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.mac_high = M10BMC_MAC_HIGH,
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.doorbell = M10BMC_DOORBELL,
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.auth_result = M10BMC_AUTH_RESULT,
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.bmc_prog_addr = BMC_PROG_ADDR,
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.bmc_reh_addr = BMC_REH_ADDR,
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.bmc_magic = BMC_PROG_MAGIC,
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.sr_prog_addr = SR_PROG_ADDR,
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.sr_reh_addr = SR_REH_ADDR,
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.sr_magic = SR_PROG_MAGIC,
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.pr_prog_addr = PR_PROG_ADDR,
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.pr_reh_addr = PR_REH_ADDR,
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.pr_magic = PR_PROG_MAGIC,
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.rsu_update_counter = STAGING_FLASH_COUNT,
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.base = M10BMC_N3000_SYS_BASE,
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.build_version = M10BMC_N3000_BUILD_VER,
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.fw_version = NIOS2_N3000_FW_VERSION,
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.mac_low = M10BMC_N3000_MAC_LOW,
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.mac_high = M10BMC_N3000_MAC_HIGH,
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.doorbell = M10BMC_N3000_DOORBELL,
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.auth_result = M10BMC_N3000_AUTH_RESULT,
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.bmc_prog_addr = M10BMC_N3000_BMC_PROG_ADDR,
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.bmc_reh_addr = M10BMC_N3000_BMC_REH_ADDR,
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.bmc_magic = M10BMC_N3000_BMC_PROG_MAGIC,
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.sr_prog_addr = M10BMC_N3000_SR_PROG_ADDR,
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.sr_reh_addr = M10BMC_N3000_SR_REH_ADDR,
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.sr_magic = M10BMC_N3000_SR_PROG_MAGIC,
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.pr_prog_addr = M10BMC_N3000_PR_PROG_ADDR,
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.pr_reh_addr = M10BMC_N3000_PR_REH_ADDR,
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.pr_magic = M10BMC_N3000_PR_PROG_MAGIC,
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.rsu_update_counter = M10BMC_N3000_STAGING_FLASH_COUNT,
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};
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static struct mfd_cell m10bmc_d5005_subdevs[] = {
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@ -12,38 +12,38 @@
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#include <linux/dev_printk.h>
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#include <linux/regmap.h>
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#define M10BMC_LEGACY_BUILD_VER 0x300468
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#define M10BMC_SYS_BASE 0x300800
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#define M10BMC_SYS_END 0x300fff
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#define M10BMC_FLASH_BASE 0x10000000
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#define M10BMC_FLASH_END 0x1fffffff
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#define M10BMC_MEM_END M10BMC_FLASH_END
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#define M10BMC_N3000_LEGACY_BUILD_VER 0x300468
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#define M10BMC_N3000_SYS_BASE 0x300800
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#define M10BMC_N3000_SYS_END 0x300fff
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#define M10BMC_N3000_FLASH_BASE 0x10000000
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#define M10BMC_N3000_FLASH_END 0x1fffffff
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#define M10BMC_N3000_MEM_END M10BMC_N3000_FLASH_END
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#define M10BMC_STAGING_BASE 0x18000000
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#define M10BMC_STAGING_SIZE 0x3800000
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/* Register offset of system registers */
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#define NIOS2_FW_VERSION 0x0
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#define M10BMC_MAC_LOW 0x10
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#define M10BMC_MAC_BYTE4 GENMASK(7, 0)
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#define M10BMC_MAC_BYTE3 GENMASK(15, 8)
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#define M10BMC_MAC_BYTE2 GENMASK(23, 16)
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#define M10BMC_MAC_BYTE1 GENMASK(31, 24)
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#define M10BMC_MAC_HIGH 0x14
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#define M10BMC_MAC_BYTE6 GENMASK(7, 0)
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#define M10BMC_MAC_BYTE5 GENMASK(15, 8)
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#define M10BMC_MAC_COUNT GENMASK(23, 16)
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#define M10BMC_TEST_REG 0x3c
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#define M10BMC_BUILD_VER 0x68
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#define M10BMC_VER_MAJOR_MSK GENMASK(23, 16)
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#define M10BMC_VER_PCB_INFO_MSK GENMASK(31, 24)
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#define M10BMC_VER_LEGACY_INVALID 0xffffffff
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#define NIOS2_N3000_FW_VERSION 0x0
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#define M10BMC_N3000_MAC_LOW 0x10
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#define M10BMC_N3000_MAC_BYTE4 GENMASK(7, 0)
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#define M10BMC_N3000_MAC_BYTE3 GENMASK(15, 8)
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#define M10BMC_N3000_MAC_BYTE2 GENMASK(23, 16)
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#define M10BMC_N3000_MAC_BYTE1 GENMASK(31, 24)
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#define M10BMC_N3000_MAC_HIGH 0x14
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#define M10BMC_N3000_MAC_BYTE6 GENMASK(7, 0)
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#define M10BMC_N3000_MAC_BYTE5 GENMASK(15, 8)
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#define M10BMC_N3000_MAC_COUNT GENMASK(23, 16)
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#define M10BMC_N3000_TEST_REG 0x3c
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#define M10BMC_N3000_BUILD_VER 0x68
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#define M10BMC_N3000_VER_MAJOR_MSK GENMASK(23, 16)
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#define M10BMC_N3000_VER_PCB_INFO_MSK GENMASK(31, 24)
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#define M10BMC_N3000_VER_LEGACY_INVALID 0xffffffff
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/* Secure update doorbell register, in system register region */
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#define M10BMC_DOORBELL 0x400
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#define M10BMC_N3000_DOORBELL 0x400
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/* Authorization Result register, in system register region */
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#define M10BMC_AUTH_RESULT 0x404
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#define M10BMC_N3000_AUTH_RESULT 0x404
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/* Doorbell register fields */
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#define DRBL_RSU_REQUEST BIT(0)
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@ -106,20 +106,20 @@
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#define RSU_COMPLETE_TIMEOUT_MS (40 * 60 * 1000)
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/* Addresses for security related data in FLASH */
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#define BMC_REH_ADDR 0x17ffc004
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#define BMC_PROG_ADDR 0x17ffc000
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#define BMC_PROG_MAGIC 0x5746
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#define M10BMC_N3000_BMC_REH_ADDR 0x17ffc004
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#define M10BMC_N3000_BMC_PROG_ADDR 0x17ffc000
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#define M10BMC_N3000_BMC_PROG_MAGIC 0x5746
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#define SR_REH_ADDR 0x17ffd004
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#define SR_PROG_ADDR 0x17ffd000
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#define SR_PROG_MAGIC 0x5253
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#define M10BMC_N3000_SR_REH_ADDR 0x17ffd004
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#define M10BMC_N3000_SR_PROG_ADDR 0x17ffd000
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#define M10BMC_N3000_SR_PROG_MAGIC 0x5253
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#define PR_REH_ADDR 0x17ffe004
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#define PR_PROG_ADDR 0x17ffe000
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#define PR_PROG_MAGIC 0x5250
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#define M10BMC_N3000_PR_REH_ADDR 0x17ffe004
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#define M10BMC_N3000_PR_PROG_ADDR 0x17ffe000
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#define M10BMC_N3000_PR_PROG_MAGIC 0x5250
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/* Address of 4KB inverted bit vector containing staging area FLASH count */
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#define STAGING_FLASH_COUNT 0x17ffb000
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#define M10BMC_N3000_STAGING_FLASH_COUNT 0x17ffb000
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/**
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* struct m10bmc_csr_map - Intel MAX 10 BMC CSR register map
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