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interconnect: qcom: qcs8300: enable QoS configuration

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Enable QoS configuration for master ports with predefined priority
and urgency forwarding.

Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://msgid.link/20260127090116.1438780-3-odelu.kukatla@oss.qualcomm.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
This commit is contained in:
Odelu Kukatla 2026-01-27 14:31:15 +05:30 committed by Georgi Djakov
parent 28a70e7939
commit bc888ba1d4
1 changed files with 375 additions and 0 deletions
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375
drivers/interconnect/qcom/qcs8300.c
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@ -186,6 +186,13 @@ static struct qcom_icc_node qxm_qup3 = {
.name = "qxm_qup3",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x11000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = { &qns_a1noc_snoc },
};
@ -194,6 +201,13 @@ static struct qcom_icc_node xm_emac_0 = {
.name = "xm_emac_0",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x12000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = { &qns_a1noc_snoc },
};
@ -202,6 +216,13 @@ static struct qcom_icc_node xm_sdc1 = {
.name = "xm_sdc1",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x14000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = { &qns_a1noc_snoc },
};
@ -210,6 +231,13 @@ static struct qcom_icc_node xm_ufs_mem = {
.name = "xm_ufs_mem",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x15000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = { &qns_a1noc_snoc },
};
@ -218,6 +246,13 @@ static struct qcom_icc_node xm_usb2_2 = {
.name = "xm_usb2_2",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x16000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = { &qns_a1noc_snoc },
};
@ -226,6 +261,13 @@ static struct qcom_icc_node xm_usb3_0 = {
.name = "xm_usb3_0",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x17000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = { &qns_a1noc_snoc },
};
@ -234,6 +276,13 @@ static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
.channels = 1,
.buswidth = 4,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x14000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = { &qns_a2noc_snoc },
};
@ -242,6 +291,13 @@ static struct qcom_icc_node qhm_qup0 = {
.name = "qhm_qup0",
.channels = 1,
.buswidth = 4,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x17000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = { &qns_a2noc_snoc },
};
@ -250,6 +306,13 @@ static struct qcom_icc_node qhm_qup1 = {
.name = "qhm_qup1",
.channels = 1,
.buswidth = 4,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x12000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = { &qns_a2noc_snoc },
};
@ -258,6 +321,13 @@ static struct qcom_icc_node qnm_cnoc_datapath = {
.name = "qnm_cnoc_datapath",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x16000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = { &qns_a2noc_snoc },
};
@ -266,6 +336,13 @@ static struct qcom_icc_node qxm_crypto_0 = {
.name = "qxm_crypto_0",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x18000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = { &qns_a2noc_snoc },
};
@ -274,6 +351,13 @@ static struct qcom_icc_node qxm_crypto_1 = {
.name = "qxm_crypto_1",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x1a000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = { &qns_a2noc_snoc },
};
@ -282,6 +366,13 @@ static struct qcom_icc_node qxm_ipa = {
.name = "qxm_ipa",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x11000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = { &qns_a2noc_snoc },
};
@ -290,6 +381,13 @@ static struct qcom_icc_node xm_qdss_etr_0 = {
.name = "xm_qdss_etr_0",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x13000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = { &qns_a2noc_snoc },
};
@ -298,6 +396,13 @@ static struct qcom_icc_node xm_qdss_etr_1 = {
.name = "xm_qdss_etr_1",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x19000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = { &qns_a2noc_snoc },
};
@ -390,6 +495,13 @@ static struct qcom_icc_node alm_gpu_tcu = {
.name = "alm_gpu_tcu",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0xaf000 },
.prio_fwd_disable = 1,
.prio = 1,
.urg_fwd = 0,
},
.num_links = 2,
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
@ -398,6 +510,13 @@ static struct qcom_icc_node alm_pcie_tcu = {
.name = "alm_pcie_tcu",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0xb0000 },
.prio_fwd_disable = 1,
.prio = 3,
.urg_fwd = 0,
},
.num_links = 2,
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
@ -406,6 +525,13 @@ static struct qcom_icc_node alm_sys_tcu = {
.name = "alm_sys_tcu",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0xb1000 },
.prio_fwd_disable = 1,
.prio = 6,
.urg_fwd = 0,
},
.num_links = 2,
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
@ -423,6 +549,13 @@ static struct qcom_icc_node qnm_cmpnoc0 = {
.name = "qnm_cmpnoc0",
.channels = 2,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 2,
.port_offsets = { 0xf6000, 0xf7000 },
.prio_fwd_disable = 1,
.prio = 0,
.urg_fwd = 0,
},
.num_links = 2,
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
@ -448,6 +581,13 @@ static struct qcom_icc_node qnm_gpu = {
.name = "qnm_gpu",
.channels = 2,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 2,
.port_offsets = { 0xf0000, 0xf1000 },
.prio_fwd_disable = 1,
.prio = 0,
.urg_fwd = 0,
},
.num_links = 2,
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
@ -456,6 +596,13 @@ static struct qcom_icc_node qnm_mnoc_hf = {
.name = "qnm_mnoc_hf",
.channels = 2,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 2,
.port_offsets = { 0xf2000, 0xf3000 },
.prio_fwd_disable = 0,
.prio = 0,
.urg_fwd = 1,
},
.num_links = 2,
.link_nodes = { &qns_llcc, &qns_pcie },
};
@ -464,6 +611,13 @@ static struct qcom_icc_node qnm_mnoc_sf = {
.name = "qnm_mnoc_sf",
.channels = 2,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 2,
.port_offsets = { 0xf4000, 0xf5000 },
.prio_fwd_disable = 0,
.prio = 0,
.urg_fwd = 1,
},
.num_links = 3,
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
&qns_pcie },
@ -473,6 +627,13 @@ static struct qcom_icc_node qnm_pcie = {
.name = "qnm_pcie",
.channels = 1,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0xb3000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 2,
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
@ -481,6 +642,13 @@ static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0xb4000 },
.prio_fwd_disable = 0,
.prio = 0,
.urg_fwd = 1,
},
.num_links = 1,
.link_nodes = { &qns_llcc },
};
@ -489,6 +657,13 @@ static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
.channels = 1,
.buswidth = 16,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0xb5000 },
.prio_fwd_disable = 0,
.prio = 0,
.urg_fwd = 1,
},
.num_links = 3,
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
&qns_pcie },
@ -541,6 +716,13 @@ static struct qcom_icc_node qnm_camnoc_hf = {
.name = "qnm_camnoc_hf",
.channels = 1,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0xa000 },
.prio_fwd_disable = 0,
.prio = 0,
.urg_fwd = 1,
},
.num_links = 1,
.link_nodes = { &qns_mem_noc_hf },
};
@ -549,6 +731,13 @@ static struct qcom_icc_node qnm_camnoc_icp = {
.name = "qnm_camnoc_icp",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x2a000 },
.prio_fwd_disable = 0,
.prio = 0,
.urg_fwd = 1,
},
.num_links = 1,
.link_nodes = { &qns_mem_noc_sf },
};
@ -557,6 +746,13 @@ static struct qcom_icc_node qnm_camnoc_sf = {
.name = "qnm_camnoc_sf",
.channels = 1,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x2a080 },
.prio_fwd_disable = 0,
.prio = 0,
.urg_fwd = 1,
},
.num_links = 1,
.link_nodes = { &qns_mem_noc_sf },
};
@ -565,6 +761,13 @@ static struct qcom_icc_node qnm_mdp0_0 = {
.name = "qnm_mdp0_0",
.channels = 1,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0xa080 },
.prio_fwd_disable = 0,
.prio = 0,
.urg_fwd = 1,
},
.num_links = 1,
.link_nodes = { &qns_mem_noc_hf },
};
@ -573,6 +776,13 @@ static struct qcom_icc_node qnm_mdp0_1 = {
.name = "qnm_mdp0_1",
.channels = 1,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0xa180 },
.prio_fwd_disable = 0,
.prio = 0,
.urg_fwd = 1,
},
.num_links = 1,
.link_nodes = { &qns_mem_noc_hf },
};
@ -597,6 +807,13 @@ static struct qcom_icc_node qnm_video0 = {
.name = "qnm_video0",
.channels = 1,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x2a100 },
.prio_fwd_disable = 0,
.prio = 0,
.urg_fwd = 1,
},
.num_links = 1,
.link_nodes = { &qns_mem_noc_sf },
};
@ -605,6 +822,13 @@ static struct qcom_icc_node qnm_video_cvp = {
.name = "qnm_video_cvp",
.channels = 1,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x2a200 },
.prio_fwd_disable = 0,
.prio = 0,
.urg_fwd = 1,
},
.num_links = 1,
.link_nodes = { &qns_mem_noc_sf },
};
@ -613,6 +837,13 @@ static struct qcom_icc_node qnm_video_v_cpu = {
.name = "qnm_video_v_cpu",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x2a280 },
.prio_fwd_disable = 0,
.prio = 0,
.urg_fwd = 1,
},
.num_links = 1,
.link_nodes = { &qns_mem_noc_sf },
};
@ -637,6 +868,13 @@ static struct qcom_icc_node xm_pcie3_0 = {
.name = "xm_pcie3_0",
.channels = 1,
.buswidth = 16,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0xb000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = { &qns_pcie_mem_noc },
};
@ -645,6 +883,13 @@ static struct qcom_icc_node xm_pcie3_1 = {
.name = "xm_pcie3_1",
.channels = 1,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0xc000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = { &qns_pcie_mem_noc },
};
@ -653,6 +898,13 @@ static struct qcom_icc_node qhm_gic = {
.name = "qhm_gic",
.channels = 1,
.buswidth = 4,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x14000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = { &qns_gemnoc_sf },
};
@ -677,6 +929,13 @@ static struct qcom_icc_node qnm_lpass_noc = {
.name = "qnm_lpass_noc",
.channels = 1,
.buswidth = 16,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x12000 },
.prio_fwd_disable = 0,
.prio = 0,
.urg_fwd = 1,
},
.num_links = 1,
.link_nodes = { &qns_gemnoc_sf },
};
@ -693,6 +952,13 @@ static struct qcom_icc_node qxm_pimem = {
.name = "qxm_pimem",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x13000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = { &qns_gemnoc_gc },
};
@ -701,6 +967,13 @@ static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x15000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = { &qns_gemnoc_gc },
};
@ -1599,11 +1872,21 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
};
static const struct regmap_config qcs8300_aggre1_noc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x17080,
.fast_io = true,
};
static const struct qcom_icc_desc qcs8300_aggre1_noc = {
.config = &qcs8300_aggre1_noc_regmap_config,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
.qos_requires_clocks = true,
};
static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
@ -1624,11 +1907,21 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
[SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
};
static const struct regmap_config qcs8300_aggre2_noc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x1a080,
.fast_io = true,
};
static const struct qcom_icc_desc qcs8300_aggre2_noc = {
.config = &qcs8300_aggre2_noc_regmap_config,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
.qos_requires_clocks = true,
};
static struct qcom_icc_bcm * const clk_virt_bcms[] = {
@ -1740,7 +2033,16 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
[SLAVE_TCU] = &xs_sys_tcu_cfg,
};
static const struct regmap_config qcs8300_config_noc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x13080,
.fast_io = true,
};
static const struct qcom_icc_desc qcs8300_config_noc = {
.config = &qcs8300_config_noc_regmap_config,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@ -1753,7 +2055,16 @@ static struct qcom_icc_node * const dc_noc_nodes[] = {
[SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
};
static const struct regmap_config qcs8300_dc_noc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x5080,
.fast_io = true,
};
static const struct qcom_icc_desc qcs8300_dc_noc = {
.config = &qcs8300_dc_noc_regmap_config,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
};
@ -1786,11 +2097,21 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
[SLAVE_SERVICE_GEM_NOC2] = &srvc_sys_gemnoc_2,
};
static const struct regmap_config qcs8300_gem_noc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xf7080,
.fast_io = true,
};
static const struct qcom_icc_desc qcs8300_gem_noc = {
.config = &qcs8300_gem_noc_regmap_config,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
.qos_requires_clocks = true,
};
static struct qcom_icc_bcm * const gpdsp_anoc_bcms[] = {
@ -1803,7 +2124,16 @@ static struct qcom_icc_node * const gpdsp_anoc_nodes[] = {
[SLAVE_GP_DSP_SAIL_NOC] = &qns_gp_dsp_sail_noc,
};
static const struct regmap_config qcs8300_gpdsp_anoc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xd080,
.fast_io = true,
};
static const struct qcom_icc_desc qcs8300_gpdsp_anoc = {
.config = &qcs8300_gpdsp_anoc_regmap_config,
.nodes = gpdsp_anoc_nodes,
.num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes),
.bcms = gpdsp_anoc_bcms,
@ -1826,7 +2156,16 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
[SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
};
static const struct regmap_config qcs8300_lpass_ag_noc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x17200,
.fast_io = true,
};
static const struct qcom_icc_desc qcs8300_lpass_ag_noc = {
.config = &qcs8300_lpass_ag_noc_regmap_config,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
.bcms = lpass_ag_noc_bcms,
@ -1872,7 +2211,16 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
[SLAVE_SERVICE_MNOC_SF] = &srvc_mnoc_sf,
};
static const struct regmap_config qcs8300_mmss_noc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x40000,
.fast_io = true,
};
static const struct qcom_icc_desc qcs8300_mmss_noc = {
.config = &qcs8300_mmss_noc_regmap_config,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@ -1892,7 +2240,16 @@ static struct qcom_icc_node * const nspa_noc_nodes[] = {
[SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
};
static const struct regmap_config qcs8300_nspa_noc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x16080,
.fast_io = true,
};
static const struct qcom_icc_desc qcs8300_nspa_noc = {
.config = &qcs8300_nspa_noc_regmap_config,
.nodes = nspa_noc_nodes,
.num_nodes = ARRAY_SIZE(nspa_noc_nodes),
.bcms = nspa_noc_bcms,
@ -1909,7 +2266,16 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = {
[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
};
static const struct regmap_config qcs8300_pcie_anoc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xc080,
.fast_io = true,
};
static const struct qcom_icc_desc qcs8300_pcie_anoc = {
.config = &qcs8300_pcie_anoc_regmap_config,
.nodes = pcie_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
.bcms = pcie_anoc_bcms,
@ -1937,7 +2303,16 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
[SLAVE_SERVICE_SNOC] = &srvc_snoc,
};
static const struct regmap_config qcs8300_system_noc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x15080,
.fast_io = true,
};
static const struct qcom_icc_desc qcs8300_system_noc = {
.config = &qcs8300_system_noc_regmap_config,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,