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dt-bindings: clock: qcom: nord-negcc: Add the secondary QUSB2 PHY reset

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The NE_GCC block has two eUSB2 PHY block resets - PRIM and SEC - but
right now only the primary is registered. Add the secondary, which is
required by the usb_1 eUSB2 PHY.

Note that the SoC has three eUSB2 PHYs but only these two QUSB2PHY
resets: the HS-only USB20 tile has no dedicated QUSB2PHY reset and
is instead reset as a whole via NE_GCC_USB20_PRIM_BCR.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://patch.msgid.link/20260901035322.654-2-shengchao.guo@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Bartosz Golaszewski 2026-09-01 11:53:21 +08:00 committed by Bjorn Andersson
parent cbe415e116
commit bc07c3a511
1 changed files with 1 additions and 0 deletions
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1
include/dt-bindings/clock/qcom,nord-negcc.h
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@ -121,5 +121,6 @@
#define NE_GCC_USB3PHY_PHY_PRIM_BCR 11
#define NE_GCC_USB3PHY_PHY_SEC_BCR 12
#define NE_GCC_QUSB2PHY_PRIM_BCR 13
#define NE_GCC_QUSB2PHY_SEC_BCR 14
#endif