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net: dsa: netc: add phylink MAC operations
Different versions of NETC switches have different numbers of ports and MAC capabilities. Add .phylink_get_caps() to struct netc_switch_info, allowing each NETC switch version to implement its own callback for obtaining MAC capabilities. Implement the phylink_mac_ops callbacks: .mac_config(), .mac_link_up(), and .mac_link_down(). Note that flow-control configuration is not yet supported in .mac_link_up(), but will be implemented in a subsequent patch. Signed-off-by: Wei Fang <wei.fang@nxp.com> Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Link: https://patch.msgid.link/20260518082506.1318236-12-wei.fang@nxp.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Wei Fang
Paolo Abeni
parent
187fbae024
commit
bbe97e3472
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@ -43,6 +43,30 @@ static void netc_mac_port_wr(struct netc_port *np, u32 reg, u32 val)
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netc_port_wr(np, reg + NETC_PMAC_OFFSET, val);
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}
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/* netc_mac_port_rmw() is used to synchronize the configurations of eMAC
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* and pMAC to maintain consistency. This function should not be used if
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* differentiated settings are required.
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*/
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static void netc_mac_port_rmw(struct netc_port *np, u32 reg,
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u32 mask, u32 val)
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{
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u32 old, new;
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if (is_netc_pseudo_port(np))
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return;
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WARN_ON((mask | val) != mask);
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old = netc_port_rd(np, reg);
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new = (old & ~mask) | val;
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if (new == old)
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return;
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netc_port_wr(np, reg, new);
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if (np->caps.pmac)
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netc_port_wr(np, reg + NETC_PMAC_OFFSET, new);
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}
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static void netc_port_get_capability(struct netc_port *np)
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{
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u32 val;
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@ -507,10 +531,232 @@ static void netc_switch_get_ip_revision(struct netc_switch *priv)
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priv->revision = FIELD_GET(IPBRR0_IP_REV, val);
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}
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static void netc_phylink_get_caps(struct dsa_switch *ds, int port,
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struct phylink_config *config)
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{
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struct netc_switch *priv = ds->priv;
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priv->info->phylink_get_caps(port, config);
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}
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static void netc_port_set_mac_mode(struct netc_port *np,
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unsigned int mode,
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phy_interface_t phy_mode)
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{
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u32 mask = PM_IF_MODE_IFMODE | PM_IF_MODE_REVMII;
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u32 val = 0;
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switch (phy_mode) {
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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val |= IFMODE_RGMII;
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break;
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case PHY_INTERFACE_MODE_RMII:
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val |= IFMODE_RMII;
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break;
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case PHY_INTERFACE_MODE_REVMII:
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val |= PM_IF_MODE_REVMII;
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fallthrough;
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case PHY_INTERFACE_MODE_MII:
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val |= IFMODE_MII;
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break;
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_2500BASEX:
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val |= IFMODE_SGMII;
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break;
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default:
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break;
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}
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netc_mac_port_rmw(np, NETC_PM_IF_MODE(0), mask, val);
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}
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static void netc_mac_config(struct phylink_config *config, unsigned int mode,
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const struct phylink_link_state *state)
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{
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struct dsa_port *dp = dsa_phylink_to_port(config);
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netc_port_set_mac_mode(NETC_PORT(dp->ds, dp->index), mode,
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state->interface);
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}
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static void netc_port_set_speed(struct netc_port *np, int speed)
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{
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netc_port_rmw(np, NETC_PCR, PCR_PSPEED, PSPEED_SET_VAL(speed));
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}
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static void netc_port_set_rgmii_mac(struct netc_port *np,
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int speed, int duplex)
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{
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u32 mask, val;
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mask = PM_IF_MODE_SSP | PM_IF_MODE_HD | PM_IF_MODE_M10;
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switch (speed) {
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default:
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case SPEED_1000:
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val = FIELD_PREP(PM_IF_MODE_SSP, SSP_1G);
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break;
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case SPEED_100:
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val = FIELD_PREP(PM_IF_MODE_SSP, SSP_100M);
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break;
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case SPEED_10:
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val = FIELD_PREP(PM_IF_MODE_SSP, SSP_10M);
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break;
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}
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if (duplex != DUPLEX_FULL)
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val |= PM_IF_MODE_HD;
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netc_mac_port_rmw(np, NETC_PM_IF_MODE(0), mask, val);
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}
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static void netc_port_set_rmii_mii_mac(struct netc_port *np,
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int speed, int duplex)
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{
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u32 mask, val = 0;
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mask = PM_IF_MODE_SSP | PM_IF_MODE_HD | PM_IF_MODE_M10;
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if (speed == SPEED_10)
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val |= PM_IF_MODE_M10;
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if (duplex != DUPLEX_FULL)
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val |= PM_IF_MODE_HD;
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netc_mac_port_rmw(np, NETC_PM_IF_MODE(0), mask, val);
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}
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static void netc_port_mac_rx_enable(struct netc_port *np)
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{
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netc_port_rmw(np, NETC_POR, POR_RXDIS, 0);
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netc_mac_port_rmw(np, NETC_PM_CMD_CFG(0), PM_CMD_CFG_RX_EN,
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PM_CMD_CFG_RX_EN);
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}
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static void netc_port_wait_rx_empty(struct netc_port *np, int mac)
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{
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u32 val;
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/* PM_IEVENT_RX_EMPTY is a read-only bit, it is automatically set by
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* hardware if RX FIFO is empty and no RX packet receive in process.
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* And it is automatically cleared if RX FIFO is not empty or RX
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* packet receive in process.
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*/
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if (read_poll_timeout(netc_port_rd, val, val & PM_IEVENT_RX_EMPTY,
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100, 10000, false, np, NETC_PM_IEVENT(mac)))
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dev_warn(np->switch_priv->dev,
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"swp%d MAC%d: RX is not idle\n", np->dp->index, mac);
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}
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static void netc_port_mac_rx_graceful_stop(struct netc_port *np)
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{
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u32 val;
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if (is_netc_pseudo_port(np))
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goto rx_disable;
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if (np->caps.pmac) {
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netc_port_rmw(np, NETC_PM_CMD_CFG(1), PM_CMD_CFG_RX_EN, 0);
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netc_port_wait_rx_empty(np, 1);
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}
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netc_port_rmw(np, NETC_PM_CMD_CFG(0), PM_CMD_CFG_RX_EN, 0);
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netc_port_wait_rx_empty(np, 0);
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if (read_poll_timeout(netc_port_rd, val, !(val & PSR_RX_BUSY),
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100, 10000, false, np, NETC_PSR))
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dev_warn(np->switch_priv->dev, "swp%d RX is busy\n",
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np->dp->index);
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rx_disable:
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netc_port_rmw(np, NETC_POR, POR_RXDIS, POR_RXDIS);
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}
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static void netc_port_mac_tx_enable(struct netc_port *np)
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{
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netc_mac_port_rmw(np, NETC_PM_CMD_CFG(0), PM_CMD_CFG_TX_EN,
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PM_CMD_CFG_TX_EN);
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netc_port_rmw(np, NETC_POR, POR_TXDIS, 0);
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}
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static void netc_port_wait_tx_empty(struct netc_port *np, int mac)
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{
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u32 val;
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/* PM_IEVENT_TX_EMPTY is a read-only bit, it is automatically set by
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* hardware if TX FIFO is empty. And it is automatically cleared if
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* TX FIFO is not empty.
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*/
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if (read_poll_timeout(netc_port_rd, val, val & PM_IEVENT_TX_EMPTY,
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100, 10000, false, np, NETC_PM_IEVENT(mac)))
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dev_warn(np->switch_priv->dev,
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"swp%d MAC%d: TX FIFO is not empty\n",
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np->dp->index, mac);
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}
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static void netc_port_mac_tx_graceful_stop(struct netc_port *np)
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{
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netc_port_rmw(np, NETC_POR, POR_TXDIS, POR_TXDIS);
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if (is_netc_pseudo_port(np))
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return;
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netc_port_wait_tx_empty(np, 0);
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if (np->caps.pmac)
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netc_port_wait_tx_empty(np, 1);
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netc_mac_port_rmw(np, NETC_PM_CMD_CFG(0), PM_CMD_CFG_TX_EN, 0);
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}
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static void netc_mac_link_up(struct phylink_config *config,
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struct phy_device *phy, unsigned int mode,
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phy_interface_t interface, int speed,
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int duplex, bool tx_pause, bool rx_pause)
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{
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struct dsa_port *dp = dsa_phylink_to_port(config);
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struct netc_port *np;
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np = NETC_PORT(dp->ds, dp->index);
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netc_port_set_speed(np, speed);
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if (phy_interface_mode_is_rgmii(interface))
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netc_port_set_rgmii_mac(np, speed, duplex);
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if (interface == PHY_INTERFACE_MODE_RMII ||
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interface == PHY_INTERFACE_MODE_REVMII ||
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interface == PHY_INTERFACE_MODE_MII)
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netc_port_set_rmii_mii_mac(np, speed, duplex);
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netc_port_mac_tx_enable(np);
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netc_port_mac_rx_enable(np);
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}
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static void netc_mac_link_down(struct phylink_config *config,
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unsigned int mode,
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phy_interface_t interface)
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{
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struct dsa_port *dp = dsa_phylink_to_port(config);
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struct netc_port *np;
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np = NETC_PORT(dp->ds, dp->index);
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netc_port_mac_rx_graceful_stop(np);
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netc_port_mac_tx_graceful_stop(np);
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}
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static const struct phylink_mac_ops netc_phylink_mac_ops = {
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.mac_config = netc_mac_config,
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.mac_link_up = netc_mac_link_up,
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.mac_link_down = netc_mac_link_down,
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};
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static const struct dsa_switch_ops netc_switch_ops = {
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.get_tag_protocol = netc_get_tag_protocol,
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.setup = netc_setup,
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.teardown = netc_teardown,
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.phylink_get_caps = netc_phylink_get_caps,
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};
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static int netc_switch_probe(struct pci_dev *pdev,
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@ -549,6 +795,7 @@ static int netc_switch_probe(struct pci_dev *pdev,
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ds->num_ports = priv->info->num_ports;
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ds->num_tx_queues = NETC_TC_NUM;
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ds->ops = &netc_switch_ops;
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ds->phylink_mac_ops = &netc_phylink_mac_ops;
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ds->priv = priv;
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priv->ds = ds;
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@ -11,8 +11,46 @@ struct netc_switch_platform {
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const struct netc_switch_info *info;
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};
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static void imx94_switch_phylink_get_caps(int port,
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struct phylink_config *config)
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{
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config->mac_capabilities = MAC_1000FD;
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switch (port) {
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case 0 ... 1:
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__set_bit(PHY_INTERFACE_MODE_SGMII,
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config->supported_interfaces);
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__set_bit(PHY_INTERFACE_MODE_2500BASEX,
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config->supported_interfaces);
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config->mac_capabilities |= MAC_2500FD;
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fallthrough;
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case 2:
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config->mac_capabilities |= MAC_10 | MAC_100;
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__set_bit(PHY_INTERFACE_MODE_MII,
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config->supported_interfaces);
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__set_bit(PHY_INTERFACE_MODE_RMII,
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config->supported_interfaces);
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/* Port 0 and 1 do not support REVMII */
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if (port == 2)
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__set_bit(PHY_INTERFACE_MODE_REVMII,
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config->supported_interfaces);
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phy_interface_set_rgmii(config->supported_interfaces);
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break;
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case 3: /* CPU port */
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__set_bit(PHY_INTERFACE_MODE_INTERNAL,
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config->supported_interfaces);
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config->mac_capabilities |= MAC_10FD | MAC_100FD |
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MAC_2500FD;
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break;
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default:
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break;
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}
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}
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static const struct netc_switch_info imx94_info = {
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.num_ports = 4,
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.phylink_get_caps = imx94_switch_phylink_get_caps,
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};
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static const struct netc_switch_platform netc_platforms[] = {
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@ -35,6 +35,7 @@ struct netc_switch;
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struct netc_switch_info {
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u32 num_ports;
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void (*phylink_get_caps)(int port, struct phylink_config *config);
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};
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struct netc_port_caps {
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@ -70,6 +71,9 @@ struct netc_switch {
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struct ntmp_user ntmp;
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};
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#define NETC_PRIV(ds) ((struct netc_switch *)((ds)->priv))
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#define NETC_PORT(ds, port_id) (NETC_PRIV(ds)->ports[(port_id)])
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/* Write/Read Switch base registers */
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#define netc_base_rd(r, o) netc_read((r)->base + (o))
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#define netc_base_wr(r, o, v) netc_write((r)->base + (o), v)
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@ -67,6 +67,14 @@
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#define PQOSMR_VQMP GENMASK(19, 16)
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#define PQOSMR_QVMP GENMASK(23, 20)
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#define NETC_POR 0x100
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#define POR_TXDIS BIT(0)
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#define POR_RXDIS BIT(1)
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#define NETC_PSR 0x104
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#define PSR_TX_BUSY BIT(0)
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#define PSR_RX_BUSY BIT(1)
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#define NETC_PTCTMSDUR(a) (0x208 + (a) * 0x20)
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#define PTCTMSDUR_MAXSDU GENMASK(15, 0)
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#define PTCTMSDUR_SDU_TYPE GENMASK(17, 16)
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@ -123,6 +131,24 @@ enum netc_mfo {
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#define NETC_PM_MAXFRM(a) (0x1014 + (a) * 0x400)
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#define PM_MAXFRAM GENMASK(15, 0)
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#define NETC_PM_IEVENT(a) (0x1040 + (a) * 0x400)
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#define PM_IEVENT_TX_EMPTY BIT(5)
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#define PM_IEVENT_RX_EMPTY BIT(6)
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#define NETC_PM_IF_MODE(a) (0x1300 + (a) * 0x400)
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#define PM_IF_MODE_IFMODE GENMASK(2, 0)
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#define IFMODE_MII 1
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#define IFMODE_RMII 3
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#define IFMODE_RGMII 4
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#define IFMODE_SGMII 5
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#define PM_IF_MODE_REVMII BIT(3)
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#define PM_IF_MODE_M10 BIT(4)
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#define PM_IF_MODE_HD BIT(6)
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#define PM_IF_MODE_SSP GENMASK(14, 13)
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#define SSP_100M 0
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#define SSP_10M 1
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#define SSP_1G 2
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#define NETC_PEMDIOCR 0x1c00
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#define NETC_EMDIO_BASE NETC_PEMDIOCR
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