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drm/i915/cx0: Rename intel_clear_response_ready flag

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Rename the non static intel_clear_response_ready_flag to
intel_cx0_clear_response_ready_flag so that we follow the
naming standards of non static function.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Nemesa Garg <nemesa.garg@intel.com>
Link: https://patch.msgid.link/20260122044859.753682-2-suraj.kandpal@intel.com
This commit is contained in:
Suraj Kandpal 2026-01-22 10:18:59 +05:30
parent f86bed1bc9
commit bbde2759de
3 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
drivers/gpu/drm/i915/display/intel_cx0_phy.c
View File

@ -128,8 +128,8 @@ static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, struct
intel_display_power_put(display, POWER_DOMAIN_DC_OFF, wakeref);
}
void intel_clear_response_ready_flag(struct intel_encoder *encoder,
int lane)
void intel_cx0_clear_response_ready_flag(struct intel_encoder *encoder,
int lane)
{
struct intel_display *display = to_intel_display(encoder);
@ -156,7 +156,7 @@ void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane)
return;
}
intel_clear_response_ready_flag(encoder, lane);
intel_cx0_clear_response_ready_flag(encoder, lane);
}
int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
@ -223,7 +223,7 @@ static int __intel_cx0_read_once(struct intel_encoder *encoder,
return -ETIMEDOUT;
}
intel_clear_response_ready_flag(encoder, lane);
intel_cx0_clear_response_ready_flag(encoder, lane);
intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING |
@ -234,7 +234,7 @@ static int __intel_cx0_read_once(struct intel_encoder *encoder,
if (ack < 0)
return ack;
intel_clear_response_ready_flag(encoder, lane);
intel_cx0_clear_response_ready_flag(encoder, lane);
/*
* FIXME: Workaround to let HW to settle
@ -296,7 +296,7 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
return -ETIMEDOUT;
}
intel_clear_response_ready_flag(encoder, lane);
intel_cx0_clear_response_ready_flag(encoder, lane);
intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING |
@ -326,7 +326,7 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
return -EINVAL;
}
intel_clear_response_ready_flag(encoder, lane);
intel_cx0_clear_response_ready_flag(encoder, lane);
/*
* FIXME: Workaround to let HW to settle

4
drivers/gpu/drm/i915/display/intel_cx0_phy.h
View File

@ -25,8 +25,8 @@ struct intel_dpll_hw_state;
struct intel_encoder;
struct intel_hdmi;
void intel_clear_response_ready_flag(struct intel_encoder *encoder,
int lane);
void intel_cx0_clear_response_ready_flag(struct intel_encoder *encoder,
int lane);
bool intel_encoder_is_c10phy(struct intel_encoder *encoder);
void intel_mtl_pll_enable(struct intel_encoder *encoder,
struct intel_dpll *pll,

2
drivers/gpu/drm/i915/display/intel_lt_phy.c
View File

@ -1053,7 +1053,7 @@ static int __intel_lt_phy_p2p_write_once(struct intel_encoder *encoder,
* This is the time PHY takes to settle down after programming the PHY.
*/
udelay(150);
intel_clear_response_ready_flag(encoder, lane);
intel_cx0_clear_response_ready_flag(encoder, lane);
intel_lt_phy_clear_status_p2p(encoder, lane);
return 0;