From bed18bbbf9d9af55ccc01a6e2a8ec90d7e35cb11 Mon Sep 17 00:00:00 2001 From: Calvin Owens Date: Mon, 25 May 2026 20:22:53 -0700 Subject: [PATCH 01/12] x86/cfi: Add __init_or_module annotations for fineibt I'm seeing some benign section mismatch warnings with fineibt when building kernels with CONFIG_MODULES=n: WARNING: modpost: vmlinux: section mismatch in reference: __apply_fineibt+0x1db (section: .text) -> text_poke_early (section: .init.text) WARNING: modpost: vmlinux: section mismatch in reference: __apply_fineibt+0x473 (section: .text) -> text_poke_early (section: .init.text) WARNING: modpost: vmlinux: section mismatch in reference: __apply_fineibt+0x57c (section: .text) -> text_poke_early (section: .init.text) WARNING: modpost: vmlinux: section mismatch in reference: __apply_fineibt+0x6d9 (section: .text) -> text_poke_early (section: .init.text) WARNING: modpost: vmlinux: section mismatch in reference: __apply_fineibt+0xb57 (section: .text) -> text_poke_early (section: .init.text) WARNING: modpost: vmlinux: section mismatch in reference: __apply_fineibt+0xb81 (section: .text) -> text_poke_early (section: .init.text) WARNING: modpost: vmlinux: section mismatch in reference: __apply_fineibt+0xd00 (section: .text) -> poison_endbr (section: .init.text) WARNING: modpost: vmlinux: section mismatch in reference: __apply_fineibt+0xdd3 (section: .text) -> text_poke_early (section: .init.text) WARNING: modpost: vmlinux: section mismatch in reference: __apply_fineibt+0xe58 (section: .text) -> text_poke_early (section: .init.text) WARNING: modpost: vmlinux: section mismatch in reference: __apply_fineibt+0xe85 (section: .text) -> text_poke_early (section: .init.text) WARNING: modpost: vmlinux: section mismatch in reference: apply_fineibt+0x8 (section: .text.unlikely.) -> __apply_fineibt (section: .init.text) Add the missing __init_or_module section annotations to fix the warnings, and also free up a tiny bit of memory after boot. Signed-off-by: Calvin Owens Signed-off-by: Borislav Petkov (AMD) Reviewed-by: Kees Cook Reviewed-by: Juergen Gross Link: https://patch.msgid.link/1f50aecf23311dc5ffb965c5ccfb8b49208dbb3f.1779763849.git.calvin@wbinvd.org --- arch/x86/kernel/alternative.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c index 62936a3bde19..400baffcd609 100644 --- a/arch/x86/kernel/alternative.c +++ b/arch/x86/kernel/alternative.c @@ -1775,8 +1775,8 @@ static int cfi_rewrite_callers(s32 *start, s32 *end) #define FINEIBT_WARN(_f, _v) \ WARN_ONCE((_f) != (_v), "FineIBT: " #_f " %ld != %d\n", _f, _v) -static void __apply_fineibt(s32 *start_retpoline, s32 *end_retpoline, - s32 *start_cfi, s32 *end_cfi, bool builtin) +static void __init_or_module __apply_fineibt(s32 *start_retpoline, s32 *end_retpoline, + s32 *start_cfi, s32 *end_cfi, bool builtin) { int ret; @@ -2088,8 +2088,8 @@ bool decode_fineibt_insn(struct pt_regs *regs, unsigned long *target, u32 *type) #else /* !CONFIG_FINEIBT: */ -static void __apply_fineibt(s32 *start_retpoline, s32 *end_retpoline, - s32 *start_cfi, s32 *end_cfi, bool builtin) +static void __init_or_module __apply_fineibt(s32 *start_retpoline, s32 *end_retpoline, + s32 *start_cfi, s32 *end_cfi, bool builtin) { if (IS_ENABLED(CONFIG_CFI) && builtin) pr_info("CFI: Using standard kCFI\n"); @@ -2101,8 +2101,8 @@ static void poison_cfi(void *addr) { } #endif /* !CONFIG_FINEIBT */ -void apply_fineibt(s32 *start_retpoline, s32 *end_retpoline, - s32 *start_cfi, s32 *end_cfi) +void __init_or_module apply_fineibt(s32 *start_retpoline, s32 *end_retpoline, + s32 *start_cfi, s32 *end_cfi) { return __apply_fineibt(start_retpoline, end_retpoline, start_cfi, end_cfi, From 0cfdf974f133e0ff17ed80e7895adbe7889d9522 Mon Sep 17 00:00:00 2001 From: Jens Remus Date: Thu, 11 Jun 2026 17:57:15 +0200 Subject: [PATCH 02/12] x86/cfi: Use symmetric SYM_START and SYM_END in __CFI_TYPE() Commit ccace936eec7 ("x86: Add types to indirectly called assembly functions") introduced a x86-specific implementation of __CFI_TYPE() using an asymmetric combination of SYM_START() and SYM_FUNC_END() to add a symbol to the KCFI type identifier that precedes a function. This asymmetric combination is an issue if SYM_FUNC_END() ever gets extended in a way that requires it to be used symmetrically with SYM_FUNC_START*(). For instance to emit DWARF CFI directives that denote the start/end of a function. [1] Use SYM_END() with SYM_T_FUNC instead. No functional change, as the generic implementation of SYM_FUNC_END(name) expands into SYM_END(name, SYM_T_FUNC). Fixes: ccace936eec7 ("x86: Add types to indirectly called assembly functions") Closes: https://sashiko.dev/#/patchset/20260522110427.2816637-1-jremus@linux.ibm.com?part=3 [1] Reported-by: Sashiko Signed-off-by: Jens Remus Signed-off-by: Borislav Petkov (AMD) Reviewed-by: Nathan Chancellor Acked-by: Peter Zijlstra (Intel) Link: https://patch.msgid.link/20260611155716.830563-1-jremus@linux.ibm.com --- arch/x86/include/asm/linkage.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/linkage.h b/arch/x86/include/asm/linkage.h index a7294656ad90..c9769a7b6e66 100644 --- a/arch/x86/include/asm/linkage.h +++ b/arch/x86/include/asm/linkage.h @@ -103,7 +103,7 @@ .byte 0xb8 ASM_NL \ .long __kcfi_typeid_##name ASM_NL \ CFI_POST_PADDING \ - SYM_FUNC_END(__cfi_##name) + SYM_END(__cfi_##name, SYM_T_FUNC) /* UML needs to be able to override memcpy() and friends for KASAN. */ #ifdef CONFIG_UML From b47748678c6cd831aba376f6b2d90b7718c7c661 Mon Sep 17 00:00:00 2001 From: Chao Gao Date: Thu, 19 Jun 2025 22:21:50 -0700 Subject: [PATCH 03/12] x86/fpu: Fix kernel-doc formatting above fpu_enable_guest_xfd_features() Adjust the indentation and use tabs between function parameters and their descriptions to align with the convention used in FPU code. Signed-off-by: Chao Gao Signed-off-by: Borislav Petkov (AMD) Link: https://patch.msgid.link/20250620052152.490414-1-chao.gao@intel.com --- arch/x86/kernel/fpu/core.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/x86/kernel/fpu/core.c b/arch/x86/kernel/fpu/core.c index 584fb9913be4..2ed26134c0d1 100644 --- a/arch/x86/kernel/fpu/core.c +++ b/arch/x86/kernel/fpu/core.c @@ -294,15 +294,15 @@ void fpu_free_guest_fpstate(struct fpu_guest *gfpu) } EXPORT_SYMBOL_FOR_KVM(fpu_free_guest_fpstate); -/* - * fpu_enable_guest_xfd_features - Check xfeatures against guest perm and enable - * @guest_fpu: Pointer to the guest FPU container - * @xfeatures: Features requested by guest CPUID - * - * Enable all dynamic xfeatures according to guest perm and requested CPUID. - * - * Return: 0 on success, error code otherwise - */ +/** + * fpu_enable_guest_xfd_features - Check xfeatures against guest perm and enable + * @guest_fpu: Pointer to the guest FPU container + * @xfeatures: Features requested by guest CPUID + * + * Enable all dynamic xfeatures according to guest perm and requested CPUID. + * + * Return: 0 on success, error code otherwise + */ int fpu_enable_guest_xfd_features(struct fpu_guest *guest_fpu, u64 xfeatures) { lockdep_assert_preemption_enabled(); From 324549c06eadc20c4ffcdcf808df2ba459c35ab1 Mon Sep 17 00:00:00 2001 From: You-Li Lin Date: Sat, 27 Jun 2026 13:13:43 +0800 Subject: [PATCH 04/12] x86/mm: Fix typo in comment Fix "begining" to "beginning" in a code comment. Signed-off-by: You-Li Lin Acked-by: Borislav Petkov Signed-off-by: Ingo Molnar Signed-off-by: Borislav Petkov (AMD) Link: https://patch.msgid.link/20260627051343.51326-1-lhu540507@gmail.com --- arch/x86/mm/ident_map.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/mm/ident_map.c b/arch/x86/mm/ident_map.c index bd5d101c5c37..5a15bffe6574 100644 --- a/arch/x86/mm/ident_map.c +++ b/arch/x86/mm/ident_map.c @@ -111,7 +111,7 @@ static int ident_pud_init(struct x86_mapping_info *info, pud_t *pud_page, use_gbpage = info->direct_gbpages; /* Don't use gbpage if it maps more than the requested region. */ - /* at the begining: */ + /* at the beginning: */ use_gbpage &= ((addr & ~PUD_MASK) == 0); /* ... or at the end: */ use_gbpage &= ((next & ~PUD_MASK) == 0); From 77d34d39509341d76ab10f63ef67648545c90da1 Mon Sep 17 00:00:00 2001 From: Borislav Petkov Date: Wed, 13 May 2026 22:07:13 +0200 Subject: [PATCH 05/12] x86/cpu: Move intel_get_platform_id() to cpu/intel.c It is not only used in the microcode loader anymore and the platform ID is cached in the cpuinfo_x86 structure so move the getter to Intel CPU-specific code. No functional changes. Signed-off-by: Borislav Petkov (AMD) Reviewed-by: Binbin Wu Reviewed-by: Xiaoyao Li Link: https://lore.kernel.org/all/20260430020953.1405535-1-binbin.wu@linux.intel.com --- arch/x86/include/asm/microcode.h | 2 -- arch/x86/include/asm/processor.h | 1 + arch/x86/kernel/cpu/intel.c | 35 ++++++++++++++++++++++++++ arch/x86/kernel/cpu/microcode/intel.c | 36 --------------------------- 4 files changed, 36 insertions(+), 38 deletions(-) diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h index 9cd136d4515c..645e65ac1586 100644 --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -62,8 +62,6 @@ static inline int intel_microcode_get_datasize(struct microcode_header_intel *hd return hdr->datasize ? : DEFAULT_UCODE_DATASIZE; } -extern u32 intel_get_platform_id(void); - static inline u32 intel_get_microcode_revision(void) { u32 rev, dummy; diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 87b1d4c0727e..8d8f890c4bc0 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -238,6 +238,7 @@ extern void early_cpu_init(void); extern void identify_secondary_cpu(unsigned int cpu); extern void print_cpu_info(struct cpuinfo_x86 *); void print_cpu_msr(struct cpuinfo_x86 *); +extern u32 intel_get_platform_id(void); /* * Friendlier CR3 helpers. diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index abb3984336eb..03073b90d2ec 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -199,6 +199,41 @@ void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c) c->cpuid_level = cpuid_eax(0); } +/* + * Use CPUID to generate a "vfm" value. Useful before cpuinfo_x86 + * structures are populated. + */ +static u32 intel_cpuid_vfm(void) +{ + u32 eax = cpuid_eax(1); + u32 fam = x86_family(eax); + u32 model = x86_model(eax); + + return IFM(fam, model); +} + +u32 intel_get_platform_id(void) +{ + unsigned int val[2]; + + if (x86_hypervisor_present) + return 0; + + /* + * This can be called early. Use CPUID directly instead of + * relying on cpuinfo_x86 which may not be fully initialized. + * The PII does not have MSR_IA32_PLATFORM_ID. Everything + * before _it_ has no microcode (for Linux at least). + */ + if (intel_cpuid_vfm() <= INTEL_PENTIUM_II_KLAMATH) + return 0; + + /* get processor flags from MSR 0x17 */ + native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); + + return (val[1] >> 18) & 7; +} + static void early_init_intel(struct cpuinfo_x86 *c) { u64 misc_enable; diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index f4a444e6114d..1142183c950c 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -121,42 +121,6 @@ static inline unsigned int exttable_size(struct extended_sigtable *et) return et->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE; } - -/* - * Use CPUID to generate a "vfm" value. Useful before cpuinfo_x86 - * structures are populated. - */ -static u32 intel_cpuid_vfm(void) -{ - u32 eax = cpuid_eax(1); - u32 fam = x86_family(eax); - u32 model = x86_model(eax); - - return IFM(fam, model); -} - -u32 intel_get_platform_id(void) -{ - unsigned int val[2]; - - if (x86_hypervisor_present) - return 0; - - /* - * This can be called early. Use CPUID directly instead of - * relying on cpuinfo_x86 which may not be fully initialized. - * The PII does not have MSR_IA32_PLATFORM_ID. Everything - * before _it_ has no microcode (for Linux at least). - */ - if (intel_cpuid_vfm() <= INTEL_PENTIUM_II_KLAMATH) - return 0; - - /* get processor flags from MSR 0x17 */ - native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); - - return (val[1] >> 18) & 7; -} - void intel_collect_cpu_info(struct cpu_signature *sig) { sig->sig = cpuid_eax(1); From c8e412f79db6a0c1a89e4289e593eb991a068bce Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Fri, 10 Apr 2026 14:27:48 +0200 Subject: [PATCH 06/12] x86/ras: Move contents from arch/x86/ras/Kconfig into drivers/ras/Kconfig Commit bc8e80d56c1ec ("x86/mce: Merge mce_amd_inj into mce-inject") removed the last .c file from arch/x86/ras/, so that there is now only a lonely Kconfig file in this folder. Its config switches CONFIG_RAS_CEC and CONFIG_RAS_CEC_DEBUG are only used in code that resides in drivers/ras/, so those Kconfig switches should better reside in drivers/ras/, too. Thus move the contents of arch/x86/ras/ into drivers/ras/Kconfig now. Signed-off-by: Thomas Huth Signed-off-by: Borislav Petkov (AMD) Link: https://patch.msgid.link/20260410122748.29978-1-thuth@redhat.com --- arch/x86/ras/Kconfig | 23 ----------------------- drivers/ras/Kconfig | 24 +++++++++++++++++++++++- 2 files changed, 23 insertions(+), 24 deletions(-) delete mode 100644 arch/x86/ras/Kconfig diff --git a/arch/x86/ras/Kconfig b/arch/x86/ras/Kconfig deleted file mode 100644 index 7488c715427e..000000000000 --- a/arch/x86/ras/Kconfig +++ /dev/null @@ -1,23 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -config RAS_CEC - bool "Correctable Errors Collector" - depends on X86_MCE && MEMORY_FAILURE && DEBUG_FS - help - This is a small cache which collects correctable memory errors per 4K - page PFN and counts their repeated occurrence. Once the counter for a - PFN overflows, we try to soft-offline that page as we take it to mean - that it has reached a relatively high error count and would probably - be best if we don't use it anymore. - - Bear in mind that this is absolutely useless if your platform doesn't - have ECC DIMMs and doesn't have DRAM ECC checking enabled in the BIOS. - -config RAS_CEC_DEBUG - bool "CEC debugging machinery" - default n - depends on RAS_CEC - help - Add extra files to (debugfs)/ras/cec to test the correctable error - collector feature. "pfn" is a writable file that allows user to - simulate an error in a particular page frame. "array" is a read-only - file that dumps out the current state of all pages logged so far. diff --git a/drivers/ras/Kconfig b/drivers/ras/Kconfig index fc4f4bb94a4c..070e17639faa 100644 --- a/drivers/ras/Kconfig +++ b/drivers/ras/Kconfig @@ -31,7 +31,29 @@ menuconfig RAS if RAS -source "arch/x86/ras/Kconfig" +config RAS_CEC + bool "Correctable Errors Collector" + depends on X86_MCE && MEMORY_FAILURE && DEBUG_FS + help + This is a small cache which collects correctable memory errors per 4K + page PFN and counts their repeated occurrence. Once the counter for a + PFN overflows, we try to soft-offline that page as we take it to mean + that it has reached a relatively high error count and would probably + be best if we don't use it anymore. + + Bear in mind that this is absolutely useless if your platform doesn't + have ECC DIMMs and doesn't have DRAM ECC checking enabled in the BIOS. + +config RAS_CEC_DEBUG + bool "CEC debugging machinery" + default n + depends on RAS_CEC + help + Add extra files to (debugfs)/ras/cec to test the correctable error + collector feature. "pfn" is a writable file that allows user to + simulate an error in a particular page frame. "array" is a read-only + file that dumps out the current state of all pages logged so far. + source "drivers/ras/amd/atl/Kconfig" config RAS_FMPM From edeed06c2ba0de3203d14f8b94c392760968666d Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Thu, 19 Jun 2025 23:56:39 -0700 Subject: [PATCH 07/12] x86/platform/quark: Fix kernel-doc warnings in imr.c Fix all kernel-doc warnings in imr.c: imr.c:300: warning: Function parameter or struct member 'rmask' not described in 'imr_add_range' imr.c:300: warning: Function parameter or struct member 'wmask' not described in 'imr_add_range' imr.c:300: warning: Excess function parameter 'read_mask' description in 'imr_add_range' imr.c:300: warning: Excess function parameter 'write_mask' description in 'imr_add_range' Fixes: 28a375df16c2 ("x86/intel/quark: Add Isolated Memory Regions for Quark X1000") Signed-off-by: Randy Dunlap Signed-off-by: Borislav Petkov (AMD) Link: https://patch.msgid.link/20250620065639.3348609-1-rdunlap@infradead.org --- arch/x86/platform/intel-quark/imr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/platform/intel-quark/imr.c b/arch/x86/platform/intel-quark/imr.c index ee25b032c0b3..9238473842c7 100644 --- a/arch/x86/platform/intel-quark/imr.c +++ b/arch/x86/platform/intel-quark/imr.c @@ -291,8 +291,8 @@ static inline int imr_address_overlap(phys_addr_t addr, struct imr_regs *imr) * * @base: physical base address of region aligned to 1KiB. * @size: physical size of region in bytes must be aligned to 1KiB. - * @read_mask: read access mask. - * @write_mask: write access mask. + * @rmask: read access mask. + * @wmask: write access mask. * @return: zero on success or negative value indicating error. */ int imr_add_range(phys_addr_t base, size_t size, From db55777feca876dd2a548a232abeb3ddd8986a09 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Hannotier?= Date: Sat, 4 Jul 2026 14:55:15 +0200 Subject: [PATCH 08/12] Documentation/arch/x86/amd-memory-encryption.rst: Fix typo MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The MSR address has one 0 too many: 0xc00100010 → 0xc0010010. Signed-off-by: Cédric Hannotier Signed-off-by: Borislav Petkov (AMD) Link: https://patch.msgid.link/20260704125516.49944-1-hannotiercedric@gmail.com --- Documentation/arch/x86/amd-memory-encryption.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/arch/x86/amd-memory-encryption.rst b/Documentation/arch/x86/amd-memory-encryption.rst index bd840df708ea..92edb26a50d2 100644 --- a/Documentation/arch/x86/amd-memory-encryption.rst +++ b/Documentation/arch/x86/amd-memory-encryption.rst @@ -53,7 +53,7 @@ CPUID function 0x8000001f reports information related to SME:: system physical addresses, not guest physical addresses) -If support for SME is present, MSR 0xc00100010 (MSR_AMD64_SYSCFG) can be used to +If support for SME is present, MSR 0xc0010010 (MSR_AMD64_SYSCFG) can be used to determine if SME is enabled and/or to enable memory encryption:: 0xc0010010: From 7bdcb5b3a9c5ea63aaea75adfc1ffd30dee969f0 Mon Sep 17 00:00:00 2001 From: "Borislav Petkov (AMD)" Date: Fri, 19 Jun 2026 21:37:57 -0700 Subject: [PATCH 09/12] x86/boot/compressed/head_64.S: Clean up SEV-related comments Move the comment about setting the encryption mask above the line which does that and, especially, inside the ifdeffery, where it belongs. Move comments on top of the code lines they refer to and not on the side, which impairs readability. No functional changes. Signed-off-by: Borislav Petkov (AMD) Signed-off-by: Ingo Molnar Reviewed-by: Tom Lendacky Link: https://patch.msgid.link/20260620043757.347076-1-bp@kernel.org --- arch/x86/boot/compressed/head_64.S | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S index d9dab940ff62..1aca51390f73 100644 --- a/arch/x86/boot/compressed/head_64.S +++ b/arch/x86/boot/compressed/head_64.S @@ -172,19 +172,23 @@ SYM_FUNC_START(startup_32) /* * Build early 4G boot pagetable */ - /* - * If SEV is active then set the encryption mask in the page tables. - * This will ensure that when the kernel is copied and decompressed - * it will be done so encrypted. - */ xorl %edx, %edx #ifdef CONFIG_AMD_MEM_ENCRYPT call get_sev_encryption_bit xorl %edx, %edx testl %eax, %eax jz 1f - subl $32, %eax /* Encryption bit is always above bit 31 */ - bts %eax, %edx /* Set encryption mask for page tables */ + + /* Encryption bit is always above bit 31 */ + subl $32, %eax + + /* + * If SEV is active then set the encryption mask in the page tables. + * This will ensure that when the kernel is copied and decompressed it + * will be done so encrypted. + */ + bts %eax, %edx + /* * Set MSR_AMD64_SEV_ENABLED_BIT in sev_status so that * startup32_check_sev_cbit() will do a check. sev_enable() will From cdb4d57c3e497fe99a9ffa54f085b75130b12b5a Mon Sep 17 00:00:00 2001 From: Melody Wang Date: Wed, 8 Jul 2026 01:21:17 +0000 Subject: [PATCH 10/12] x86/apic: Ensure ICR register write value is handled as 32 bits The low 32-bit ICR data is prepared by __prepare_ICR(), which returns a 32-bit value. However, when this value is assigned to a new variable, it's easy to mistakenly declare that variable with a different width. To avoid this class of mistakes, use __prepare_ICR() directly as the function argument instead of storing its result in an intermediate variable. This also shaves off a bunch of lines in the code. There should be no functionality change resulting from this. Signed-off-by: Melody Wang Signed-off-by: Borislav Petkov (AMD) Acked-by: Thomas Gleixner Link: https://patch.msgid.link/20260708012117.177959-1-huibo.wang@amd.com --- arch/x86/kernel/apic/local.h | 4 +--- arch/x86/kernel/apic/x2apic_phys.c | 4 +--- arch/x86/kernel/apic/x2apic_savic.c | 5 +---- 3 files changed, 3 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/apic/local.h b/arch/x86/kernel/apic/local.h index 998efd442063..090dd71837aa 100644 --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -44,9 +44,7 @@ static inline unsigned int __prepare_ICR(unsigned int shortcut, int vector, #ifdef CONFIG_X86_X2APIC static inline void __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int dest) { - unsigned long cfg = __prepare_ICR(0, vector, dest); - - native_x2apic_icr_write(cfg, apicid); + native_x2apic_icr_write(__prepare_ICR(0, vector, dest), apicid); } #endif diff --git a/arch/x86/kernel/apic/x2apic_phys.c b/arch/x86/kernel/apic/x2apic_phys.c index 10f79026e8e3..090647cc5a78 100644 --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -85,11 +85,9 @@ static void static void __x2apic_send_IPI_shorthand(int vector, u32 which) { - unsigned long cfg = __prepare_ICR(which, vector, 0); - /* x2apic MSRs are special and need a special fence: */ weak_wrmsr_fence(); - native_x2apic_icr_write(cfg, 0); + native_x2apic_icr_write(__prepare_ICR(which, vector, 0), 0); } void x2apic_send_IPI_allbutself(int vector) diff --git a/arch/x86/kernel/apic/x2apic_savic.c b/arch/x86/kernel/apic/x2apic_savic.c index dbc5678bc3b6..4bc6d7e018a5 100644 --- a/arch/x86/kernel/apic/x2apic_savic.c +++ b/arch/x86/kernel/apic/x2apic_savic.c @@ -243,10 +243,7 @@ static void savic_write(u32 reg, u32 data) static void send_ipi(u32 dest, unsigned int vector, unsigned int dsh) { - unsigned int icr_low; - - icr_low = __prepare_ICR(dsh, vector, APIC_DEST_PHYSICAL); - savic_icr_write(icr_low, dest); + savic_icr_write(__prepare_ICR(dsh, vector, APIC_DEST_PHYSICAL), dest); } static void savic_send_ipi(int cpu, int vector) From b096d79bc1eed9eda57c12ccd76d6797cdba4cf2 Mon Sep 17 00:00:00 2001 From: Tim Wiederhake Date: Mon, 29 Jun 2026 19:37:59 +0200 Subject: [PATCH 11/12] x86/msr: Document the I/O-like write semantics in the msr driver Explain why msr_write() does not advance the index. [ bp: Massage commit message. ] Signed-off-by: Tim Wiederhake Signed-off-by: Borislav Petkov (AMD) Link: https://patch.msgid.link/20260629173759.1770596-1-twiederh@redhat.com --- arch/x86/kernel/msr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/kernel/msr.c b/arch/x86/kernel/msr.c index 34bdb752f892..eb988df22521 100644 --- a/arch/x86/kernel/msr.c +++ b/arch/x86/kernel/msr.c @@ -13,6 +13,9 @@ * and then read/write in chunks of 8 bytes. A larger size means multiple * reads or writes of the same register. * + * Writing the same register multiple times can be useful for MSRs with + * I/O-like semantics, e.g. a virtual MSR that accepts logging information. + * * This driver uses /dev/cpu/%d/msr where %d is the minor number, and on * an SMP box will direct the access to CPU %d. */ From 10b45e63a5b010be59ecbd2e437744adb12f838a Mon Sep 17 00:00:00 2001 From: Thorsten Blum Date: Tue, 30 Jun 2026 10:30:30 +0200 Subject: [PATCH 12/12] x86/cpu: Remove unnecessary __maybe_unused annotations Remove __maybe_unused from variables and functions that are referenced unconditionally. Signed-off-by: Thorsten Blum Signed-off-by: Borislav Petkov (AMD) Link: https://patch.msgid.link/20260630083031.683508-2-thorsten.blum@linux.dev --- arch/x86/kernel/cpu/common.c | 2 +- arch/x86/kernel/cpu/microcode/amd.c | 3 +-- arch/x86/kernel/cpu/topology_common.c | 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index a3df21d26460..63cab0554bc6 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1651,7 +1651,7 @@ static inline bool parse_set_clear_cpuid(char *arg, bool set) int taint = 0; while (arg) { - bool found __maybe_unused = false; + bool found = false; unsigned int bit; opt = strsep(&arg, ","); diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c index 531dfb771c8b..6cdc410e7547 100644 --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -136,8 +136,7 @@ struct cont_desc { * Microcode patch container file is prepended to the initrd in cpio * format. See Documentation/arch/x86/microcode.rst */ -static const char -ucode_path[] __maybe_unused = "kernel/x86/microcode/AuthenticAMD.bin"; +static const char ucode_path[] = "kernel/x86/microcode/AuthenticAMD.bin"; /* * This is CPUID(1).EAX on the BSP. It is used in two ways: diff --git a/arch/x86/kernel/cpu/topology_common.c b/arch/x86/kernel/cpu/topology_common.c index cf7513416b70..f0b0a91fcf0f 100644 --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -62,7 +62,7 @@ const char *get_topology_cpu_type_name(struct cpuinfo_x86 *c) } } -static unsigned int __maybe_unused parse_num_cores_legacy(struct cpuinfo_x86 *c) +static unsigned int parse_num_cores_legacy(struct cpuinfo_x86 *c) { struct { u32 cache_type : 5,