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dt-bindings: arm: tegra: pmc: Improve property descriptions
Reformat the description of various properties to make them more consistent with existing ones. Make use of json-schema's ability to provide a description for individual list items to make improve the documentation further. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding
parent
0bb80ecc33
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bbcab224f9
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@ -26,12 +26,10 @@ properties:
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clock-names:
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items:
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# Tegra clock of the same name
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- const: pclk
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# 32 KHz clock input
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- const: clk32k_in
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description:
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Must includes entries pclk and clk32k_in.
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pclk is the Tegra clock of that name and clk32k_in is 32KHz clock
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input to Tegra.
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clocks:
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maxItems: 2
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@ -41,105 +39,103 @@ properties:
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'#clock-cells':
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const: 1
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description:
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Tegra PMC has clk_out_1, clk_out_2, and clk_out_3.
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PMC also has blink control which allows 32Khz clock output to
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Tegra blink pad.
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Consumer of PMC clock should specify the desired clock by having
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the clock ID in its "clocks" phandle cell with pmc clock provider.
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See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC
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clock IDs.
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description: |
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Tegra PMC has clk_out_1, clk_out_2, and clk_out_3. PMC also has blink
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control which allows 32Khz clock output to Tegra blink pad.
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Consumer of PMC clock should specify the desired clock by having the
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clock ID in its "clocks" phandle cell with PMC clock provider. See
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include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC clock IDs.
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'#interrupt-cells':
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const: 2
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description:
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Specifies number of cells needed to encode an interrupt source.
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The value must be 2.
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description: Specifies number of cells needed to encode an interrupt
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source.
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interrupt-controller: true
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nvidia,invert-interrupt:
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$ref: /schemas/types.yaml#/definitions/flag
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description: Inverts the PMU interrupt signal.
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The PMU is an external Power Management Unit, whose interrupt output
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signal is fed into the PMC. This signal is optionally inverted, and
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then fed into the ARM GIC. The PMC is not involved in the detection
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or handling of this interrupt signal, merely its inversion.
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description: Inverts the PMU interrupt signal. The PMU is an external Power
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Management Unit, whose interrupt output signal is fed into the PMC. This
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signal is optionally inverted, and then fed into the ARM GIC. The PMC is
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not involved in the detection or handling of this interrupt signal,
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merely its inversion.
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nvidia,core-power-req-active-high:
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$ref: /schemas/types.yaml#/definitions/flag
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description: Core power request active-high.
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description: core power request active-high
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nvidia,sys-clock-req-active-high:
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$ref: /schemas/types.yaml#/definitions/flag
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description: System clock request active-high.
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description: system clock request active-high
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nvidia,combined-power-req:
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$ref: /schemas/types.yaml#/definitions/flag
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description: combined power request for CPU and Core.
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description: combined power request for CPU and core
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nvidia,cpu-pwr-good-en:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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CPU power good signal from external PMIC to PMC is enabled.
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description: CPU power good signal from external PMIC to PMC is enabled
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nvidia,suspend-mode:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 2]
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description:
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The suspend mode that the platform should use.
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Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh
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Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh
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Mode 2 is for LP2, CPU voltage off
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description: the suspend mode that the platform should use
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oneOf:
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- description: LP0, CPU + Core voltage off and DRAM in self-refresh
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const: 0
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- description: LP1, CPU voltage off and DRAM in self-refresh
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const: 1
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- description: LP2, CPU voltage off
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const: 2
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nvidia,cpu-pwr-good-time:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: CPU power good time in uSec.
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description: CPU power good time in microseconds
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nvidia,cpu-pwr-off-time:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: CPU power off time in uSec.
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description: CPU power off time in microseconds
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nvidia,core-pwr-good-time:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description:
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<Oscillator-stable-time Power-stable-time>
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Core power good time in uSec.
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description: core power good time in microseconds
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items:
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- description: oscillator stable time
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- description: power stable time
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nvidia,core-pwr-off-time:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Core power off time in uSec.
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description: core power off time in microseconds
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nvidia,lp0-vec:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description:
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<start length> Starting address and length of LP0 vector.
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The LP0 vector contains the warm boot code that is executed
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by AVP when resuming from the LP0 state.
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The AVP (Audio-Video Processor) is an ARM7 processor and
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always being the first boot processor when chip is power on
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or resume from deep sleep mode. When the system is resumed
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from the deep sleep mode, the warm boot code will restore
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some PLLs, clocks and then brings up CPU0 for resuming the
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system.
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description: |
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Starting address and length of LP0 vector. The LP0 vector contains the
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warm boot code that is executed by AVP when resuming from the LP0 state.
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The AVP (Audio-Video Processor) is an ARM7 processor and always being
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the first boot processor when chip is power on or resume from deep sleep
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mode. When the system is resumed from the deep sleep mode, the warm boot
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code will restore some PLLs, clocks and then brings up CPU0 for resuming
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the system.
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items:
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- description: starting address of LP0 vector
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- description: length of LP0 vector
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core-supply:
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description:
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Phandle to voltage regulator connected to the SoC Core power rail.
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description: phandle to voltage regulator connected to the SoC core power
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rail
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core-domain:
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type: object
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description: |
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The vast majority of hardware blocks of Tegra SoC belong to a
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Core power domain, which has a dedicated voltage rail that powers
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the blocks.
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description: The vast majority of hardware blocks of Tegra SoC belong to a
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core power domain, which has a dedicated voltage rail that powers the
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blocks.
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properties:
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operating-points-v2:
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description:
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Should contain level, voltages and opp-supported-hw property.
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The supported-hw is a bitfield indicating SoC speedo or process
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ID mask.
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description: Should contain level, voltages and opp-supported-hw
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property. The supported-hw is a bitfield indicating SoC speedo or
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process ID mask.
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"#power-domain-cells":
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const: 0
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@ -152,37 +148,32 @@ properties:
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i2c-thermtrip:
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type: object
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description:
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On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists,
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hardware-triggered thermal reset will be enabled.
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description: On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode
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exists, hardware-triggered thermal reset will be enabled.
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properties:
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nvidia,i2c-controller-id:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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ID of I2C controller to send poweroff command to PMU.
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Valid values are described in section 9.2.148
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"APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference
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Manual.
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description: ID of I2C controller to send poweroff command to PMU.
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Valid values are described in section 9.2.148 "APBDEV_PMC_SCRATCH53_0"
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of the Tegra K1 Technical Reference Manual.
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nvidia,bus-addr:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Bus address of the PMU on the I2C bus.
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description: bus address of the PMU on the I2C bus
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nvidia,reg-addr:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: PMU I2C register address to issue poweroff command.
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description: PMU I2C register address to issue poweroff command
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nvidia,reg-data:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Poweroff command to write to PMU.
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description: power-off command to write to PMU
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nvidia,pinmux-id:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Pinmux used by the hardware when issuing Poweroff command.
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Defaults to 0. Valid values are described in section 12.5.2
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"Pinmux Support" of the Tegra4 Technical Reference Manual.
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description: Pinmux used by the hardware when issuing power-off command.
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Defaults to 0. Valid values are described in section 12.5.2 "Pinmux
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Support" of the Tegra4 Technical Reference Manual.
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required:
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- nvidia,i2c-controller-id
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@ -195,41 +186,44 @@ properties:
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powergates:
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type: object
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description: |
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This node contains a hierarchy of power domain nodes, which should
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match the powergates on the Tegra SoC. Each powergate node
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represents a power-domain on the Tegra SoC that can be power-gated
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by the Tegra PMC.
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Hardware blocks belonging to a power domain should contain
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"power-domains" property that is a phandle pointing to corresponding
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powergate node.
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The name of the powergate node should be one of the below. Note that
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not every powergate is applicable to all Tegra devices and the following
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list shows which powergates are applicable to which devices.
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Please refer to Tegra TRM for mode details on the powergate nodes to
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use for each power-gate block inside Tegra.
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Name Description Devices Applicable
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3d 3D Graphics Tegra20/114/124/210
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3d0 3D Graphics 0 Tegra30
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3d1 3D Graphics 1 Tegra30
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aud Audio Tegra210
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dfd Debug Tegra210
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dis Display A Tegra114/124/210
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disb Display B Tegra114/124/210
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heg 2D Graphics Tegra30/114/124/210
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iram Internal RAM Tegra124/210
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mpe MPEG Encode All
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nvdec NVIDIA Video Decode Engine Tegra210
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nvjpg NVIDIA JPEG Engine Tegra210
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pcie PCIE Tegra20/30/124/210
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sata SATA Tegra30/124/210
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sor Display interfaces Tegra124/210
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ve2 Video Encode Engine 2 Tegra210
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venc Video Encode Engine All
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vdec Video Decode Engine Tegra20/30/114/124
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vic Video Imaging Compositor Tegra124/210
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xusba USB Partition A Tegra114/124/210
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xusbb USB Partition B Tegra114/124/210
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xusbc USB Partition C Tegra114/124/210
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This node contains a hierarchy of power domain nodes, which should match
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the powergates on the Tegra SoC. Each powergate node represents a power-
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domain on the Tegra SoC that can be power-gated by the Tegra PMC.
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Hardware blocks belonging to a power domain should contain "power-domains"
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property that is a phandle pointing to corresponding powergate node.
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The name of the powergate node should be one of the below. Note that not
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every powergate is applicable to all Tegra devices and the following list
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shows which powergates are applicable to which devices.
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Please refer to Tegra TRM for mode details on the powergate nodes to use
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for each power-gate block inside Tegra.
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Name Description Devices Applicable
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--------------------------------------------------------------
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3d 3D Graphics Tegra20/114/124/210
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3d0 3D Graphics 0 Tegra30
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3d1 3D Graphics 1 Tegra30
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aud Audio Tegra210
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dfd Debug Tegra210
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dis Display A Tegra114/124/210
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disb Display B Tegra114/124/210
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heg 2D Graphics Tegra30/114/124/210
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iram Internal RAM Tegra124/210
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mpe MPEG Encode All
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nvdec NVIDIA Video Decode Engine Tegra210
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nvjpg NVIDIA JPEG Engine Tegra210
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pcie PCIE Tegra20/30/124/210
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sata SATA Tegra30/124/210
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sor Display interfaces Tegra124/210
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ve2 Video Encode Engine 2 Tegra210
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venc Video Encode Engine All
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vdec Video Decode Engine Tegra20/30/114/124
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vic Video Imaging Compositor Tegra124/210
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xusba USB Partition A Tegra114/124/210
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xusbb USB Partition B Tegra114/124/210
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xusbc USB Partition C Tegra114/124/210
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patternProperties:
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"^[a-z0-9]+$":
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