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arm64: dts: qcom: sm6350: Set up DDR & L3 scaling
Add the CPU OPP tables including core frequency and L3 bus frequency. The L3 throughput values were chosen by studying the frequencies available in HW LUT and picking the highest one that's less than the CPU frequency. DDR clock rates come from the vendor kernel. Available values from the HW LUT: 300000000 556800000 652800000 806400000 844800000 940800000 1132800000 1209600000 1286400000 1401600000 1459200000 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230104171643.1004054-3-konrad.dybcio@linaro.org
This commit is contained in:
Konrad Dybcio
Bjorn Andersson
parent
e17a806571
commit
bba952275b
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@ -8,6 +8,8 @@
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/dma/qcom-gpi.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,osm-l3.h>
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#include <dt-bindings/interconnect/qcom,sm6350.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/mailbox/qcom-ipcc.h>
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@ -47,6 +49,10 @@ CPU0: cpu@0 {
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dynamic-power-coefficient = <100>;
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next-level-cache = <&L2_0>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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operating-points-v2 = <&cpu0_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
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&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
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#cooling-cells = <2>;
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L2_0: l2-cache {
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compatible = "cache";
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@ -68,6 +74,10 @@ CPU1: cpu@100 {
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dynamic-power-coefficient = <100>;
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next-level-cache = <&L2_100>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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operating-points-v2 = <&cpu0_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
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&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
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#cooling-cells = <2>;
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L2_100: l2-cache {
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compatible = "cache";
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@ -85,6 +95,10 @@ CPU2: cpu@200 {
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dynamic-power-coefficient = <100>;
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next-level-cache = <&L2_200>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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operating-points-v2 = <&cpu0_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
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&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
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#cooling-cells = <2>;
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L2_200: l2-cache {
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compatible = "cache";
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@ -102,6 +116,10 @@ CPU3: cpu@300 {
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dynamic-power-coefficient = <100>;
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next-level-cache = <&L2_300>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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operating-points-v2 = <&cpu0_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
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&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
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#cooling-cells = <2>;
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L2_300: l2-cache {
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compatible = "cache";
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@ -119,6 +137,10 @@ CPU4: cpu@400 {
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dynamic-power-coefficient = <100>;
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next-level-cache = <&L2_400>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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operating-points-v2 = <&cpu0_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
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&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
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#cooling-cells = <2>;
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L2_400: l2-cache {
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compatible = "cache";
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@ -136,6 +158,10 @@ CPU5: cpu@500 {
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dynamic-power-coefficient = <100>;
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next-level-cache = <&L2_500>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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operating-points-v2 = <&cpu0_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
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&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
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#cooling-cells = <2>;
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L2_500: l2-cache {
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compatible = "cache";
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@ -154,6 +180,10 @@ CPU6: cpu@600 {
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dynamic-power-coefficient = <703>;
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next-level-cache = <&L2_600>;
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qcom,freq-domain = <&cpufreq_hw 1>;
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operating-points-v2 = <&cpu6_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
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&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
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#cooling-cells = <2>;
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L2_600: l2-cache {
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compatible = "cache";
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@ -171,6 +201,10 @@ CPU7: cpu@700 {
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dynamic-power-coefficient = <703>;
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next-level-cache = <&L2_700>;
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qcom,freq-domain = <&cpufreq_hw 1>;
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operating-points-v2 = <&cpu6_opp_table>;
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interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
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&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
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<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
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#cooling-cells = <2>;
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L2_700: l2-cache {
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compatible = "cache";
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@ -229,6 +263,112 @@ memory@80000000 {
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reg = <0x0 0x80000000 0x0 0x0>;
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};
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cpu0_opp_table: opp-table-cpu0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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/* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */
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opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>;
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};
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opp-576000000 {
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opp-hz = /bits/ 64 <576000000>;
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opp-peak-kBps = <(547000 * 4 * 2 * 2) (556800 * 16 * 2)>;
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};
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opp-768000000 {
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opp-hz = /bits/ 64 <768000000>;
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opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>;
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};
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opp-1017600000 {
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opp-hz = /bits/ 64 <1017600000>;
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opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>;
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};
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opp-1248000000 {
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opp-hz = /bits/ 64 <1248000000>;
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opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>;
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};
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opp-1324800000 {
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opp-hz = /bits/ 64 <1324800000>;
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opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1286400 * 16 * 2)>;
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};
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opp-1516800000 {
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opp-hz = /bits/ 64 <1516800000>;
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opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
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};
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opp-1612800000 {
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opp-hz = /bits/ 64 <1612800000>;
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opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
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};
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opp-1708800000 {
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opp-hz = /bits/ 64 <1708800000>;
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opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
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};
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};
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cpu6_opp_table: opp-table-cpu6 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>;
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};
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opp-787200000 {
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opp-hz = /bits/ 64 <787200000>;
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opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>;
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};
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opp-979200000 {
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opp-hz = /bits/ 64 <979200000>;
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opp-peak-kBps = <(768000 * 4 * 2 * 2) (940800 * 16 * 2)>;
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};
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opp-1036800000 {
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opp-hz = /bits/ 64 <1036800000>;
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opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>;
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};
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opp-1248000000 {
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opp-hz = /bits/ 64 <1248000000>;
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opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>;
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};
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opp-1401600000 {
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opp-hz = /bits/ 64 <1401600000>;
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opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1401600 * 16 * 2)>;
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};
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opp-1555200000 {
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opp-hz = /bits/ 64 <1555200000>;
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opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
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};
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opp-1766400000 {
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opp-hz = /bits/ 64 <1766400000>;
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opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
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};
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opp-1900800000 {
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opp-hz = /bits/ 64 <1900800000>;
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opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
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};
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opp-2073600000 {
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opp-hz = /bits/ 64 <2073600000>;
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opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
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};
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>;
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@ -14,3 +14,22 @@
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&CPU5 { compatible = "qcom,kryo570"; };
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&CPU6 { compatible = "qcom,kryo570"; };
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&CPU7 { compatible = "qcom,kryo570"; };
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&cpu0_opp_table {
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opp-1804800000 {
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opp-hz = /bits/ 64 <1804800000>;
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opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
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};
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};
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&cpu6_opp_table {
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opp-2131200000 {
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opp-hz = /bits/ 64 <2131200000>;
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opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
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};
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opp-2208000000 {
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opp-hz = /bits/ 64 <2208000000>;
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opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
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};
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};
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