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amd-drm-fixes-6.17-2025-07-31:
amdgpu: - DSC divide by 0 fix - clang fix - DC debugfs fix - Userq fixes - Avoid extra evict-restore with KFD - Backlight fix - Documentation fix - RAS fix - Add new kicker handling - DSC fix for DCN 3.1.4 - PSR fix - Atomic fix - DC reset fixes - DCN 3.0.1 fix - MMHUB client mapping fix -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQQgO5Idg2tXNTSZAr293/aFa7yZ2AUCaIvAzgAKCRC93/aFa7yZ 2IQwAQCh7VV32tbpsQVlfimhz2nVIFyXEKjBAhYtGUkB6JuCEAD8CnQV88UG+7X7 O4wCP/kMngoOr0K1BbUVbX1H3krMVQc= =r7iI -----END PGP SIGNATURE----- Merge tag 'amd-drm-fixes-6.17-2025-07-31' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-fixes-6.17-2025-07-31: amdgpu: - DSC divide by 0 fix - clang fix - DC debugfs fix - Userq fixes - Avoid extra evict-restore with KFD - Backlight fix - Documentation fix - RAS fix - Add new kicker handling - DSC fix for DCN 3.1.4 - PSR fix - Atomic fix - DC reset fixes - DCN 3.0.1 fix - MMHUB client mapping fix Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://lore.kernel.org/r/20250731191916.255648-1-alexander.deucher@amd.com
This commit is contained in:
Dave Airlie
commit
bb9ddd99a7
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@ -883,6 +883,7 @@ struct amdgpu_mqd_prop {
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uint64_t csa_addr;
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uint64_t fence_address;
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bool tmz_queue;
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bool kernel_queue;
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};
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struct amdgpu_mqd {
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@ -459,7 +459,7 @@ static u32 amdgpu_cper_ring_get_ent_sz(struct amdgpu_ring *ring, u64 pos)
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void amdgpu_cper_ring_write(struct amdgpu_ring *ring, void *src, int count)
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{
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u64 pos, wptr_old, rptr = *ring->rptr_cpu_addr & ring->ptr_mask;
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u64 pos, wptr_old, rptr;
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int rec_cnt_dw = count >> 2;
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u32 chunk, ent_sz;
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u8 *s = (u8 *)src;
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@ -472,9 +472,11 @@ void amdgpu_cper_ring_write(struct amdgpu_ring *ring, void *src, int count)
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return;
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}
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wptr_old = ring->wptr;
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mutex_lock(&ring->adev->cper.ring_lock);
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wptr_old = ring->wptr;
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rptr = *ring->rptr_cpu_addr & ring->ptr_mask;
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while (count) {
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ent_sz = amdgpu_cper_ring_get_ent_sz(ring, ring->wptr);
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chunk = umin(ent_sz, count);
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@ -719,6 +719,7 @@ static void amdgpu_ring_to_mqd_prop(struct amdgpu_ring *ring,
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prop->eop_gpu_addr = ring->eop_gpu_addr;
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prop->use_doorbell = ring->use_doorbell;
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prop->doorbell_index = ring->doorbell_index;
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prop->kernel_queue = true;
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/* map_queues packet doesn't need activate the queue,
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* so only kiq need set this field.
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@ -32,6 +32,7 @@
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static const struct kicker_device kicker_device_list[] = {
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{0x744B, 0x00},
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{0x7551, 0xC8}
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};
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static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr)
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@ -2414,13 +2414,11 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
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*/
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long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
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{
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timeout = dma_resv_wait_timeout(vm->root.bo->tbo.base.resv,
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DMA_RESV_USAGE_BOOKKEEP,
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true, timeout);
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timeout = drm_sched_entity_flush(&vm->immediate, timeout);
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if (timeout <= 0)
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return timeout;
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return dma_fence_wait_timeout(vm->last_unlocked, true, timeout);
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return drm_sched_entity_flush(&vm->delayed, timeout);
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}
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static void amdgpu_vm_destroy_task_info(struct kref *kref)
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@ -79,6 +79,7 @@ MODULE_FIRMWARE("amdgpu/gc_12_0_1_pfp.bin");
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MODULE_FIRMWARE("amdgpu/gc_12_0_1_me.bin");
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MODULE_FIRMWARE("amdgpu/gc_12_0_1_mec.bin");
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MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc.bin");
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MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc_kicker.bin");
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MODULE_FIRMWARE("amdgpu/gc_12_0_1_toc.bin");
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static const struct amdgpu_hwip_reg_entry gc_reg_list_12_0[] = {
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@ -586,7 +587,7 @@ static int gfx_v12_0_init_toc_microcode(struct amdgpu_device *adev, const char *
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static int gfx_v12_0_init_microcode(struct amdgpu_device *adev)
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{
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char ucode_prefix[15];
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char ucode_prefix[30];
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int err;
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const struct rlc_firmware_header_v2_0 *rlc_hdr;
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uint16_t version_major;
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@ -613,9 +614,14 @@ static int gfx_v12_0_init_microcode(struct amdgpu_device *adev)
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amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK);
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if (!amdgpu_sriov_vf(adev)) {
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err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
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AMDGPU_UCODE_REQUIRED,
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"amdgpu/%s_rlc.bin", ucode_prefix);
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if (amdgpu_is_kicker_fw(adev))
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err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
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AMDGPU_UCODE_REQUIRED,
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"amdgpu/%s_rlc_kicker.bin", ucode_prefix);
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else
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err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
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AMDGPU_UCODE_REQUIRED,
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"amdgpu/%s_rlc.bin", ucode_prefix);
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if (err)
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goto out;
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rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
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@ -34,12 +34,13 @@
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MODULE_FIRMWARE("amdgpu/gc_12_0_0_imu.bin");
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MODULE_FIRMWARE("amdgpu/gc_12_0_1_imu.bin");
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MODULE_FIRMWARE("amdgpu/gc_12_0_1_imu_kicker.bin");
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#define TRANSFER_RAM_MASK 0x001c0000
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static int imu_v12_0_init_microcode(struct amdgpu_device *adev)
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{
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char ucode_prefix[15];
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char ucode_prefix[30];
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int err;
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const struct imu_firmware_header_v1_0 *imu_hdr;
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struct amdgpu_firmware_info *info = NULL;
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@ -47,8 +48,12 @@ static int imu_v12_0_init_microcode(struct amdgpu_device *adev)
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DRM_DEBUG("\n");
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amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
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err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, AMDGPU_UCODE_REQUIRED,
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"amdgpu/%s_imu.bin", ucode_prefix);
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if (amdgpu_is_kicker_fw(adev))
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err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, AMDGPU_UCODE_REQUIRED,
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"amdgpu/%s_imu_kicker.bin", ucode_prefix);
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else
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err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, AMDGPU_UCODE_REQUIRED,
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"amdgpu/%s_imu.bin", ucode_prefix);
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if (err)
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goto out;
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@ -362,7 +367,7 @@ static void program_imu_rlc_ram(struct amdgpu_device *adev,
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static void imu_v12_0_program_rlc_ram(struct amdgpu_device *adev)
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{
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u32 reg_data, size = 0;
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const u32 *data;
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const u32 *data = NULL;
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int r = -EINVAL;
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WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX, 0x2);
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@ -37,39 +37,31 @@
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static const char *mmhub_client_ids_v4_1_0[][2] = {
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[0][0] = "VMC",
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[4][0] = "DCEDMC",
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[5][0] = "DCEVGA",
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[6][0] = "MP0",
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[7][0] = "MP1",
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[8][0] = "MPIO",
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[16][0] = "HDP",
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[17][0] = "LSDMA",
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[18][0] = "JPEG",
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[19][0] = "VCNU0",
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[21][0] = "VSCH",
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[22][0] = "VCNU1",
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[23][0] = "VCN1",
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[32+20][0] = "VCN0",
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[2][1] = "DBGUNBIO",
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[16][0] = "LSDMA",
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[17][0] = "JPEG",
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[19][0] = "VCNU",
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[22][0] = "VSCH",
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[23][0] = "HDP",
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[32+23][0] = "VCNRD",
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[3][1] = "DCEDWB",
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[4][1] = "DCEDMC",
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[5][1] = "DCEVGA",
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[6][1] = "MP0",
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[7][1] = "MP1",
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[8][1] = "MPIO",
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[10][1] = "DBGU0",
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[11][1] = "DBGU1",
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[12][1] = "DBGU2",
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[13][1] = "DBGU3",
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[12][1] = "DBGUNBIO",
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[14][1] = "XDP",
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[15][1] = "OSSSYS",
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[16][1] = "HDP",
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[17][1] = "LSDMA",
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[18][1] = "JPEG",
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[19][1] = "VCNU0",
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[20][1] = "VCN0",
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[21][1] = "VSCH",
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[22][1] = "VCNU1",
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[23][1] = "VCN1",
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[16][1] = "LSDMA",
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[17][1] = "JPEG",
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[18][1] = "VCNWR",
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[19][1] = "VCNU",
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[22][1] = "VSCH",
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[23][1] = "HDP",
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};
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static uint32_t mmhub_v4_1_0_get_invalidate_req(unsigned int vmid,
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@ -34,7 +34,9 @@
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MODULE_FIRMWARE("amdgpu/psp_14_0_2_sos.bin");
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MODULE_FIRMWARE("amdgpu/psp_14_0_2_ta.bin");
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MODULE_FIRMWARE("amdgpu/psp_14_0_3_sos.bin");
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MODULE_FIRMWARE("amdgpu/psp_14_0_3_sos_kicker.bin");
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MODULE_FIRMWARE("amdgpu/psp_14_0_3_ta.bin");
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MODULE_FIRMWARE("amdgpu/psp_14_0_3_ta_kicker.bin");
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MODULE_FIRMWARE("amdgpu/psp_14_0_5_toc.bin");
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MODULE_FIRMWARE("amdgpu/psp_14_0_5_ta.bin");
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@ -3398,8 +3398,10 @@ static int dm_resume(struct amdgpu_ip_block *ip_block)
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link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
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r = dm_dmub_hw_init(adev);
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if (r)
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if (r) {
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drm_err(adev_to_drm(adev), "DMUB interface failed to initialize: status=%d\n", r);
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return r;
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}
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dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);
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dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
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@ -4983,9 +4985,9 @@ amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)
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caps = &dm->backlight_caps[aconnector->bl_idx];
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if (get_brightness_range(caps, &min, &max)) {
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if (power_supply_is_system_supplied() > 0)
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props.brightness = (max - min) * DIV_ROUND_CLOSEST(caps->ac_level, 100);
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props.brightness = DIV_ROUND_CLOSEST((max - min) * caps->ac_level, 100);
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else
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props.brightness = (max - min) * DIV_ROUND_CLOSEST(caps->dc_level, 100);
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props.brightness = DIV_ROUND_CLOSEST((max - min) * caps->dc_level, 100);
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/* min is zero, so max needs to be adjusted */
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props.max_brightness = max - min;
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drm_dbg(drm, "Backlight caps: min: %d, max: %d, ac %d, dc %d\n", min, max,
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@ -5410,7 +5412,8 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
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static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
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{
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drm_atomic_private_obj_fini(&dm->atomic_obj);
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if (dm->atomic_obj.state)
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drm_atomic_private_obj_fini(&dm->atomic_obj);
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}
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||||
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||||
/******************************************************************************
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|
|
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|||
|
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@ -3988,7 +3988,7 @@ static int capabilities_show(struct seq_file *m, void *unused)
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|
||||
struct hubbub *hubbub = dc->res_pool->hubbub;
|
||||
|
||||
if (hubbub->funcs->get_mall_en)
|
||||
if (hubbub && hubbub->funcs->get_mall_en)
|
||||
hubbub->funcs->get_mall_en(hubbub, &mall_in_use);
|
||||
|
||||
if (dc->cap_funcs.get_subvp_en)
|
||||
|
|
|
|||
|
|
@ -119,8 +119,10 @@ bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
|
|||
psr_config.allow_multi_disp_optimizations =
|
||||
(amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT);
|
||||
|
||||
if (!psr_su_set_dsc_slice_height(dc, link, stream, &psr_config))
|
||||
return false;
|
||||
if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
|
||||
if (!psr_su_set_dsc_slice_height(dc, link, stream, &psr_config))
|
||||
return false;
|
||||
}
|
||||
|
||||
ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);
|
||||
|
||||
|
|
|
|||
|
|
@ -5443,7 +5443,8 @@ bool dc_update_planes_and_stream(struct dc *dc,
|
|||
else
|
||||
ret = update_planes_and_stream_v2(dc, srf_updates,
|
||||
surface_count, stream, stream_update);
|
||||
if (ret && dc->ctx->dce_version >= DCN_VERSION_3_2)
|
||||
if (ret && (dc->ctx->dce_version >= DCN_VERSION_3_2 ||
|
||||
dc->ctx->dce_version == DCN_VERSION_3_01))
|
||||
clear_update_flags(srf_updates, surface_count, stream);
|
||||
|
||||
return ret;
|
||||
|
|
|
|||
|
|
@ -377,10 +377,16 @@ static bool setup_engine(
|
|||
}
|
||||
|
||||
/**
|
||||
* cntl_stuck_hw_workaround - Workaround for I2C engine stuck state
|
||||
* @dce_i2c_hw: Pointer to dce_i2c_hw structure
|
||||
*
|
||||
* If we boot without an HDMI display, the I2C engine does not get initialized
|
||||
* correctly. One of its symptoms is that SW_USE_I2C does not get cleared after
|
||||
* acquire, so that after setting SW_DONE_USING_I2C on release, the engine gets
|
||||
* acquire. After setting SW_DONE_USING_I2C on release, the engine gets
|
||||
* immediately reacquired by SW, preventing DMUB from using it.
|
||||
*
|
||||
* This function checks the I2C arbitration status and applies a release
|
||||
* workaround if necessary.
|
||||
*/
|
||||
static void cntl_stuck_hw_workaround(struct dce_i2c_hw *dce_i2c_hw)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -152,7 +152,7 @@ uint32_t dc_bandwidth_in_kbps_from_timing(
|
|||
}
|
||||
|
||||
/* Forward Declerations */
|
||||
static unsigned int get_min_slice_count_for_odm(
|
||||
static unsigned int get_min_dsc_slice_count_for_odm(
|
||||
const struct display_stream_compressor *dsc,
|
||||
const struct dsc_enc_caps *dsc_enc_caps,
|
||||
const struct dc_crtc_timing *timing);
|
||||
|
|
@ -466,7 +466,7 @@ bool dc_dsc_compute_bandwidth_range(
|
|||
struct dc_dsc_bw_range *range)
|
||||
{
|
||||
bool is_dsc_possible = false;
|
||||
unsigned int min_slice_count;
|
||||
unsigned int min_dsc_slice_count;
|
||||
struct dsc_enc_caps dsc_enc_caps;
|
||||
struct dsc_enc_caps dsc_common_caps;
|
||||
struct dc_dsc_config config = {0};
|
||||
|
|
@ -478,14 +478,14 @@ bool dc_dsc_compute_bandwidth_range(
|
|||
|
||||
get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz);
|
||||
|
||||
min_slice_count = get_min_slice_count_for_odm(dsc, &dsc_enc_caps, timing);
|
||||
min_dsc_slice_count = get_min_dsc_slice_count_for_odm(dsc, &dsc_enc_caps, timing);
|
||||
|
||||
is_dsc_possible = intersect_dsc_caps(dsc_sink_caps, &dsc_enc_caps,
|
||||
timing->pixel_encoding, &dsc_common_caps);
|
||||
|
||||
if (is_dsc_possible)
|
||||
is_dsc_possible = setup_dsc_config(dsc_sink_caps, &dsc_enc_caps, 0, timing,
|
||||
&options, link_encoding, min_slice_count, &config);
|
||||
&options, link_encoding, min_dsc_slice_count, &config);
|
||||
|
||||
if (is_dsc_possible)
|
||||
is_dsc_possible = decide_dsc_bandwidth_range(min_bpp_x16, max_bpp_x16,
|
||||
|
|
@ -593,14 +593,12 @@ static void build_dsc_enc_caps(
|
|||
|
||||
struct dc *dc;
|
||||
|
||||
memset(&single_dsc_enc_caps, 0, sizeof(struct dsc_enc_caps));
|
||||
|
||||
if (!dsc || !dsc->ctx || !dsc->ctx->dc || !dsc->funcs->dsc_get_single_enc_caps)
|
||||
return;
|
||||
|
||||
dc = dsc->ctx->dc;
|
||||
|
||||
if (!dc->clk_mgr || !dc->clk_mgr->funcs->get_max_clock_khz || !dc->res_pool)
|
||||
if (!dc->clk_mgr || !dc->clk_mgr->funcs->get_max_clock_khz || !dc->res_pool || dc->debug.disable_dsc)
|
||||
return;
|
||||
|
||||
/* get max DSCCLK from clk_mgr */
|
||||
|
|
@ -634,7 +632,7 @@ static inline uint32_t dsc_div_by_10_round_up(uint32_t value)
|
|||
return (value + 9) / 10;
|
||||
}
|
||||
|
||||
static unsigned int get_min_slice_count_for_odm(
|
||||
static unsigned int get_min_dsc_slice_count_for_odm(
|
||||
const struct display_stream_compressor *dsc,
|
||||
const struct dsc_enc_caps *dsc_enc_caps,
|
||||
const struct dc_crtc_timing *timing)
|
||||
|
|
@ -651,6 +649,10 @@ static unsigned int get_min_slice_count_for_odm(
|
|||
}
|
||||
}
|
||||
|
||||
/* validate parameters */
|
||||
if (max_dispclk_khz == 0 || dsc_enc_caps->max_slice_width == 0)
|
||||
return 1;
|
||||
|
||||
/* consider minimum odm slices required due to
|
||||
* 1) display pipe throughput (dispclk)
|
||||
* 2) max image width per slice
|
||||
|
|
@ -669,13 +671,12 @@ static void get_dsc_enc_caps(
|
|||
{
|
||||
memset(dsc_enc_caps, 0, sizeof(struct dsc_enc_caps));
|
||||
|
||||
if (!dsc)
|
||||
if (!dsc || !dsc->ctx || !dsc->ctx->dc || dsc->ctx->dc->debug.disable_dsc)
|
||||
return;
|
||||
|
||||
/* check if reported cap global or only for a single DCN DSC enc */
|
||||
if (dsc->funcs->dsc_get_enc_caps) {
|
||||
if (!dsc->ctx->dc->debug.disable_dsc)
|
||||
dsc->funcs->dsc_get_enc_caps(dsc_enc_caps, pixel_clock_100Hz);
|
||||
dsc->funcs->dsc_get_enc_caps(dsc_enc_caps, pixel_clock_100Hz);
|
||||
} else {
|
||||
build_dsc_enc_caps(dsc, dsc_enc_caps);
|
||||
}
|
||||
|
|
@ -1295,10 +1296,10 @@ bool dc_dsc_compute_config(
|
|||
{
|
||||
bool is_dsc_possible = false;
|
||||
struct dsc_enc_caps dsc_enc_caps;
|
||||
unsigned int min_slice_count;
|
||||
unsigned int min_dsc_slice_count;
|
||||
get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz);
|
||||
|
||||
min_slice_count = get_min_slice_count_for_odm(dsc, &dsc_enc_caps, timing);
|
||||
min_dsc_slice_count = get_min_dsc_slice_count_for_odm(dsc, &dsc_enc_caps, timing);
|
||||
|
||||
is_dsc_possible = setup_dsc_config(dsc_sink_caps,
|
||||
&dsc_enc_caps,
|
||||
|
|
@ -1306,7 +1307,7 @@ bool dc_dsc_compute_config(
|
|||
timing,
|
||||
options,
|
||||
link_encoding,
|
||||
min_slice_count,
|
||||
min_dsc_slice_count,
|
||||
dsc_cfg);
|
||||
return is_dsc_possible;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -926,6 +926,7 @@ static const struct dc_debug_options debug_defaults_drv = {
|
|||
.seamless_boot_odm_combine = true,
|
||||
.enable_legacy_fast_update = true,
|
||||
.using_dml2 = false,
|
||||
.disable_dsc_power_gate = true,
|
||||
};
|
||||
|
||||
static const struct dc_panel_config panel_config_defaults = {
|
||||
|
|
|
|||
|
|
@ -62,13 +62,14 @@ const int decoded_link_width[8] = {0, 1, 2, 4, 8, 12, 16, 32};
|
|||
|
||||
MODULE_FIRMWARE("amdgpu/smu_14_0_2.bin");
|
||||
MODULE_FIRMWARE("amdgpu/smu_14_0_3.bin");
|
||||
MODULE_FIRMWARE("amdgpu/smu_14_0_3_kicker.bin");
|
||||
|
||||
#define ENABLE_IMU_ARG_GFXOFF_ENABLE 1
|
||||
|
||||
int smu_v14_0_init_microcode(struct smu_context *smu)
|
||||
{
|
||||
struct amdgpu_device *adev = smu->adev;
|
||||
char ucode_prefix[15];
|
||||
char ucode_prefix[30];
|
||||
int err = 0;
|
||||
const struct smc_firmware_header_v1_0 *hdr;
|
||||
const struct common_firmware_header *header;
|
||||
|
|
@ -79,8 +80,12 @@ int smu_v14_0_init_microcode(struct smu_context *smu)
|
|||
return 0;
|
||||
|
||||
amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
|
||||
err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
|
||||
"amdgpu/%s.bin", ucode_prefix);
|
||||
if (amdgpu_is_kicker_fw(adev))
|
||||
err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
|
||||
"amdgpu/%s_kicker.bin", ucode_prefix);
|
||||
else
|
||||
err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
|
||||
"amdgpu/%s.bin", ucode_prefix);
|
||||
if (err)
|
||||
goto out;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user