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s390/setup: Recognize sequential instruction fetching facility
When sequential instruction fetching facility is present, certain guarantees are provided for code patching. In particular, atomic overwrites within 8 aligned bytes is safe from an instruction-fetching point of view. Reviewed-by: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: Vasily Gorbik <gor@linux.ibm.com>
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@ -34,6 +34,7 @@
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#define MACHINE_FLAG_SCC BIT(17)
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#define MACHINE_FLAG_PCI_MIO BIT(18)
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#define MACHINE_FLAG_RDP BIT(19)
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#define MACHINE_FLAG_SEQ_INSN BIT(20)
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#define LPP_MAGIC BIT(31)
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#define LPP_PID_MASK _AC(0xffffffff, UL)
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@ -95,6 +96,7 @@ extern unsigned long mio_wb_bit_mask;
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#define MACHINE_HAS_SCC (get_lowcore()->machine_flags & MACHINE_FLAG_SCC)
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#define MACHINE_HAS_PCI_MIO (get_lowcore()->machine_flags & MACHINE_FLAG_PCI_MIO)
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#define MACHINE_HAS_RDP (get_lowcore()->machine_flags & MACHINE_FLAG_RDP)
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#define MACHINE_HAS_SEQ_INSN (get_lowcore()->machine_flags & MACHINE_FLAG_SEQ_INSN)
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/*
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* Console mode. Override with conmode=
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@ -268,6 +268,8 @@ static __init void detect_machine_facilities(void)
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}
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if (test_facility(194))
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get_lowcore()->machine_flags |= MACHINE_FLAG_RDP;
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if (test_facility(85))
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get_lowcore()->machine_flags |= MACHINE_FLAG_SEQ_INSN;
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}
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static inline void save_vector_registers(void)
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